JAJSOZ4A June   2023  – June 2024 TPS6521905

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  System Control Thresholds
    6. 5.6  BUCK1 Converter
    7. 5.7  BUCK2, BUCK3 Converter
    8. 5.8  General Purpose LDOs (LDO1, LDO2)
    9. 5.9  General Purpose LDOs (LDO3, LDO4)
    10. 5.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
    11. 5.11 Voltage and Temperature Monitors
    12. 5.12 I2C Interface
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power-Up Sequencing
      2. 6.3.2  Power-Down Sequencing
      3. 6.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 6.3.4  Reset to SoC (nRSTOUT)
      5. 6.3.5  Buck Converters (Buck1, Buck2, and Buck3)
      6. 6.3.6  Linear Regulators (LDO1 through LDO4)
      7. 6.3.7  Interrupt Pin (nINT)
      8. 6.3.8  PWM/PFM and Low Power Modes (MODE/STBY)
      9. 6.3.9  PWM/PFM and Reset (MODE/RESET)
      10. 6.3.10 Voltage Select pin (VSEL_SD/VSEL_DDR)
      11. 6.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
      12. 6.3.12 I2C-Compatible Interface
        1. 6.3.12.1 Data Validity
        2. 6.3.12.2 Start and Stop Conditions
        3. 6.3.12.3 Transferring Data
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes of Operation
        1. 6.4.1.1 OFF State
        2. 6.4.1.2 INITIALIZE State
        3. 6.4.1.3 ACTIVE State
        4. 6.4.1.4 STBY State
        5. 6.4.1.5 Fault Handling
    5. 6.5 Multi-PMIC Operation
    6. 6.6 NVM Programming
      1. 6.6.1 TPS6521905 default NVM settings
      2. 6.6.2 NVM programming in Initialize State
      3. 6.6.3 NVM Programming in Active State
    7. 6.7 User Registers
    8. 6.8 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application Example
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Buck1, Buck2, Buck3 Design Procedure
        2. 7.2.3.2 LDO1, LDO2 Design Procedure
        3. 7.2.3.3 LDO3, LDO4 Design Procedure
        4. 7.2.3.4 VSYS, VDD1P8
        5. 7.2.3.5 Digital Signals Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 System Control Thresholds

Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the AGND ground of the device.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics
4.1.1 VSYS Operating Input Voltage 2.5 5.5 V
4.1.2 VSYSPOR_Rising VSYS POR rising threshold Measured on VSYS pin, untrimmed 2.2 2.5 V
4.1.3 VSYSUVLO_Falling VSYS UVLO falling threshold Measured on VSYS pin, trimmed 2.175 2.25 V
4.1.4 VSYSPOR_Hyst VSYS UVLO/POR hysteresis VSYSPOR_Rising_untrimmed-VSYSUVLO_Falling_trimmed 130 mV
4.1.5 VVSYS_OVP_Rise VSYS OVP rising threshold, trimmed Measured on VSYS pin, trimmed 5.9 6.1 V
4.1.6 VVSYS_OVP_Fall VSYS OVP falling threshold, trimmed Measured on VSYS pin, trimmed 5.7 5.95 V
4.1.7 VVSYS_OVP_Hyst VSYS OVP hysteresis VSYSOVP_Rising_trimmed-VSYSOVP_falling_trimmed 100 140 180 mV
4.1.8 VVDD1P8 VDD1P8 voltage 1.7 1.8 1.9 V
4.2.1a IINITIALIZE Current Consumption in INITIALIZE state,
at 25°C		 Combined Current from VSYS and PVIN_x pins. VSYS = PVIN_Bx = PVIN_LDOx = 5V. All Monitors are off.
TJ = 25°C		 15 22 µA
4.2.1b IINITIALIZE Current Consumption in INITIALIZE state,
40°C to 125°C		 Combined Current from VSYS and PVIN_x pins. VSYS = PVIN_Bx = PVIN_LDOx = 5V. All Monitors are off.
TJ = -40°C to 125°C		 15 35 µA
4.2.2a IACTIVE ACTIVE State Current Consumption, all rails on, at 25°C Combined Current from VSYS and PVIN_x pins. VSYS = PVIN_Bx = PVIN_LDOx = 5V. All Outputs are on, all LDOs in LDO-mode, Bucks in PFM mode. No Load.
TJ = 25°C		 250 290 µA
4.2.2b IACTIVE ACTIVE State Current Consumption, all rails on, 
-40°C to 125°C		 Combined Current from VSYS and PVIN_x pins. VSYS = PVIN_Bx = PVIN_LDOx = 5V. All Outputs are on, all LDOs in LDO-mode, Bucks in PFM mode. No Load.
TJ = -40°C to 125°C		 250 430 µA
4.2.3a ISTBY STBY State Current Consumption, only LDO1 on, at 25°C Combined Current from VSYS and PVIN_x pins. VSYS = PVIN_Bx = PVIN_LDOx = 5V. Only LDO1 on in LDO-mode. No Load. 
TJ = 25°C		 105 125 µA
4.2.3b ISTBY STBY State Current Consumption, only LDO1 on, -40°C to 125°C Combined Current from VSYS and PVIN_x pins. VSYS = PVIN_Bx = PVIN_LDOx = 5V. Only LDO1 on in LDO-mode. No Load. 
TJ = -40°C to 125°C		 105 150 µA
4.2.4a ISTBY STBY State Current Consumption, all rails on, VMON on at 25°C Combined Current from VSYS and PVIN_x pins. VSYS = PVIN_Bx = PVIN_LDOx = 5V. All Outputs are on, all LDOs in LDO-mode, Bucks in PFM mode. No Load. Output-voltage Monitors are on, VSYS-monitor (UV/OVP) are on.
TJ = 25°C		 250 290 µA
4.2.4b ISTBY STBY State Current Consumption, all rails on, VMON on,
-40°C to 125°C		 Combined Current from VSYS and PVIN_x pins. VSYS = PVIN_Bx = PVIN_LDOx = 5V. All Outputs are on, all LDOs in LDO-mo, Bucks in PFM mode. No Load. Output-voltage Monitors are on, VSYS-monitor (UV/OVP) are on.
TJ = -40°C to 125°C		 250 430 µA
Timing Requirements
4.3.1 tOFF_TO_INIT Time from VSYS passing VSYS_POR until entering INITIALIZE state, including EEPROM-read, ready for ON-request Time from VSYS passing VSYS_POR until entering INITIALIZE state. On request execution gated by HOT and RV 3.2 ms
4.3.2a tTIMEOUT_UV UV-detection in case a rail does not reach UV-threshold during ramp-up end of tRAMP + sample- and deglitch time
4.3.2b tTIMEOUT_UV_SLOT Timeout in case a rail does not reach UV-threshold during ramp-up, applicable in Multi-PMIC-configuration only end of slot-extension time (3ms, 4ms or 13ms)
4.3.3 tTIMEOUT_Discharge Timeout in case a rail cannot be discharged when transitioning from STBY to ACTIVE state 72 80 88 ms