JAJSOR4B December 2022 – June 2024 TPS65220
PRODUCTION DATA
The default I2C1 7-bit device address of the TPS65220 is set to 0x30 (0b0110000 in binary), but can be changed if needed, for example for multi-PMIC-operation.
The I2C-compatible synchronous serial interface provides access to the configurable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the devices connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). Every device on the bus is assigned a unique address and acts as either a controller or a target depending on whether it generates or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor placed somewhere on the line and remain HIGH even when the bus is idle. The TPS65220 supports standard mode (100 kHz), fast mode (400 kHz), and fast mode plus (1 MHz) when VIO is 3.3 V or 1.8 V.