JAJSOR4B December 2022 – June 2024 TPS65220
PRODUCTION DATA
Table 6-7 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in Table 6-7 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | TI_DEV_ID | Device ID | Go |
1h | NVM_ID | NVM configuration ID | Go |
2h | ENABLE_CTRL | Enable/Push-Button/Vsense Control | Go |
3h | BUCKS_CONFIG | Generic Buck Configuration | Go |
4h | LDO4_VOUT | LDO4 Configuration | Go |
5h | LDO3_VOUT | LDO3 Configuration | Go |
6h | LDO2_VOUT | LDO2 Configuration | Go |
7h | LDO1_VOUT | LDO1 Configuration | Go |
8h | BUCK3_VOUT | Buck3 Configuration | Go |
9h | BUCK2_VOUT | Buck2 Configuration | Go |
Ah | BUCK1_VOUT | Buck1 Configuration | Go |
Bh | LDO4_SEQUENCE_SLOT | Power-up and -down slot for LDO4 | Go |
Ch | LDO3_SEQUENCE_SLOT | Power-up and -down slot for LDO3 | Go |
Dh | LDO2_SEQUENCE_SLOT | Power-up and -down slot for LDO2 | Go |
Eh | LDO1_SEQUENCE_SLOT | Power-up and -down slot for LDO10 | Go |
Fh | BUCK3_SEQUENCE_SLOT | Power-up and -down slot for Buck3 | Go |
10h | BUCK2_SEQUENCE_SLOT | Power-up and -down slot for Buck2 | Go |
11h | BUCK1_SEQUENCE_SLOT | Power-up and -down slot for Buck1 | Go |
12h | nRST_SEQUENCE_SLOT | Power-up and -down slot for nRSTOUT | Go |
13h | GPIO_SEQUENCE_SLOT | Power-up and -down slot for GPIO | Go |
14h | GPO2_SEQUENCE_SLOT | Power-up and -down slot for GPO2 | Go |
15h | GPO1_SEQUENCE_SLOT | Power-up and -down slot for GPO1 | Go |
16h | POWER_UP_SLOT_DURATION_1 | Slot-duration at power-up for slot0-3 | Go |
17h | POWER_UP_SLOT_DURATION_2 | Slot-duration at power-up for slot4-7 | Go |
18h | POWER_UP_SLOT_DURATION_3 | Slot-duration at power-up for slot8-11 | Go |
19h | POWER_UP_SLOT_DURATION_4 | Slot-duration at power-up for slot12-15 | Go |
1Ah | POWER_DOWN_SLOT_DURATION_1 | Slot-duration at power-down for slot0-3 | Go |
1Bh | POWER_DOWN_SLOT_DURATION_2 | Slot-duration at power-down for slot4-7 | Go |
1Ch | POWER_DOWN_SLOT_DURATION_3 | Slot-duration at power-down for slot8-11 | Go |
1Dh | POWER_DOWN_SLOT_DURATION_4 | Slot-duration at power-down for slot12-15 | Go |
1Eh | GENERAL_CONFIG | LDO-undervoltage and GPO-enable | Go |
1Fh | MFP_1_CONFIG | Multi-Function pin configuration1 | Go |
20h | MFP_2_CONFIG | Multi-Function pin configuration2 | Go |
21h | STBY_1_CONFIG | STBY configuration LDOs and Bucks | Go |
22h | STBY_2_CONFIG | STBY configuration GPIO and GPO | Go |
23h | OC_DEGL_CONFIG | Overcurrent deglitch time per rail | Go |
24h | INT_MASK_UV | Undervoltage fault-masking | Go |
25h | MASK_CONFIG | WARM-masking and mask-effect | Go |
26h | I2C_ADDRESS_REG | I2C-address | Go |
27h | USER_GENERAL_NVM_STORAGE_REG | User-configurable register (NVM-backed) | Go |
28h | MANUFACTURING_VER | Silicon-revision (read-only) | Go |
29h | MFP_CTRL | I2C-control for RESET, STBY, OFF | Go |
2Ah | DISCHARGE_CONFIG | Discharge configuration per rail | Go |
2Bh | INT_SOURCE | Interrupt source | Go |
2Ch | INT_LDO_3_4 | OC, UV, SCG for LDO3 and LDO4 | Go |
2Dh | INT_LDO_1_2 | OC, UV, SCG for LDO1 and LDO2 | Go |
2Eh | INT_BUCK_3 | OC, UV, SCG for Buck3 | Go |
2Fh | INT_BUCK_1_2 | OC, UV, SCG for Buck1 and Buck2 | Go |
30h | INT_SYSTEM | WARM and HOT fault flags | Go |
31h | INT_RV | RV (residual voltage) per rail | Go |
32h | INT_TIMEOUT_RV_SD | RV (residual voltage) per rail causing shut-down | Go |
33h | INT_PB | PushButton status and edge-detection | Go |
34h | USER_NVM_CMD_REG | DIY - user programming commands | Go |
35h | POWER_UP_STATUS_REG | Power-up status and STATE | Go |
36h | SPARE_2 | Spare register (not NVM-backed) | Go |
37h | SPARE_3 | Spare register (not NVM-backed) | Go |
41h | FACTORY_CONFIG_2 | Revision of NVM-configuration (read only) | Go |
Complex bit access types are encoded to fit into small table cells. Table 6-8 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
W1C | W 1C |
Write 1 to clear |
WSelfClrF | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
TI_DEV_ID is shown in Figure 6-18 and described in Table 6-9.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TI_DEVICE_ID | |||||||
R-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | TI_DEVICE_ID | R | X | TI_DEVICE_ID[7:6]: 0h = TA: -40°C to 105°C, TJ: -40°C to 125°C 2h = TA: -40°C to 125°C, TJ: -40°C to 150°C 3h = TA: -55°C to 125°C, TJ: -55°C to 150°C TI_DEVICE_ID[5:0]: Device GPN Note: This register can be programmed only by the manufacturer! Refer to Technical Reference Manual / User's Guide for specific numbering and associated configuration. (Default from NVM memory) |
NVM_ID is shown in Figure 6-19 and described in Table 6-10.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TI_NVM_ID | |||||||
R-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | TI_NVM_ID | R | X | NVM ID of the IC Note: This register can be programmed only by the manufacturer! Refer to Technical Reference Manual / User's Guide for specific numbering and associated configuration. (Default from NVM memory) |
ENABLE_CTRL is shown in Figure 6-20 and described in Table 6-11.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LDO4_EN | LDO3_EN | LDO2_EN | LDO1_EN | BUCK3_EN | BUCK2_EN | BUCK1_EN |
R-X | R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | R/W-X |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | X | Reserved |
6 | LDO4_EN | R/W | X | Enable LDO4 regulator (Default from NVM memory) 0h = Disabled 1h = Enabled |
5 | LDO3_EN | R/W | X | Enable LDO3 regulator (Default from NVM memory) 0h = Disabled 1h = Enabled |
4 | LDO2_EN | R/W | X | Enable LDO2 regulator (Default from NVM memory) 0h = Disabled 1h = Enabled |
3 | LDO1_EN | R/W | X | Enable LDO1 regulator (Default from NVM memory) 0h = Disabled 1h = Enabled |
2 | BUCK3_EN | R/W | X | Enable BUCK3 regulator (Default from NVM memory) 0h = Disabled 1h = Enabled |
1 | BUCK2_EN | R/W | X | Enable BUCK2 regulator (Default from NVM memory) 0h = Disabled 1h = Enabled |
0 | BUCK1_EN | R/W | X | Enable BUCK1 regulator (Default from NVM memory) 0h = Disabled 1h = Enabled |
BUCKS_CONFIG is shown in Figure 6-21 and described in Table 6-12.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER_NVM_SPARE_2 | USER_NVM_SPARE_1 | BUCK_SS_ENABLE | BUCK_FF_ENABLE | BUCK3_PHASE_CONFIG | BUCK2_PHASE_CONFIG | ||
R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | USER_NVM_SPARE_2 | R/W | X | Spare bit in user NVM space (Default from NVM memory) |
6 | USER_NVM_SPARE_1 | R/W | X | Spare bit in user NVM space (Default from NVM memory) |
5 | BUCK_SS_ENABLE | R/W | X | Spread spectrum enabled on Bucks (only applicable in
FF-mode) (Default from NVM memory) 0h = Spread spectrum disabled 1h = Spread spectrum enabled |
4 | BUCK_FF_ENABLE | R | X | All Bucks set into fixed frequency mode NOTE: MUST
NOT CHANGE AT ANY TIME! (Default from NVM memory) 0h = Quasi-fixed frequency mode 1h = Fixed frequency mode |
3-2 | BUCK3_PHASE_CONFIG | R/W | X | Phase of BUCK3 clock. Applicable if Bucks are
configured for fixed frequency. NOTE: ONLY CHANGE WHILE RAIL IS
DISABLED! (Default from NVM memory) 0h = 0 degrees 1h = 90 degrees 2h = 180 degrees 3h = 270 degrees |
1-0 | BUCK2_PHASE_CONFIG | R/W | X | Phase of BUCK2 clock. Applicable if Bucks are
configured for fixed frequency. NOTE: ONLY CHANGE WHILE RAIL IS
DISABLED! (Default from NVM memory) 0h = 0 degrees 1h = 90 degrees 2h = 180 degrees 3h = 270 degrees |
LDO4_VOUT is shown in Figure 6-22 and described in Table 6-13.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LDO4_SLOW_PU_RAMP | LDO4_LSW_CONFIG | LDO4_VSET | |||||
R/W-X | R/W-X | R/W-X | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | LDO4_SLOW_PU_RAMP | R/W | X | LDO4 Power-up ramp When set high, slows down the
power-up ramp to ~3ms. Cout max 30uF When set low, ramp time is
~660us. Cout max 15uF (Default from NVM memory) 0h = Fast ramp for power-up (~660us) 1h = Slow ramp for power-up (~3ms) |
6 | LDO4_LSW_CONFIG | R/W | X | LDO4 LDO or LSW Mode. NOTE: ONLY CHANGE WHILE RAIL IS
DISABLED! (Default from NVM memory) 0h = LDO Mode 1h = LSW Mode |
5-0 | LDO4_VSET | R/W | X | Voltage selection for LDO4. The output voltage range
is from 1.2V to 3.3V. (Default from NVM memory) 0h = 1.200V 1h = 1.200V 2h = 1.200V 3h = 1.200V 4h = 1.200V 5h = 1.200V 6h = 1.200V 7h = 1.200V 8h = 1.200V 9h = 1.200V Ah = 1.200V Bh = 1.200V Ch = 1.200V Dh = 1.250V Eh = 1.300V Fh = 1.350V 10h = 1.400V 11h = 1.450V 12h = 1.500V 13h = 1.550V 14h = 1.600V 15h = 1.650V 16h = 1.700V 17h = 1.750V 18h = 1.800V 19h = 1.850V 1Ah = 1.900V 1Bh = 1.950V 1Ch = 2.000V 1Dh = 2.050V 1Eh = 2.100V 1Fh = 2.150V 20h = 2.200V 21h = 2.250V 22h = 2.300V 23h = 2.350V 24h = 2.400V 25h = 2.450V 26h = 2.500V 27h = 2.550V 28h = 2.600V 29h = 2.650V 2Ah = 2.700V 2Bh = 2.750V 2Ch = 2.800V 2Dh = 2.850V 2Eh = 2.900V 2Fh = 2.950V 30h = 3.000V 31h = 3.050V 32h = 3.100V 33h = 3.150V 34h = 3.200V 35h = 3.250V 36h = 3.300V 37h = 3.300V 38h = 3.300V 39h = 3.300V 3Ah = 3.300V 3Bh = 3.300V 3Ch = 3.300V 3Dh = 3.300V 3Eh = 3.300V 3Fh = 3.300V |
LDO3_VOUT is shown in Figure 6-23 and described in Table 6-14.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LDO3_SLOW_PU_RAMP | LDO3_LSW_CONFIG | LDO3_VSET | |||||
R/W-X | R/W-X | R/W-X | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | LDO3_SLOW_PU_RAMP | R/W | X | LDO3 Power-up ramp When set high, slows down the
power-up ramp to ~3ms. Cout max 30uF When set low, ramp time is
~660us. Cout max 15uF (Default from NVM memory) 0h = Fast ramp for power-up (~660us) 1h = Slow ramp for power-up (~3ms) |
6 | LDO3_LSW_CONFIG | R/W | X | LDO3 LDO or LSW Mode. NOTE: ONLY CHANGE WHILE RAIL IS
DISABLED! (Default from NVM memory) 0h = LDO Mode 1h = LSW Mode |
5-0 | LDO3_VSET | R/W | X | Voltage selection for LDO3. The output voltage range
is from 1.2V to 3.3V. (Default from NVM memory) 0h = 1.200V 1h = 1.200V 2h = 1.200V 3h = 1.200V 4h = 1.200V 5h = 1.200V 6h = 1.200V 7h = 1.200V 8h = 1.200V 9h = 1.200V Ah = 1.200V Bh = 1.200V Ch = 1.200V Dh = 1.250V Eh = 1.300V Fh = 1.350V 10h = 1.400V 11h = 1.450V 12h = 1.500V 13h = 1.550V 14h = 1.600V 15h = 1.650V 16h = 1.700V 17h = 1.750V 18h = 1.800V 19h = 1.850V 1Ah = 1.900V 1Bh = 1.950V 1Ch = 2.000V 1Dh = 2.050V 1Eh = 2.100V 1Fh = 2.150V 20h = 2.200V 21h = 2.250V 22h = 2.300V 23h = 2.350V 24h = 2.400V 25h = 2.450V 26h = 2.500V 27h = 2.550V 28h = 2.600V 29h = 2.650V 2Ah = 2.700V 2Bh = 2.750V 2Ch = 2.800V 2Dh = 2.850V 2Eh = 2.900V 2Fh = 2.950V 30h = 3.000V 31h = 3.050V 32h = 3.100V 33h = 3.150V 34h = 3.200V 35h = 3.250V 36h = 3.300V 37h = 3.300V 38h = 3.300V 39h = 3.300V 3Ah = 3.300V 3Bh = 3.300V 3Ch = 3.300V 3Dh = 3.300V 3Eh = 3.300V 3Fh = 3.300V |
LDO2_VOUT is shown in Figure 6-24 and described in Table 6-15.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LDO2_LSW_CONFIG | LDO2_BYP_CONFIG | LDO2_VSET | |||||
R/W-X | R/W-X | R/W-X | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | LDO2_LSW_CONFIG | R/W | X | LDO2 LDO/Bypass or LSW Mode. NOTE: ONLY CHANGE WHILE
RAIL IS DISABLED! (Default from NVM memory) 0h = Not Applicable (LDO2 not configured as load-switch) 1h = LDO1 configured as Load-switch |
6 | LDO2_BYP_CONFIG | R/W | X | LDO2 LDO or Bypass Mode. (Default from NVM memory)
0h = LDO2 configured as LDO (only applicable if LDO2_LSW_CONFIG 0x0) 1h = LDO2 configured as Bypass (only applicable if LDO2_LSW_CONFIG 0x0) |
5-0 | LDO2_VSET | R/W | X | Voltage selection for LDO2. The output voltage range
is from 0.6V to 3.4V in LDO mode and 1.5V to 3.4V in bypass-mode.
(Default from NVM memory) 0h = 0.600V 1h = 0.650V 2h = 0.700V 3h = 0.750V 4h = 0.800V 5h = 0.850V 6h = 0.900V 7h = 0.950V 8h = 1.000V 9h = 1.050V Ah = 1.100V Bh = 1.150V Ch = 1.200V Dh = 1.250V Eh = 1.300V Fh = 1.350V 10h = 1.400V 11h = 1.450V 12h = 1.500V 13h = 1.550V 14h = 1.600V 15h = 1.650V 16h = 1.700V 17h = 1.750V 18h = 1.800V 19h = 1.850V 1Ah = 1.900V 1Bh = 1.950V 1Ch = 2.000V 1Dh = 2.050V 1Eh = 2.100V 1Fh = 2.150V 20h = 2.200V 21h = 2.250V 22h = 2.300V 23h = 2.350V 24h = 2.400V 25h = 2.450V 26h = 2.500V 27h = 2.550V 28h = 2.600V 29h = 2.650V 2Ah = 2.700V 2Bh = 2.750V 2Ch = 2.800V 2Dh = 2.850V 2Eh = 2.900V 2Fh = 2.950V 30h = 3.000V 31h = 3.050V 32h = 3.100V 33h = 3.150V 34h = 3.200V 35h = 3.250V 36h = 3.300V 37h = 3.350V 38h = 3.400V 39h = 3.400V 3Ah = 3.400V 3Bh = 3.400V 3Ch = 3.400V 3Dh = 3.400V 3Eh = 3.400V 3Fh = 3.400V |
LDO1_VOUT is shown in Figure 6-25 and described in Table 6-16.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LDO1_LSW_CONFIG | LDO1_BYP_CONFIG | LDO1_VSET | |||||
R/W-X | R/W-X | R/W-X | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | LDO1_LSW_CONFIG | R/W | X | LDO1 LDO/Bypass or LSW Mode. NOTE: ONLY CHANGE WHILE
RAIL IS DISABLED! (Default from NVM memory) 0h = Not Applicable (LDO1 not configured as load-switch) 1h = LDO1 configured as Load-switch |
6 | LDO1_BYP_CONFIG | R/W | X | LDO1 LDO or Bypass Mode. (Default from NVM memory)
0h = LDO1 configured as LDO (only applicable if LDO1_LSW_CONFIG 0x0) 1h = LDO1 configured as Bypass (only applicable if LDO1_LSW_CONFIG 0x0) |
5-0 | LDO1_VSET | R/W | X | Voltage selection for LDO1. The output voltage range
is from 0.6V to 3.4V in LDO-mode and 1.5V to 3.4V in bypass-mode.
(Default from NVM memory) 0h = 0.600V 1h = 0.650V 2h = 0.700V 3h = 0.750V 4h = 0.800V 5h = 0.850V 6h = 0.900V 7h = 0.950V 8h = 1.000V 9h = 1.050V Ah = 1.100V Bh = 1.150V Ch = 1.200V Dh = 1.250V Eh = 1.300V Fh = 1.350V 10h = 1.400V 11h = 1.450V 12h = 1.500V 13h = 1.550V 14h = 1.600V 15h = 1.650V 16h = 1.700V 17h = 1.750V 18h = 1.800V 19h = 1.850V 1Ah = 1.900V 1Bh = 1.950V 1Ch = 2.000V 1Dh = 2.050V 1Eh = 2.100V 1Fh = 2.150V 20h = 2.200V 21h = 2.250V 22h = 2.300V 23h = 2.350V 24h = 2.400V 25h = 2.450V 26h = 2.500V 27h = 2.550V 28h = 2.600V 29h = 2.650V 2Ah = 2.700V 2Bh = 2.750V 2Ch = 2.800V 2Dh = 2.850V 2Eh = 2.900V 2Fh = 2.950V 30h = 3.000V 31h = 3.050V 32h = 3.100V 33h = 3.150V 34h = 3.200V 35h = 3.250V 36h = 3.300V 37h = 3.350V 38h = 3.400V 39h = 3.400V 3Ah = 3.400V 3Bh = 3.400V 3Ch = 3.400V 3Dh = 3.400V 3Eh = 3.400V 3Fh = 3.400V |
BUCK3_VOUT is shown in Figure 6-26 and described in Table 6-17.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUCK3_BW_SEL | BUCK3_UV_THR_SEL | BUCK3_VSET | |||||
R/W-X | R/W-X | R/W-X | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | BUCK3_BW_SEL | R/W | X | BUCK3 Bandwidth selection. NOTE: ONLY CHANGE WHILE
RAIL IS DISABLED! (Default from NVM memory) 0h = low bandwidth 1h = high bandwidth |
6 | BUCK3_UV_THR_SEL | R/W | X | UV threshold selection for BUCK3. (Default from NVM
memory) 0h = -5% UV detection 1h = -10% UV detection |
5-0 | BUCK3_VSET | R/W | X | Voltage selection for BUCK3. The output voltage range
is from 0.6V to 3.4V. (Default from NVM memory) 0h = 0.600V 1h = 0.625V 2h = 0.650V 3h = 0.675V 4h = 0.700V 5h = 0.725V 6h = 0.750V 7h = 0.775V 8h = 0.800V 9h = 0.825V Ah = 0.850V Bh = 0.875V Ch = 0.900V Dh = 0.925V Eh = 0.950V Fh = 0.975V 10h = 1.000V 11h = 1.025V 12h = 1.050V 13h = 1.075V 14h = 1.100V 15h = 1.125V 16h = 1.150V 17h = 1.175V 18h = 1.200V 19h = 1.225V 1Ah = 1.250V 1Bh = 1.275V 1Ch = 1.300V 1Dh = 1.325V 1Eh = 1.350V 1Fh = 1.375V 20h = 1.400V 21h = 1.500V 22h = 1.600V 23h = 1.700V 24h = 1.800V 25h = 1.900V 26h = 2.000V 27h = 2.100V 28h = 2.200V 29h = 2.300V 2Ah = 2.400V 2Bh = 2.500V 2Ch = 2.600V 2Dh = 2.700V 2Eh = 2.800V 2Fh = 2.900V 30h = 3.000V 31h = 3.100V 32h = 3.200V 33h = 3.300V 34h = 3.400V 35h = 3.400V 36h = 3.400V 37h = 3.400V 38h = 3.400V 39h = 3.400V 3Ah = 3.400V 3Bh = 3.400V 3Ch = 3.400V 3Dh = 3.400V 3Eh = 3.400V 3Fh = 3.400V |
BUCK2_VOUT is shown in Figure 6-27 and described in Table 6-18.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUCK2_BW_SEL | BUCK2_UV_THR_SEL | BUCK2_VSET | |||||
R/W-X | R/W-X | R/W-X | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | BUCK2_BW_SEL | R/W | X | BUCK2 Bandwidth selection. NOTE: ONLY CHANGE WHILE
RAIL IS DISABLED! (Default from NVM memory) 0h = low bandwidth 1h = high bandwidth |
6 | BUCK2_UV_THR_SEL | R/W | X | UV threshold selection for BUCK2. (Default from NVM
memory) 0h = -5% UV detection 1h = -10% UV detection |
5-0 | BUCK2_VSET | R/W | X | Voltage selection for BUCK2. The output voltage range
is from 0.6V to 3.4V. (Default from NVM memory) 0h = 0.600V 1h = 0.625V 2h = 0.650V 3h = 0.675V 4h = 0.700V 5h = 0.725V 6h = 0.750V 7h = 0.775V 8h = 0.800V 9h = 0.825V Ah = 0.850V Bh = 0.875V Ch = 0.900V Dh = 0.925V Eh = 0.950V Fh = 0.975V 10h = 1.000V 11h = 1.025V 12h = 1.050V 13h = 1.075V 14h = 1.100V 15h = 1.125V 16h = 1.150V 17h = 1.175V 18h = 1.200V 19h = 1.225V 1Ah = 1.250V 1Bh = 1.275V 1Ch = 1.300V 1Dh = 1.325V 1Eh = 1.350V 1Fh = 1.375V 20h = 1.400V 21h = 1.500V 22h = 1.600V 23h = 1.700V 24h = 1.800V 25h = 1.900V 26h = 2.000V 27h = 2.100V 28h = 2.200V 29h = 2.300V 2Ah = 2.400V 2Bh = 2.500V 2Ch = 2.600V 2Dh = 2.700V 2Eh = 2.800V 2Fh = 2.900V 30h = 3.000V 31h = 3.100V 32h = 3.200V 33h = 3.300V 34h = 3.400V 35h = 3.400V 36h = 3.400V 37h = 3.400V 38h = 3.400V 39h = 3.400V 3Ah = 3.400V 3Bh = 3.400V 3Ch = 3.400V 3Dh = 3.400V 3Eh = 3.400V 3Fh = 3.400V |
BUCK1_VOUT is shown in Figure 6-28 and described in Table 6-19.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUCK1_BW_SEL | BUCK1_UV_THR_SEL | BUCK1_VSET | |||||
R/W-X | R/W-X | R/W-X | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | BUCK1_BW_SEL | R/W | X | BUCK1 Bandwidth selection. NOTE: ONLY CHANGE WHILE
RAIL IS DISABLED! (Default from NVM memory) 0h = low bandwidth 1h = high bandwidth |
6 | BUCK1_UV_THR_SEL | R/W | X | UV threshold selection for BUCK1. (Default from NVM
memory) 0h = -5% UV detection 1h = -10% UV detection |
5-0 | BUCK1_VSET | R/W | X | Voltage selection for BUCK1. The output voltage range
is from 0.6V to 3.4V. (Default from NVM memory) 0h = 0.600V 1h = 0.625V 2h = 0.650V 3h = 0.675V 4h = 0.700V 5h = 0.725V 6h = 0.750V 7h = 0.775V 8h = 0.800V 9h = 0.825V Ah = 0.850V Bh = 0.875V Ch = 0.900V Dh = 0.925V Eh = 0.950V Fh = 0.975V 10h = 1.000V 11h = 1.025V 12h = 1.050V 13h = 1.075V 14h = 1.100V 15h = 1.125V 16h = 1.150V 17h = 1.175V 18h = 1.200V 19h = 1.225V 1Ah = 1.250V 1Bh = 1.275V 1Ch = 1.300V 1Dh = 1.325V 1Eh = 1.350V 1Fh = 1.375V 20h = 1.400V 21h = 1.500V 22h = 1.600V 23h = 1.700V 24h = 1.800V 25h = 1.900V 26h = 2.000V 27h = 2.100V 28h = 2.200V 29h = 2.300V 2Ah = 2.400V 2Bh = 2.500V 2Ch = 2.600V 2Dh = 2.700V 2Eh = 2.800V 2Fh = 2.900V 30h = 3.000V 31h = 3.100V 32h = 3.200V 33h = 3.300V 34h = 3.400V 35h = 3.400V 36h = 3.400V 37h = 3.400V 38h = 3.400V 39h = 3.400V 3Ah = 3.400V 3Bh = 3.400V 3Ch = 3.400V 3Dh = 3.400V 3Eh = 3.400V 3Fh = 3.400V |
LDO4_SEQUENCE_SLOT is shown in Figure 6-29 and described in Table 6-20.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LDO4_SEQUENCE_ON_SLOT | LDO4_SEQUENCE_OFF_SLOT | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | LDO4_SEQUENCE_ON_SLOT | R/W | X | LDO4 slot number for power-up (Default from NVM
memory) 0h = slot 0 1h = slot 1 2h = slot 2 3h = slot 3 4h = slot 4 5h = slot 5 6h = slot 6 7h = slot 7 8h = slot 8 9h = slot 9 Ah = slot 10 Bh = slot 11 Ch = slot 12 Dh = slot 13 Eh = slot 14 Fh = slot 15 |
3-0 | LDO4_SEQUENCE_OFF_SLOT | R/W | X | LDO4 slot number for power-down (Default from NVM
memory) 0h = slot 0 1h = slot 1 2h = slot 2 3h = slot 3 4h = slot 4 5h = slot 5 6h = slot 6 7h = slot 7 8h = slot 8 9h = slot 9 Ah = slot 10 Bh = slot 11 Ch = slot 12 Dh = slot 13 Eh = slot 14 Fh = slot 15 |
LDO3_SEQUENCE_SLOT is shown in Figure 6-30 and described in Table 6-21.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LDO3_SEQUENCE_ON_SLOT | LDO3_SEQUENCE_OFF_SLOT | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | LDO3_SEQUENCE_ON_SLOT | R/W | X | LDO3 slot number for power-up (Default from NVM
memory) 0h = slot 0 1h = slot 1 2h = slot 2 3h = slot 3 4h = slot 4 5h = slot 5 6h = slot 6 7h = slot 7 8h = slot 8 9h = slot 9 Ah = slot 10 Bh = slot 11 Ch = slot 12 Dh = slot 13 Eh = slot 14 Fh = slot 15 |
3-0 | LDO3_SEQUENCE_OFF_SLOT | R/W | X | LDO3 slot number for power-down (Default from NVM
memory) 0h = slot 0 1h = slot 1 2h = slot 2 3h = slot 3 4h = slot 4 5h = slot 5 6h = slot 6 7h = slot 7 8h = slot 8 9h = slot 9 Ah = slot 10 Bh = slot 11 Ch = slot 12 Dh = slot 13 Eh = slot 14 Fh = slot 15 |
LDO2_SEQUENCE_SLOT is shown in Figure 6-31 and described in Table 6-22.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LDO2_SEQUENCE_ON_SLOT | LDO2_SEQUENCE_OFF_SLOT | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | LDO2_SEQUENCE_ON_SLOT | R/W | X | LDO2 slot number for power-up (Default from NVM
memory) 0h = slot 0 1h = slot 1 2h = slot 2 3h = slot 3 4h = slot 4 5h = slot 5 6h = slot 6 7h = slot 7 8h = slot 8 9h = slot 9 Ah = slot 10 Bh = slot 11 Ch = slot 12 Dh = slot 13 Eh = slot 14 Fh = slot 15 |
3-0 | LDO2_SEQUENCE_OFF_SLOT | R/W | X | LDO2 slot number for power-down (Default from NVM
memory) 0h = slot 0 1h = slot 1 2h = slot 2 3h = slot 3 4h = slot 4 5h = slot 5 6h = slot 6 7h = slot 7 8h = slot 8 9h = slot 9 Ah = slot 10 Bh = slot 11 Ch = slot 12 Dh = slot 13 Eh = slot 14 Fh = slot 15 |
LDO1_SEQUENCE_SLOT is shown in Figure 6-32 and described in Table 6-23.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LDO1_SEQUENCE_ON_SLOT | LDO1_SEQUENCE_OFF_SLOT | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | LDO1_SEQUENCE_ON_SLOT | R/W | X | LDO1 slot number for power-up (Default from NVM
memory) 0h = slot 0 1h = slot 1 2h = slot 2 3h = slot 3 4h = slot 4 5h = slot 5 6h = slot 6 7h = slot 7 8h = slot 8 9h = slot 9 Ah = slot 10 Bh = slot 11 Ch = slot 12 Dh = slot 13 Eh = slot 14 Fh = slot 15 |
3-0 | LDO1_SEQUENCE_OFF_SLOT | R/W | X | LDO1 slot number for power-down (Default from NVM
memory) 0h = slot 0 1h = slot 1 2h = slot 2 3h = slot 3 4h = slot 4 5h = slot 5 6h = slot 6 7h = slot 7 8h = slot 8 9h = slot 9 Ah = slot 10 Bh = slot 11 Ch = slot 12 Dh = slot 13 Eh = slot 14 Fh = slot 15 |
BUCK3_SEQUENCE_SLOT is shown in Figure 6-33 and described in Table 6-24.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUCK3_SEQUENCE_ON_SLOT | BUCK3_SEQUENCE_OFF_SLOT | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | BUCK3_SEQUENCE_ON_SLOT | R/W | X | BUCK3 slot number for power-up (Default from NVM
memory) 0h = slot 0 1h = slot 1 2h = slot 2 3h = slot 3 4h = slot 4 5h = slot 5 6h = slot 6 7h = slot 7 8h = slot 8 9h = slot 9 Ah = slot 10 Bh = slot 11 Ch = slot 12 Dh = slot 13 Eh = slot 14 Fh = slot 15 |
3-0 | BUCK3_SEQUENCE_OFF_SLOT | R/W | X | BUCK3 slot number for power-down (Default from NVM
memory) 0h = slot 0 1h = slot 1 2h = slot 2 3h = slot 3 4h = slot 4 5h = slot 5 6h = slot 6 7h = slot 7 8h = slot 8 9h = slot 9 Ah = slot 10 Bh = slot 11 Ch = slot 12 Dh = slot 13 Eh = slot 14 Fh = slot 15 |
BUCK2_SEQUENCE_SLOT is shown in Figure 6-34 and described in Table 6-25.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUCK2_SEQUENCE_ON_SLOT | BUCK2_SEQUENCE_OFF_SLOT | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | BUCK2_SEQUENCE_ON_SLOT | R/W | X | BUCK2 Slot number for power-up (Default from NVM
memory) 0h = slot 0 1h = slot 1 2h = slot 2 3h = slot 3 4h = slot 4 5h = slot 5 6h = slot 6 7h = slot 7 8h = slot 8 9h = slot 9 Ah = slot 10 Bh = slot 11 Ch = slot 12 Dh = slot 13 Eh = slot 14 Fh = slot 15 |
3-0 | BUCK2_SEQUENCE_OFF_SLOT | R/W | X | BUCK2 slot number for power-down (Default from NVM
memory) 0h = slot 0 1h = slot 1 2h = slot 2 3h = slot 3 4h = slot 4 5h = slot 5 6h = slot 6 7h = slot 7 8h = slot 8 9h = slot 9 Ah = slot 10 Bh = slot 11 Ch = slot 12 Dh = slot 13 Eh = slot 14 Fh = slot 15 |
BUCK1_SEQUENCE_SLOT is shown in Figure 6-35 and described in Table 6-26.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUCK1_SEQUENCE_ON_SLOT | BUCK1_SEQUENCE_OFF_SLOT | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | BUCK1_SEQUENCE_ON_SLOT | R/W | X | BUCK1 Slot number for power-up (Default from NVM
memory) 0h = slot 0 1h = slot 1 2h = slot 2 3h = slot 3 4h = slot 4 5h = slot 5 6h = slot 6 7h = slot 7 8h = slot 8 9h = slot 9 Ah = slot 10 Bh = slot 11 Ch = slot 12 Dh = slot 13 Eh = slot 14 Fh = slot 15 |
3-0 | BUCK1_SEQUENCE_OFF_SLOT | R/W | X | BUCK1 slot number for power-down (Default from NVM
memory) 0h = slot 0 1h = slot 1 2h = slot 2 3h = slot 3 4h = slot 4 5h = slot 5 6h = slot 6 7h = slot 7 8h = slot 8 9h = slot 9 Ah = slot 10 Bh = slot 11 Ch = slot 12 Dh = slot 13 Eh = slot 14 Fh = slot 15 |
nRST_SEQUENCE_SLOT is shown in Figure 6-36 and described in Table 6-27.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
nRST_SEQUENCE_ON_SLOT | nRST_SEQUENCE_OFF_SLOT | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | nRST_SEQUENCE_ON_SLOT | R/W | X | nRST slot number for power-up (Default from NVM
memory) 0h = slot 0 1h = slot 1 2h = slot 2 3h = slot 3 4h = slot 4 5h = slot 5 6h = slot 6 7h = slot 7 8h = slot 8 9h = slot 9 Ah = slot 10 Bh = slot 11 Ch = slot 12 Dh = slot 13 Eh = slot 14 Fh = slot 15 |
3-0 | nRST_SEQUENCE_OFF_SLOT | R/W | X | nRST slot number for power-down (Default from NVM
memory) 0h = slot 0 1h = slot 1 2h = slot 2 3h = slot 3 4h = slot 4 5h = slot 5 6h = slot 6 7h = slot 7 8h = slot 8 9h = slot 9 Ah = slot 10 Bh = slot 11 Ch = slot 12 Dh = slot 13 Eh = slot 14 Fh = slot 15 |
GPIO_SEQUENCE_SLOT is shown in Figure 6-37 and described in Table 6-28.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO_SEQUENCE_ON_SLOT | GPIO_SEQUENCE_OFF_SLOT | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | GPIO_SEQUENCE_ON_SLOT | R/W | X | GPIO slot number for power-up (Default from NVM
memory) 0h = slot 0 1h = slot 1 2h = slot 2 3h = slot 3 4h = slot 4 5h = slot 5 6h = slot 6 7h = slot 7 8h = slot 8 9h = slot 9 Ah = slot 10 Bh = slot 11 Ch = slot 12 Dh = slot 13 Eh = slot 14 Fh = slot 15 |
3-0 | GPIO_SEQUENCE_OFF_SLOT | R/W | X | GPIO slot number for power-down (Default from NVM
memory) 0h = slot 0 1h = slot 1 2h = slot 2 3h = slot 3 4h = slot 4 5h = slot 5 6h = slot 6 7h = slot 7 8h = slot 8 9h = slot 9 Ah = slot 10 Bh = slot 11 Ch = slot 12 Dh = slot 13 Eh = slot 14 Fh = slot 15 |
GPO2_SEQUENCE_SLOT is shown in Figure 6-38 and described in Table 6-29.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPO2_SEQUENCE_ON_SLOT | GPO2_SEQUENCE_OFF_SLOT | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | GPO2_SEQUENCE_ON_SLOT | R/W | X | GPO2 slot number for power-up (Default from NVM
memory) 0h = slot 0 1h = slot 1 2h = slot 2 3h = slot 3 4h = slot 4 5h = slot 5 6h = slot 6 7h = slot 7 8h = slot 8 9h = slot 9 Ah = slot 10 Bh = slot 11 Ch = slot 12 Dh = slot 13 Eh = slot 14 Fh = slot 15 |
3-0 | GPO2_SEQUENCE_OFF_SLOT | R/W | X | GPO2 slot number for power-down (Default from NVM
memory) 0h = slot 0 1h = slot 1 2h = slot 2 3h = slot 3 4h = slot 4 5h = slot 5 6h = slot 6 7h = slot 7 8h = slot 8 9h = slot 9 Ah = slot 10 Bh = slot 11 Ch = slot 12 Dh = slot 13 Eh = slot 14 Fh = slot 15 |
GPO1_SEQUENCE_SLOT is shown in Figure 6-39 and described in Table 6-30.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPO1_SEQUENCE_ON_SLOT | GPO1_SEQUENCE_OFF_SLOT | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | GPO1_SEQUENCE_ON_SLOT | R/W | X | GPO1 slot number for power-up (Default from NVM
memory) 0h = slot 0 1h = slot 1 2h = slot 2 3h = slot 3 4h = slot 4 5h = slot 5 6h = slot 6 7h = slot 7 8h = slot 8 9h = slot 9 Ah = slot 10 Bh = slot 11 Ch = slot 12 Dh = slot 13 Eh = slot 14 Fh = slot 15 |
3-0 | GPO1_SEQUENCE_OFF_SLOT | R/W | X | GPO1 slot number for power-down (Default from NVM
memory) 0h = slot 0 1h = slot 1 2h = slot 2 3h = slot 3 4h = slot 4 5h = slot 5 6h = slot 6 7h = slot 7 8h = slot 8 9h = slot 9 Ah = slot 10 Bh = slot 11 Ch = slot 12 Dh = slot 13 Eh = slot 14 Fh = slot 15 |
POWER_UP_SLOT_DURATION_1 is shown in Figure 6-40 and described in Table 6-31.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POWER_UP_SLOT_0_DURATION | POWER_UP_SLOT_1_DURATION | POWER_UP_SLOT_2_DURATION | POWER_UP_SLOT_3_DURATION | ||||
R/W-X | R/W-X | R/W-X | R/W-X | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | POWER_UP_SLOT_0_DURATION | R/W | X | Duration of slot 0 during the power-up and
standby-to-active sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
5-4 | POWER_UP_SLOT_1_DURATION | R/W | X | Duration of slot 1 during the power-up and
standby-to-active sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
3-2 | POWER_UP_SLOT_2_DURATION | R/W | X | Duration of slot 2 during the power-up and
standby-to-active sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
1-0 | POWER_UP_SLOT_3_DURATION | R/W | X | Duration of slot 3 during the power-up and
standby-to-active sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
POWER_UP_SLOT_DURATION_2 is shown in Figure 6-41 and described in Table 6-32.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POWER_UP_SLOT_4_DURATION | POWER_UP_SLOT_5_DURATION | POWER_UP_SLOT_6_DURATION | POWER_UP_SLOT_7_DURATION | ||||
R/W-X | R/W-X | R/W-X | R/W-X | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | POWER_UP_SLOT_4_DURATION | R/W | X | Duration of slot 4 during the power-up and
standby-to-active sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
5-4 | POWER_UP_SLOT_5_DURATION | R/W | X | Duration of slot 5 during the power-up and
standby-to-active sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
3-2 | POWER_UP_SLOT_6_DURATION | R/W | X | Duration of slot 6 during the power-up and
standby-to-active sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
1-0 | POWER_UP_SLOT_7_DURATION | R/W | X | Duration of slot 7 during the power-up and
standby-to-active sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
POWER_UP_SLOT_DURATION_3 is shown in Figure 6-42 and described in Table 6-33.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POWER_UP_SLOT_8_DURATION | POWER_UP_SLOT_9_DURATION | POWER_UP_SLOT_10_DURATION | POWER_UP_SLOT_11_DURATION | ||||
R/W-X | R/W-X | R/W-X | R/W-X | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | POWER_UP_SLOT_8_DURATION | R/W | X | Duration of slot 8 during the power-up and
standby-to-active sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
5-4 | POWER_UP_SLOT_9_DURATION | R/W | X | Duration of slot 9 during the power-up and
standby-to-active sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
3-2 | POWER_UP_SLOT_10_DURATION | R/W | X | Duration of slot 10 during the power-up and
standby-to-active sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
1-0 | POWER_UP_SLOT_11_DURATION | R/W | X | Duration of slot 11 during the power-up and
standby-to-active sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
POWER_UP_SLOT_DURATION_4 is shown in Figure 6-43 and described in Table 6-34.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POWER_UP_SLOT_12_DURATION | POWER_UP_SLOT_13_DURATION | POWER_UP_SLOT_14_DURATION | POWER_UP_SLOT_15_DURATION | ||||
R/W-X | R/W-X | R/W-X | R/W-X | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | POWER_UP_SLOT_12_DURATION | R/W | X | Duration of slot 12 during the power-up and
standby-to-active sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
5-4 | POWER_UP_SLOT_13_DURATION | R/W | X | Duration of slot 13 during the power-up and
standby-to-active sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
3-2 | POWER_UP_SLOT_14_DURATION | R/W | X | Duration of slot 14 during the power-up and
standby-to-active sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
1-0 | POWER_UP_SLOT_15_DURATION | R/W | X | Duration of slot 15 during the power-up and
standby-to-active sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
POWER_DOWN_SLOT_DURATION_1 is shown in Figure 6-44 and described in Table 6-35.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POWER_DOWN_SLOT_0_DURATION | POWER_DOWN_SLOT_1_DURATION | POWER_DOWN_SLOT_2_DURATION | POWER_DOWN_SLOT_3_DURATION | ||||
R/W-X | R/W-X | R/W-X | R/W-X | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | POWER_DOWN_SLOT_0_DURATION | R/W | X | Duration of slot 0 during the power-down and
active-to-standby sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
5-4 | POWER_DOWN_SLOT_1_DURATION | R/W | X | Duration of slot 1 during the power-down and
active-to-standby sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
3-2 | POWER_DOWN_SLOT_2_DURATION | R/W | X | Duration of slot 2 during the power-down and
active-to-standby sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
1-0 | POWER_DOWN_SLOT_3_DURATION | R/W | X | Duration of slot 3 during the power-down and
active-to-standby sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
POWER_DOWN_SLOT_DURATION_2 is shown in Figure 6-45 and described in Table 6-36.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POWER_DOWN_SLOT_4_DURATION | POWER_DOWN_SLOT_5_DURATION | POWER_DOWN_SLOT_6_DURATION | POWER_DOWN_SLOT_7_DURATION | ||||
R/W-X | R/W-X | R/W-X | R/W-X | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | POWER_DOWN_SLOT_4_DURATION | R/W | X | Duration of slot 4 during the power-down and
active-to-standby sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
5-4 | POWER_DOWN_SLOT_5_DURATION | R/W | X | Duration of slot 5 during the power-down and
active-to-standby sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
3-2 | POWER_DOWN_SLOT_6_DURATION | R/W | X | Duration of slot 6 during the power-down and
active-to-standby sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
1-0 | POWER_DOWN_SLOT_7_DURATION | R/W | X | Duration of slot 7 during the power-down and
active-to-standby sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
POWER_DOWN_SLOT_DURATION_3 is shown in Figure 6-46 and described in Table 6-37.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POWER_DOWN_SLOT_8_DURATION | POWER_DOWN_SLOT_9_DURATION | POWER_DOWN_SLOT_10_DURATION | POWER_DOWN_SLOT_11_DURATION | ||||
R/W-X | R/W-X | R/W-X | R/W-X | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | POWER_DOWN_SLOT_8_DURATION | R/W | X | Duration of slot 8 during the power-down and
active-to-standby sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
5-4 | POWER_DOWN_SLOT_9_DURATION | R/W | X | Duration of slot 9 during the power-down and
active-to-standby sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
3-2 | POWER_DOWN_SLOT_10_DURATION | R/W | X | Duration of slot 10 during the power-down and
active-to-standby sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
1-0 | POWER_DOWN_SLOT_11_DURATION | R/W | X | Duration of slot 11 during the power-down and
active-to-standby sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
POWER_DOWN_SLOT_DURATION_4 is shown in Figure 6-47 and described in Table 6-38.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POWER_DOWN_SLOT_12_DURATION | POWER_DOWN_SLOT_13_DURATION | POWER_DOWN_SLOT_14_DURATION | POWER_DOWN_SLOT_15_DURATION | ||||
R/W-X | R/W-X | R/W-X | R/W-X | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | POWER_DOWN_SLOT_12_DURATION | R/W | X | Duration of slot 12 during the power-down and
active-to-standby sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
5-4 | POWER_DOWN_SLOT_13_DURATION | R/W | X | Duration of slot 13 during the power-down and
active-to-standby sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
3-2 | POWER_DOWN_SLOT_14_DURATION | R/W | X | Duration of slot 14 during the power-down and
active-to-standby sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
1-0 | POWER_DOWN_SLOT_15_DURATION | R/W | X | Duration of slot 15 during the power-down and
active-to-standby sequences. (Default from NVM memory) 0h = 0ms 1h = 1.5ms 2h = 3ms 3h = 10ms |
GENERAL_CONFIG is shown in Figure 6-48 and described in Table 6-39.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BYPASS_RAILS_DISCHARGED_CHECK | LDO4_UV_THR | LDO3_UV_THR | LDO2_UV_THR | LDO1_UV_THR | GPIO_EN | GPO2_EN | GPO1_EN |
R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | R/W-X |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | BYPASS_RAILS_DISCHARGED_CHECK | R/W | X | Bypass the all-rails discharged check to commence a
transition to ACTIVE state, and the rails-in-slot discharged check
executed in each slot during a power-down to INITIALIZE state. Does
not bypass the check for RV(Pre-biased) condition prior to enabling
a regulator. (Default from NVM memory) 0h = Discharged checks enforced 1h = Discharged checks bypassed |
6 | LDO4_UV_THR | R/W | X | UV threshold selection bit for LDO4. Only applicable
if configured as LDO. (Default from NVM memory) 0h = -5% UV detection 1h = -10% UV detection |
5 | LDO3_UV_THR | R/W | X | UV threshold selection bit for LDO3. Only applicable
if configured as LDO. (Default from NVM memory) 0h = -5% UV detection 1h = -10% UV detection |
4 | LDO2_UV_THR | R/W | X | UV threshold selection bit for LDO2. Only applicable
if configured as LDO. (Default from NVM memory) 0h = -5% UV detection 1h = -10% UV detection |
3 | LDO1_UV_THR | R/W | X | UV threshold selection bit for LDO1. Only applicable
if configured as LDO. (Default from NVM memory) 0h = -5% UV detection 1h = -10% UV detection |
2 | GPIO_EN | R/W | X | Both an enable and state control of GPIO. This bit
enables the GPIO function and also controls the state of the GPIO
pin. (Default from NVM memory) 0h = The GPIO function is disabled. The output state is 'low'. 1h = The GPIO function is enabled. The output state is 'high'. |
1 | GPO2_EN | R/W | X | Both an enable and state control of GPO2. This bit
enables the GPO2 function and also controls the state of the GPO2
pin. (Default from NVM memory) 0h = GPO2 disabled. The output state is low. 1h = GPO2 enabled. The output state is Hi-Z. |
0 | GPO1_EN | R/W | X | Both an enable and state control of GPO1. This bit
enables the GPO1 function and also controls the state of the GPO1
pin. (Default from NVM memory) 0h = GPO1 disabled. The output state is low. 1h = GPO1 enabled. The output state is Hi-Z. |
MFP_1_CONFIG is shown in Figure 6-49 and described in Table 6-40.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODE_I2C_CTRL | VSEL_SD_I2C_CTRL | MODE_RESET_POLARITY | MODE_STBY_POLARITY | MULTI_DEVICE_ENABLE | VSEL_RAIL | VSEL_SD_POLARITY | VSEL_DDR_SD |
R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | R/W-X |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | MODE_I2C_CTRL | R/W | X | MODE control using I2C. Consolidated with MODE
control via MODE/RESET and/or MODE/STBY pins. Refer to table in the
data sheet. (Default from NVM memory) 0h = Auto PFM 1h = Forced PWM |
6 | VSEL_SD_I2C_CTRL | R/W | X | VSEL_SD control using I2C. Applicable only if
VSEL_SD/VSEL_DDR pin is configured as "VSEL_DDR". (Default from NVM
memory) 0h = 1.8V 1h = LDOx_VOUT register setting |
5 | MODE_RESET_POLARITY | R/W | X | MODE_RESET Pin Polarity configuration. Note: Ok to
change during operation, but consider immediate reaction:
MODE-change or RESET-entry! (Default from NVM memory) 0h = [if configured as MODE] LOW - auto-PFM / HIGH - forced PWM. [if configured as RESET] LOW - reset / HIGH - normal operation. 1h = [if configured as MODE] HIGH - auto-PFM / LOW - forced PWM. [if configured as RESET] HIGH - reset / LOW - normal operation. |
4 | MODE_STBY_POLARITY | R/W | X | MODE_STBY Pin Polarity configuration. Note: Ok to
change during operation, but consider immediate reaction:
MODE-change or STATE-change! (Default from NVM memory) 0h = [if configured as MODE] LOW - auto-PFM / HIGH - forced PWM. [if configured as a STBY] LOW - STBY state / HIGH - ACTIVE state. 1h = [if configured as MODE] HIGH - auto-PFM / LOW - forced PWM. [if configured as a STBY] HIGH - STBY state / LOW - ACTIVE state. |
3 | MULTI_DEVICE_ENABLE | R/W | X | Configures the device as a single device where GPO is
used as GPO function, or as a multi-device configuration where GPO
is used for synchronization with other devices. NOTE: ONLY CHANGE IN
INITIALIZE STATE! (Default from NVM memory) 0h = Single-device configuration, GPIO pin configured as GPO 1h = Multi-device configuration, GPIO pin configured as GPIO |
2 | VSEL_RAIL | R/W | X | LDO controlled by VSEL_SD/VSEL_DDR. NOTE: ONLY CHANGE
IN INITIALIZE STATE! (Default from NVM memory) 0h = LDO1 1h = LDO2 |
1 | VSEL_SD_POLARITY | R/W | X | SD Card Voltage Select Note: Ok to change during
operation, but consider immediate reaction: change of SD-card supply
voltage! (Default from NVM memory) 0h = LOW - 1.8V / HIGH - LDOx_VOUT register setting 1h = HIGH - 1.8V / LOW - LDOx_VOUT register setting |
0 | VSEL_DDR_SD | R/W | X | VSEL_SD/VSEL_DDR Configuration NOTE: ONLY CHANGE IN
INITIALIZE STATE! (Default from NVM memory) 0h = VSEL pin configured as DDR to set the voltage on Buck3 1h = VSEL pin configured as SD to set the voltage on the VSEL_RAIL |
MFP_2_CONFIG is shown in Figure 6-50 and described in Table 6-41.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PU_ON_FSD | WARM_COLD_RESET_CONFIG | EN_PB_VSENSE_CONFIG | EN_PB_VSENSE_DEGL | MODE_RESET_CONFIG | MODE_STBY_CONFIG | ||
R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | PU_ON_FSD | R/W | X | Power up upon First Supply Detected (FSD). So when
VSYS is applied, device does power up to ACTIVE state even if
EN/PB/VSENSE pin is at OFF_REQ status. (Default from NVM memory) 0h = First Supply Detection (FSD) Disabled. 1h = First Supply Detection (FSD) Enabled. |
6 | WARM_COLD_RESET_CONFIG | R/W | X | Selection between WARM or COLD Reset, when a RESET
event is triggered via MODE/RESET pin (does not apply to RESET via
I2C) (Default from NVM memory) 0h = COLD RESET 1h = WARM RESET |
5-4 | EN_PB_VSENSE_CONFIG | R/W | X | Enable / Push-Button / VSENSE Configuration. Do not
change via I2C after NVM load (except as a precursor before
programming NVM) (Default from NVM memory) 0h = Device Enable Configuration 1h = Push Button Configuration 2h = VSENSE Configuration 3h = Device Enable Configuration |
3 | EN_PB_VSENSE_DEGL | R/W | X | Enable / Push-Button / VSENSE Deglitch NOTE: ONLY
CHANGE IN INITIALIZE STATE! Consider immediate reaction when
changing from EN/VSENSE to PB or vice versa: power-up! (Default from
NVM memory) 0h = short (typ: 120us for EN/VSENSE and 200ms for PB) 1h = long (typ: 50ms for EN/VSENSE and 600ms for PB) |
2 | MODE_RESET_CONFIG | R/W | X | MODE/RESET Configuration (Default from NVM memory)
0h = MODE 1h = RESET |
1-0 | MODE_STBY_CONFIG | R/W | X | MODE_STDBY Configuration (Default from NVM memory)
0h = MODE 1h = STBY 2h = MODE and STBY 3h = MODE |
STBY_1_CONFIG is shown in Figure 6-51 and described in Table 6-42.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LDO4_STBY_EN | LDO3_STBY_EN | LDO2_STBY_EN | LDO1_STBY_EN | BUCK3_STBY_EN | BUCK2_STBY_EN | BUCK1_STBY_EN |
R-X | R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | R/W-X |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | X | Reserved |
6 | LDO4_STBY_EN | R/W | X | Enable LDO4 in STANDBY state. (Default from NVM
memory) 0h = Disabled in STBY Mode 1h = Enabled in STBY Mode |
5 | LDO3_STBY_EN | R/W | X | Enable LDO3 in STANDBY state. (Default from NVM
memory) 0h = Disabled in STBY Mode 1h = Enabled in STBY Mode |
4 | LDO2_STBY_EN | R/W | X | Enable LDO2 in STANDBY state. (Default from NVM
memory) 0h = Disabled in STBY Mode 1h = Enabled in STBY Mode |
3 | LDO1_STBY_EN | R/W | X | Enable LDO1 in STANDBY state. (Default from NVM
memory) 0h = Disabled in STBY Mode 1h = Enabled in STBY Mode |
2 | BUCK3_STBY_EN | R/W | X | Enable BUCK3 in STANDBY state. (Default from NVM
memory) 0h = Disabled in STBY Mode 1h = Enabled in STBY Mode |
1 | BUCK2_STBY_EN | R/W | X | Enable BUCK2 in STANDBY state. (Default from NVM
memory) 0h = Disabled in STBY Mode 1h = Enabled in STBY Mode |
0 | BUCK1_STBY_EN | R/W | X | Enable BUCK1 in STANDBY state. (Default from NVM
memory) 0h = Disabled in STBY Mode 1h = Enabled in STBY Mode |
STBY_2_CONFIG is shown in Figure 6-52 and described in Table 6-43.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | GPIO_STBY_EN | GPO2_STBY_EN | GPO1_STBY_EN |
R-X | R-X | R-X | R-X | R-X | R/W-X | R/W-X | R/W-X |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | X | Reserved |
6 | RESERVED | R | X | Reserved |
5 | RESERVED | R | X | Reserved |
4 | RESERVED | R | X | Reserved |
3 | RESERVED | R | X | Reserved |
2 | GPIO_STBY_EN | R/W | X | Enable GPIO in STANDBY state. (Default from NVM
memory) 0h = Disabled in STBY Mode 1h = Enabled in STBY Mode |
1 | GPO2_STBY_EN | R/W | X | Enable GPO2 in STANDBY state. (Default from NVM
memory) 0h = Disabled in STBY Mode 1h = Enabled in STBY Mode |
0 | GPO1_STBY_EN | R/W | X | Enable GPO1 in STANDBY state. (Default from NVM
memory) 0h = Disabled in STBY Mode 1h = Enabled in STBY Mode |
OC_DEGL_CONFIG is shown in Figure 6-53 and described in Table 6-44.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EN_LONG_DEGL_FOR_OC_LDO4 | EN_LONG_DEGL_FOR_OC_LDO3 | EN_LONG_DEGL_FOR_OC_LDO2 | EN_LONG_DEGL_FOR_OC_LDO1 | EN_LONG_DEGL_FOR_OC_BUCK3 | EN_LONG_DEGL_FOR_OC_BUCK2 | EN_LONG_DEGL_FOR_OC_BUCK1 |
R-X | R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | R/W-X |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | X | Reserved |
6 | EN_LONG_DEGL_FOR_OC_LDO4 | R/W | X | When set, enables the long-deglitch option for
OverCurrent signal of LDO4. When clear, enables the short-deglitch
option for OverCurrent signal of LDO4. (Default from NVM memory) 0h = Deglitch duration for OverCurrent signals of LDO4 is ~20us 1h = Deglitch duration for OverCurrent signals of LDO4 is ~2ms |
5 | EN_LONG_DEGL_FOR_OC_LDO3 | R/W | X | When set, enables the long-deglitch option for
OverCurrent signal of LDO3. When clear, enables the short-deglitch
option for OverCurrent signal of LDO3. (Default from NVM memory) 0h = Deglitch duration for OverCurrent signals of LDO3 is ~20us 1h = Deglitch duration for OverCurrent signals of LDO3 is ~2ms |
4 | EN_LONG_DEGL_FOR_OC_LDO2 | R/W | X | When set, enables the long-deglitch option for
OverCurrent signal of LDO2. When clear, enables the short-deglitch
option for OverCurrent signal of LDO2. (Default from NVM memory) 0h = Deglitch duration for OverCurrent signals of LDO2 is ~20us 1h = Deglitch duration for OverCurrent signals of LDO2 is ~2ms |
3 | EN_LONG_DEGL_FOR_OC_LDO1 | R/W | X | When set, enables the long-deglitch option for
OverCurrent signal of LDO1. When clear, enables the short-deglitch
option for OverCurrent signal of LDO1. (Default from NVM memory) 0h = Deglitch duration for OverCurrent signals of LDO1 is ~20us 1h = Deglitch duration for OverCurrent signals of LDO1 is ~2ms |
2 | EN_LONG_DEGL_FOR_OC_BUCK3 | R/W | X | When set, enables the long-deglitch option for
OverCurrent signals of BUCK3. When clear, enables the short-deglitch
option for OverCurrent signals of BUCK3. (Default from NVM memory)
0h = Deglitch duration for OverCurrent signals for BUCK3 (High-Side Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative OverCurrent) is ~20us 1h = Deglitch duration for OverCurrent signals for BUCK3 (High-Side Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative OverCurrent) is ~2ms |
1 | EN_LONG_DEGL_FOR_OC_BUCK2 | R/W | X | When set, enables the long-deglitch option for
OverCurrent signals of BUCK2. When clear, enables the short-deglitch
option for OverCurrent signals of BUCK2. (Default from NVM memory)
0h = Deglitch duration for OverCurrent signals for BUCK2 (High-Side Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative OverCurrent) is ~20us 1h = Deglitch duration for OverCurrent signals for BUCK2 (High-Side Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative OverCurrent) is ~2ms |
0 | EN_LONG_DEGL_FOR_OC_BUCK1 | R/W | X | When set, enables the long-deglitch option for
OverCurrent signals of BUCK1. When clear, enables the short-deglitch
option for OverCurrent signals of BUCK1. (Default from NVM memory)
0h = Deglitch duration for OverCurrent signals for BUCK1 (High-Side Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative OverCurrent) is ~20us 1h = Deglitch duration for OverCurrent signals for BUCK1 (High-Side Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative OverCurrent) is ~2ms |
INT_MASK_UV is shown in Figure 6-54 and described in Table 6-45.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MASK_RETRY_COUNT | BUCK3_UV_MASK | BUCK2_UV_MASK | BUCK1_UV_MASK | LDO4_UV_MASK | LDO3_UV_MASK | LDO2_UV_MASK | LDO1_UV_MASK |
R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | R/W-X |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | MASK_RETRY_COUNT | R/W | X | When set, device can power up even after two retries.
(Default from NVM memory) 0h = Device does retry up to 2 times, then stay off 1h = Device does retry infinitely |
6 | BUCK3_UV_MASK | R/W | X | BUCK3 Undervoltage Mask. (Default from NVM memory)
0h = un-masked (Faults reported) 1h = masked (Faults not reported) |
5 | BUCK2_UV_MASK | R/W | X | BUCK2 Undervoltage Mask. (Default from NVM memory)
0h = un-masked (Faults reported) 1h = masked (Faults not reported) |
4 | BUCK1_UV_MASK | R/W | X | BUCK1 Undervoltage Mask. (Default from NVM memory)
0h = un-masked (Faults reported) 1h = masked (Faults not reported) |
3 | LDO4_UV_MASK | R/W | X | LDO4 Undervoltage Mask - Always masked in BYP or LSW
modes. (Default from NVM memory) 0h = un-masked (Faults reported) 1h = masked (Faults not reported) |
2 | LDO3_UV_MASK | R/W | X | LDO3 Undervoltage Mask - Always masked in BYP or LSW
modes. (Default from NVM memory) 0h = un-masked (Faults reported) 1h = masked (Faults not reported) |
1 | LDO2_UV_MASK | R/W | X | LDO2 Undervoltage Mask - Always masked in BYP or LSW
modes. (Default from NVM memory) 0h = un-masked (Faults reported) 1h = masked (Faults not reported) |
0 | LDO1_UV_MASK | R/W | X | LDO1 Undervoltage Mask - Always masked in BYP or LSW
modes. (Default from NVM memory) 0h = un-masked (Faults reported) 1h = masked (Faults not reported) |
MASK_CONFIG is shown in Figure 6-55 and described in Table 6-46.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MASK_INT_FOR_PB | MASK_EFFECT | MASK_INT_FOR_RV | SENSOR_0_WARM_MASK | SENSOR_1_WARM_MASK | SENSOR_2_WARM_MASK | SENSOR_3_WARM_MASK | |
R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | MASK_INT_FOR_PB | R/W | X | Masking bit to control whether nINT pin is sensitive
to PushButton (PB) press/release events or not. (Default from NVM
memory) 0h = un-masked (nINT pulled low for any PB events) 1h = masked (nINT not sensitive to any PB events) |
6-5 | MASK_EFFECT | R/W | X | Effect of masking (global) (Default from NVM memory)
0h = no state change, no nINT reaction, no bit set for Faults 1h = no state change, no nINT reaction, bit set for Faults 2h = no state change, nINT reaction, bit set for Faults (same as 11b) 3h = no state change, nINT reaction, bit set for Faults (same as 10b) |
4 | MASK_INT_FOR_RV | R/W | X | Masking bit to control whether nINT pin is sensitive
to RV (Residual Voltage) events or not. (Default from NVM memory)
0h = un-masked (nINT pulled low for any RV events during transition to ACTIVE state or during enabling of rails) 1h = masked (nINT not sensitive to any RV events) |
3 | SENSOR_0_WARM_MASK | R/W | X | Die Temperature Warm Fault Mask, Sensor 0. (Default
from NVM memory) 0h = un-masked (Faults reported) 1h = masked (Faults not reported) |
2 | SENSOR_1_WARM_MASK | R/W | X | Die Temperature Warm Fault Mask, Sensor 1. (Default
from NVM memory) 0h = un-masked (Faults reported) 1h = masked (Faults not reported) |
1 | SENSOR_2_WARM_MASK | R/W | X | Die Temperature Warm Fault Mask, Sensor 2. (Default
from NVM memory) 0h = un-masked (Faults reported) 1h = masked (Faults not reported) |
0 | SENSOR_3_WARM_MASK | R/W | X | Die Temperature Warm Fault Mask, Sensor 3. (Default
from NVM memory) 0h = un-masked (Faults reported) 1h = masked (Faults not reported) |
I2C_ADDRESS_REG is shown in Figure 6-56 and described in Table 6-47.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIY_NVM_PROGRAM_CMD_ISSUED | I2C_ADDRESS | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | DIY_NVM_PROGRAM_CMD_ISSUED | R/W | X | Bit that indicates whether a DIY program command was
attempted. Once set, remains always set. (Default from NVM memory)
0h = NVM data not changed 1h = NVM data attempted to be changed via DIY program command |
6-0 | I2C_ADDRESS | R/W | X | I2C secondary address. Note: Ok to change during operation, but consider immediate reaction: new address for read/write! (Default from NVM memory) |
USER_GENERAL_NVM_STORAGE_REG is shown in Figure 6-57 and described in Table 6-48.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER_GENERAL_NVM_STORAGE | |||||||
R/W-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | USER_GENERAL_NVM_STORAGE | R/W | X | 8-bit NVM-based register available to the user to use to store user-data, for example NVM-ID of customer-modified NVM-version or other purposes. (Default from NVM memory) |
MANUFACTURING_VER is shown in Figure 6-58 and described in Table 6-49.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SILICON_REV | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | SILICON_REV | R | 0h | SILICON_REV[7:6] - Reserved SILICON_REV[5:3] - ALR SILICON_REV[2:0] - Metal Silicon Revision - Hard wired (not under NVM control) |
MFP_CTRL is shown in Figure 6-59 and described in Table 6-50.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | GPIO_STATUS | WARM_RESET_I2C_CTRL | COLD_RESET_I2C_CTRL | STBY_I2C_CTRL | I2C_OFF_REQ |
R-X | R-X | R-X | R-0h | R/WSelfClrF-0h | R/W-0h | R/W-0h | R/WSelfClrF-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | X | Reserved |
6 | RESERVED | R | X | Reserved |
5 | RESERVED | R | X | Reserved |
4 | GPIO_STATUS | R | 0h | Indicates the real-time value of GPIO pin 0h = The GPIO pin is currently '0' 1h = The GPIO pin is currently '1' |
3 | WARM_RESET_I2C_CTRL | R/WSelfClrF | 0h | Triggers a WARM RESET when written as '1'. Note: This
bit self-clears automatically, so cannot be read as '1' after the
write. 0h = normal operation 1h = WARM_RESET |
2 | COLD_RESET_I2C_CTRL | R/W | 0h | Triggers a COLD RESET when set high. Cleared upon
entry to INITIALIZE. 0h = normal operation 1h = COLD_RESET |
1 | STBY_I2C_CTRL | R/W | 0h | STBY control using I2C. Consolidated with STBY
control via MODE/STBY pin. Refer to table in spec. 0h = normal operation 1h = STBY mode |
0 | I2C_OFF_REQ | R/WSelfClrF | 0h | When '1' is written to this bit: Trigger OFF request.
When '0': No effect. Does self-clear. 0h = No effect 1h = Trigger OFF Request |
DISCHARGE_CONFIG is shown in Figure 6-60 and described in Table 6-51.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LDO4_DISCHARGE_EN | LDO3_DISCHARGE_EN | LDO2_DISCHARGE_EN | LDO1_DISCHARGE_EN | BUCK3_DISCHARGE_EN | BUCK2_DISCHARGE_EN | BUCK1_DISCHARGE_EN |
R-X | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | X | Reserved |
6 | LDO4_DISCHARGE_EN | R/W | 1h | Discharge setting for LDO4 0h = No Discharge 1h = 250 Ω |
5 | LDO3_DISCHARGE_EN | R/W | 1h | Discharge setting for LDO3 0h = No Discharge 1h = 250 Ω |
4 | LDO2_DISCHARGE_EN | R/W | 1h | Discharge setting for LDO2 0h = No Discharge 1h = 200 Ω |
3 | LDO1_DISCHARGE_EN | R/W | 1h | Discharge setting for LDO1 0h = No Discharge 1h = 200 Ω |
2 | BUCK3_DISCHARGE_EN | R/W | 1h | Discharge setting for BUCK3 0h = No Discharge 1h = 125 Ω |
1 | BUCK2_DISCHARGE_EN | R/W | 1h | Discharge setting for BUCK2 0h = No Discharge 1h = 125 Ω |
0 | BUCK1_DISCHARGE_EN | R/W | 1h | Discharge setting for BUCK1 0h = No Discharge 1h = 125 Ω |
INT_SOURCE is shown in Figure 6-61 and described in Table 6-52.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_PB_IS_SET | INT_LDO_3_4_IS_SET | INT_LDO_1_2_IS_SET | INT_BUCK_3_IS_SET | INT_BUCK_1_2_IS_SET | INT_SYSTEM_IS_SET | INT_RV_IS_SET | INT_TIMEOUT_RV_SD_IS_SET |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_PB_IS_SET | R | 0h | One or more sources of the INT present in register
INT_PB 0h = No bits set in INT_PB 1h = One or more bits set in INT_PB |
6 | INT_LDO_3_4_IS_SET | R | 0h | One or more sources of the INT present in register
INT_LDO_3_4 0h = No bits set in INT_LDO_3_4 1h = One or more bits set in INT_LDO_3_4 |
5 | INT_LDO_1_2_IS_SET | R | 0h | One or more sources of the INT present in register
INT_LDO_1_2 0h = No bits set in INT_LDO_1_2 1h = One or more bits set in INT_LDO_1_2 |
4 | INT_BUCK_3_IS_SET | R | 0h | One or more sources of the INT present in register
INT_BUCK_3 0h = No bits set in INT_BUCK_3 1h = One or more bits set in INT_BUCK_3 |
3 | INT_BUCK_1_2_IS_SET | R | 0h | One or more sources of the INT present in register
INT_BUCK_1_2 0h = No bits set in INT_BUCK_1_2 1h = One or more bits set in INT_BUCK_1_2 |
2 | INT_SYSTEM_IS_SET | R | 0h | One or more sources of the INT present in register
INT_SYSTEM 0h = No bits set in INT_SYSTEM 1h = One or more bits set in INT_SYSTEM |
1 | INT_RV_IS_SET | R | 0h | One or more sources of the INT present in register
INT_RV 0h = No bits set in INT_RV 1h = One or more bits set in INT_RV |
0 | INT_TIMEOUT_RV_SD_IS_SET | R | 0h | One or more sources of the INT present in register
INT_TIMEOUT_RV_SD 0h = No bits set in INT_TIMEOUT_RV_SD 1h = One or more bits set in INT_TIMEOUT_RV_SD |
INT_LDO_3_4 is shown in Figure 6-62 and described in Table 6-53.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | LDO4_UV | LDO4_OC | LDO4_SCG | LDO3_UV | LDO3_OC | LDO3_SCG |
R-X | R-X | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | X | Reserved |
6 | RESERVED | R | X | Reserved |
5 | LDO4_UV | R/W1C | 0h | LDO4 Undervoltage Fault. Is automatically cleared
upon a transition to INITIALIZE state, if corresponding *_UV_MASK
bit in register INT_MASK_UV is '1' 0h = No Fault detected 1h = Fault detected |
4 | LDO4_OC | R/W1C | 0h | LDO4 Overcurrent Fault. 0h = No Fault detected 1h = Fault detected |
3 | LDO4_SCG | R/W1C | 0h | LDO4 Short Circuit to Ground Fault 0h = No Fault detected 1h = Fault detected |
2 | LDO3_UV | R/W1C | 0h | LDO3 Undervoltage Fault. Is automatically cleared
upon a transition to INITIALIZE state, if corresponding *_UV_MASK
bit in register INT_MASK_UV is '1' 0h = No Fault detected 1h = Fault detected |
1 | LDO3_OC | R/W1C | 0h | LDO3 Overcurrent Fault 0h = No Fault detected 1h = Fault detected |
0 | LDO3_SCG | R/W1C | 0h | LDO3 Short Circuit to Ground Fault 0h = No Fault detected 1h = Fault detected |
INT_LDO_1_2 is shown in Figure 6-63 and described in Table 6-54.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | LDO2_UV | LDO2_OC | LDO2_SCG | LDO1_UV | LDO1_OC | LDO1_SCG |
R-X | R-X | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | X | Reserved |
6 | RESERVED | R | X | Reserved |
5 | LDO2_UV | R/W1C | 0h | LDO2 Undervoltage Fault. Is automatically cleared
upon a transition to INITIALIZE state, if corresponding *_UV_MASK
bit in register INT_MASK_UV is '1' 0h = No Fault detected 1h = Fault detected |
4 | LDO2_OC | R/W1C | 0h | LDO2 Overcurrent Fault 0h = No Fault detected 1h = Fault detected |
3 | LDO2_SCG | R/W1C | 0h | LDO2 Short Circuit to Ground Fault 0h = No Fault detected 1h = Fault detected |
2 | LDO1_UV | R/W1C | 0h | LDO1 Undervoltage Fault. Is automatically cleared
upon a transition to INITIALIZE state, if corresponding *_UV_MASK
bit in register INT_MASK_UV is '1' 0h = No Fault detected 1h = Fault detected |
1 | LDO1_OC | R/W1C | 0h | LDO1 Overcurrent Fault 0h = No Fault detected 1h = Fault detected |
0 | LDO1_SCG | R/W1C | 0h | LDO1 Short Circuit to Ground Fault 0h = No Fault detected 1h = Fault detected |
INT_BUCK_3 is shown in Figure 6-64 and described in Table 6-55.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | BUCK3_UV | BUCK3_NEG_OC | BUCK3_OC | BUCK3_SCG |
R-X | R-X | R-X | R-X | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | X | Reserved |
6 | RESERVED | R | X | Reserved |
5 | RESERVED | R | X | Reserved |
4 | RESERVED | R | X | Reserved |
3 | BUCK3_UV | R/W1C | 0h | BUCK3 Undervoltage Fault. Is automatically cleared
upon a transition to INITIALIZE state, if corresponding *_UV_MASK
bit in register INT_MASK_UV is '1' 0h = No Fault detected 1h = Fault detected |
2 | BUCK3_NEG_OC | R/W1C | 0h | BUCK3 Negative Overcurrent Fault 0h = No Fault detected 1h = Fault detected |
1 | BUCK3_OC | R/W1C | 0h | BUCK3 Positive Overcurrent Fault 0h = No Fault detected 1h = Fault detected |
0 | BUCK3_SCG | R/W1C | 0h | BUCK3 Short Circuit to Ground Fault 0h = No Fault detected 1h = Fault detected |
INT_BUCK_1_2 is shown in Figure 6-65 and described in Table 6-56.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUCK2_UV | BUCK2_NEG_OC | BUCK2_OC | BUCK2_SCG | BUCK1_UV | BUCK1_NEG_OC | BUCK1_OC | BUCK1_SCG |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | BUCK2_UV | R/W1C | 0h | BUCK2 Undervoltage Fault. Is automatically cleared
upon a transition to INITIALIZE state, if corresponding *_UV_MASK
bit in register INT_MASK_UV is '1' 0h = No Fault detected 1h = Fault detected |
6 | BUCK2_NEG_OC | R/W1C | 0h | BUCK2 Negative Overcurrent Fault 0h = No Fault detected 1h = Fault detected |
5 | BUCK2_OC | R/W1C | 0h | BUCK2 Positive Overcurrent Fault 0h = No Fault detected 1h = Fault detected |
4 | BUCK2_SCG | R/W1C | 0h | BUCK2 Short Circuit to Ground Fault 0h = No Fault detected 1h = Fault detected |
3 | BUCK1_UV | R/W1C | 0h | BUCK1 Undervoltage Fault. Is automatically cleared
upon a transition to INITIALIZE state, if corresponding *_UV_MASK
bit in register INT_MASK_UV is '1' 0h = No Fault detected 1h = Fault detected |
2 | BUCK1_NEG_OC | R/W1C | 0h | BUCK1 Negative Overcurrent Fault 0h = No Fault detected 1h = Fault detected |
1 | BUCK1_OC | R/W1C | 0h | BUCK1 Positive Overcurrent Fault 0h = No Fault detected 1h = Fault detected |
0 | BUCK1_SCG | R/W1C | 0h | BUCK1 Short Circuit to Ground Fault 0h = No Fault detected 1h = Fault detected |
INT_SYSTEM is shown in Figure 6-66 and described in Table 6-57.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SENSOR_0_HOT | SENSOR_1_HOT | SENSOR_2_HOT | SENSOR_3_HOT | SENSOR_0_WARM | SENSOR_1_WARM | SENSOR_2_WARM | SENSOR_3_WARM |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SENSOR_0_HOT | R/W1C | 0h | TSD Hot detection for sensor 0 0h = No Fault detected 1h = Fault detected |
6 | SENSOR_1_HOT | R/W1C | 0h | TSD Hot detection for sensor 1 0h = No Fault detected 1h = Fault detected |
5 | SENSOR_2_HOT | R/W1C | 0h | TSD Hot detection for sensor 2 0h = No Fault detected 1h = Fault detected |
4 | SENSOR_3_HOT | R/W1C | 0h | TSD Hot detection for sensor 3 0h = No Fault detected 1h = Fault detected |
3 | SENSOR_0_WARM | R/W1C | 0h | TSD Warm detection for sensor 0. Is automatically
cleared upon a transition to INITIALIZE state, if corresponding
*_WARM_MASK bit in register MASK_CONFIG is '1' 0h = No Fault detected 1h = Fault detected |
2 | SENSOR_1_WARM | R/W1C | 0h | TSD Warm detection for sensor 1. Is automatically
cleared upon a transition to INITIALIZE state, if corresponding
*_WARM_MASK bit in register MASK_CONFIG is '1' 0h = No Fault detected 1h = Fault detected |
1 | SENSOR_2_WARM | R/W1C | 0h | TSD Warm detection for sensor 2. Is automatically
cleared upon a transition to INITIALIZE state, if corresponding
*_WARM_MASK bit in register MASK_CONFIG is '1' 0h = No Fault detected 1h = Fault detected |
0 | SENSOR_3_WARM | R/W1C | 0h | TSD Warm detection for sensor 3. Is automatically
cleared upon a transition to INITIALIZE state, if corresponding
*_WARM_MASK bit in register MASK_CONFIG is '1' 0h = No Fault detected 1h = Fault detected |
INT_RV is shown in Figure 6-67 and described in Table 6-58.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LDO4_RV | LDO3_RV | LDO2_RV | LDO1_RV | BUCK3_RV | BUCK2_RV | BUCK1_RV |
R-X | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | X | Reserved |
6 | LDO4_RV | R/W1C | 0h | RV event detected on LDO4 rail during rail-turn-on,
or after 4-5 ms during discharge checks prior to entering power
sequence to ACTIVE state 0h = No RV detected 1h = RV detected |
5 | LDO3_RV | R/W1C | 0h | RV event detected on LDO3 rail during rail-turn-on,
or after 4-5 ms during discharge checks prior to entering power
sequence to ACTIVE state 0h = No RV detected 1h = RV detected |
4 | LDO2_RV | R/W1C | 0h | RV event detected on LDO2 rail during rail-turn-on,
or after 4-5 ms during discharge checks prior to entering power
sequence to ACTIVE state 0h = No RV detected 1h = RV detected |
3 | LDO1_RV | R/W1C | 0h | RV event detected on LDO1 rail during rail-turn-on,
or after 4-5 ms during discharge checks prior to entering power
sequence to ACTIVE state 0h = No RV detected 1h = RV detected |
2 | BUCK3_RV | R/W1C | 0h | RV event detected on BUCK3 rail during rail-turn-on,
or after 4-5 ms during discharge checks prior to entering power
sequence to ACTIVE state 0h = No RV detected 1h = RV detected |
1 | BUCK2_RV | R/W1C | 0h | RV event detected on BUCK2 rail during rail-turn-on,
or after 4-5 ms during discharge checks prior to entering power
sequence to ACTIVE state 0h = No RV detected 1h = RV detected |
0 | BUCK1_RV | R/W1C | 0h | RV event detected on BUCK1 rail during rail-turn-on,
or after 4-5 ms during discharge checks prior to entering power
sequence to ACTIVE state 0h = No RV detected 1h = RV detected |
INT_TIMEOUT_RV_SD is shown in Figure 6-68 and described in Table 6-59.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TIMEOUT | LDO4_RV_SD | LDO3_RV_SD | LDO2_RV_SD | LDO1_RV_SD | BUCK3_RV_SD | BUCK2_RV_SD | BUCK1_RV_SD |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | TIMEOUT | R/W1C | 0h | Is set if ShutDown occurred due to a TimeOut while:
1. Transitioning to ACTIVE state, and one or more rails did not rise
past the UV level at the end of the assigned slot (and UV on this
rail is configured as a SD fault). Which rail(s) is/are indicated by
the *_UV bits in the INT_* registers. 2. Transitioning to STANDBY
state, and one or more rails did not fall below the SCG level at the
end of the assigned slot and discharge is enabled for that rail
(which rail(s) is/are indicated by the corresponding RV_SD bit(s) in
this register). 0h = No SD due to TimeOut occurred 1h = SD due to TimeOut occurred |
6 | LDO4_RV_SD | R/W1C | 0h | RV on LDO4 rail caused a shutdown during: 1. A
transition to STANDBY state, this rail did not discharge at the end
of the assigned slot and discharge is enabled for this rail 2. A
transition to STANDBY state, RV was observed on this rail during the
transition after this rail was disabled and discharge was enabled 3.
A transition to ACTIVE state, RV was observed on this rail during
the transition when this rail was OFF (rails are expected to be
discharged before commencing the sequence to ACTIVE) 4. This rail
did not discharge and therefore caused a Timeout-SD while attempting
to discharge all rails at the start of a transition from STANDBY to
ACTIVE (TIMEOUT bit gets also set in this case) 0h = No SD due to RV/DISCHARGE_TIMEOUT on LDO4 occurred 1h = SD due to RV/DISCHARGE_TIMEOUT on LDO4 occurred |
5 | LDO3_RV_SD | R/W1C | 0h | RV on LDO4 rail caused a shutdown during: 1. A
transition to STANDBY state, this rail did not discharge at the end
of the assigned slot and discharge is enabled for this rail 2. A
transition to STANDBY state, RV was observed on this rail during the
transition after this rail was disabled and discharge was enabled 3.
A transition to ACTIVE state, RV was observed on this rail during
the transition when this rail was OFF (rails are expected to be
discharged before commencing the sequence to ACTIVE) 4. This rail
did not discharge and therefore caused a Timeout-SD while attempting
to discharge all rails at the start of a transition from STANDBY to
ACTIVE (TIMEOUT bit gets also set in this case) 0h = No SD due to RV/DISCHARGE_TIMEOUT on LDO3 occurred 1h = SD due to RV/DISCHARGE_TIMEOUT on LDO3 occurred |
4 | LDO2_RV_SD | R/W1C | 0h | RV on LDO4 rail caused a shutdown during: 1. A
transition to STANDBY state, this rail did not discharge at the end
of the assigned slot and discharge is enabled for this rail 2. A
transition to STANDBY state, RV was observed on this rail during the
transition after this rail was disabled and discharge was enabled 3.
A transition to ACTIVE state, RV was observed on this rail during
the transition when this rail was OFF (rails are expected to be
discharged before commencing the sequence to ACTIVE) 4. This rail
did not discharge and therefore caused a Timeout-SD while attempting
to discharge all rails at the start of a transition from STANDBY to
ACTIVE (TIMEOUT bit gets also set in this case) 0h = No SD due to RV/DISCHARGE_TIMEOUT on LDO2 occurred 1h = SD due to RV/DISCHARGE_TIMEOUT on LDO2 occurred |
3 | LDO1_RV_SD | R/W1C | 0h | RV on LDO4 rail caused a shutdown during: 1. A
transition to STANDBY state, this rail did not discharge at the end
of the assigned slot and discharge is enabled for this rail 2. A
transition to STANDBY state, RV was observed on this rail during the
transition after this rail was disabled and discharge was enabled 3.
A transition to ACTIVE state, RV was observed on this rail during
the transition when this rail was OFF (rails are expected to be
discharged before commencing the sequence to ACTIVE) 4. This rail
did not discharge and therefore caused a Timeout-SD while attempting
to discharge all rails at the start of a transition from STANDBY to
ACTIVE (TIMEOUT bit gets also set in this case) 0h = No SD due to RV/DISCHARGE_TIMEOUT on LDO1 occurred 1h = SD due to RV/DISCHARGE_TIMEOUT on LDO1 occurred |
2 | BUCK3_RV_SD | R/W1C | 0h | RV on LDO4 rail caused a shutdown during: 1. A
transition to STANDBY state, this rail did not discharge at the end
of the assigned slot and discharge is enabled for this rail 2. A
transition to STANDBY state, RV was observed on this rail during the
transition after this rail was disabled and discharge was enabled 3.
A transition to ACTIVE state, RV was observed on this rail during
the transition when this rail was OFF (rails are expected to be
discharged before commencing the sequence to ACTIVE) 4. This rail
did not discharge and therefore caused a Timeout-SD while attempting
to discharge all rails at the start of a transition from STANDBY to
ACTIVE (TIMEOUT bit gets also set in this case) 0h = No SD due to RV/DISCHARGE_TIMEOUT on BUCK3 occurred 1h = SD due to RV/DISCHARGE_TIMEOUT on BUCK3 occurred |
1 | BUCK2_RV_SD | R/W1C | 0h | RV on LDO4 rail caused a shutdown during: 1. A
transition to STANDBY state, this rail did not discharge at the end
of the assigned slot and discharge is enabled for this rail 2. A
transition to STANDBY state, RV was observed on this rail during the
transition after this rail was disabled and discharge was enabled 3.
A transition to ACTIVE state, RV was observed on this rail during
the transition when this rail was OFF (rails are expected to be
discharged before commencing the sequence to ACTIVE) 4. This rail
did not discharge and therefore caused a Timeout-SD while attempting
to discharge all rails at the start of a transition from STANDBY to
ACTIVE (TIMEOUT bit gets also set in this case) 0h = No SD due to RV/DISCHARGE_TIMEOUT on BUCK2 occurred 1h = SD due to RV/DISCHARGE_TIMEOUT on BUCK2 occurred |
0 | BUCK1_RV_SD | R/W1C | 0h | RV on LDO4 rail caused a shutdown during: 1. A
transition to STANDBY state, this rail did not discharge at the end
of the assigned slot and discharge is enabled for this rail 2. A
transition to STANDBY state, RV was observed on this rail during the
transition after this rail was disabled and discharge was enabled 3.
A transition to ACTIVE state, RV was observed on this rail during
the transition when this rail was OFF (rails are expected to be
discharged before commencing the sequence to ACTIVE) 4. This rail
did not discharge and therefore caused a Timeout-SD while attempting
to discharge all rails at the start of a transition from STANDBY to
ACTIVE (TIMEOUT bit gets also set in this case) 0h = No SD due to RV/DISCHARGE_TIMEOUT on BUCK1 occurred 1h = SD due to RV/DISCHARGE_TIMEOUT on BUCK1 occurred |
INT_PB is shown in Figure 6-69 and described in Table 6-60.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | PB_REAL_TIME_STATUS | PB_RISING_EDGE_DETECTED | PB_FALLING_EDGE_DETECTED |
R-X | R-X | R-X | R-X | R-X | R-1h | R/W1C-0h | R/W1C-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | X | Reserved |
6 | RESERVED | R | X | Reserved |
5 | RESERVED | R | X | Reserved |
4 | RESERVED | R | X | Reserved |
3 | RESERVED | R | X | Reserved |
2 | PB_REAL_TIME_STATUS | R | 1h | Deglitched (64-128ms) real-time status of PB pin.
Valid only when EN/PB/VSENSE pin is configured as PB. 0h = Current deglitched status of PB: PRESSED 1h = Current deglitched status of PB: RELEASED |
1 | PB_RISING_EDGE_DETECTED | R/W1C | 0h | PB was released for > deglitch period (64-128ms)
since the previous time this bit was cleared. This bit when set,
does assert nINT pin (if config bit MASK_INT_FOR_PB='0'). 0h = No PB-release detected 1h = PB-release detected |
0 | PB_FALLING_EDGE_DETECTED | R/W1C | 0h | PB was pressed for > deglitch period (64-128ms)
since the previous time this bit was cleared. This bit when set,
does assert nINT pin (if config bit MASK_INT_FOR_PB='0'). 0h = No PB-press detected 1h = PB-press detected |
USER_NVM_CMD_REG is shown in Figure 6-70 and described in Table 6-61.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NVM_VERIFY_RESULT | CUST_NVM_VERIFY_DONE | CUST_PROG_DONE | I2C_OSC_ON | USER_NVM_CMD | |||
R-0h | R/W1C-0h | R/W1C-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | NVM_VERIFY_RESULT | R | 0h | After an CUST_NVM_VERIFY_CMD is executed, this bit
gives the result of the operation. (1 = fail, 0= pass). If '1', can
only be cleared if a subsequent CUST_NVM_VERIFY_CMD passes. 0h = PASS 1h = FAIL |
6 | CUST_NVM_VERIFY_DONE | R/W1C | 0h | Is set to '1' after a CUST_NVM_VERIFY_CMD is
executed. Remains '1' until W1C by user. 0h = Not yet done / not in progress 1h = Done |
5 | CUST_PROG_DONE | R/W1C | 0h | Is set to '1' after a CUST_PROG_CMD is executed.
Remains '1' until W1C by user. 0h = Not yet done / not in progress 1h = Done |
4 | I2C_OSC_ON | R | 0h | This register field is set to '1' if an EN_OSC_DIY is
received. 0h = OSC not controlled via I2C 1h = OSC unconditionally ON due to I2C command EN_OSC_DIY |
3-0 | USER_NVM_CMD | R | 0h | Commands to enter DIY programming mode and program
user NVM space. Always reads as 0. 6h = DIS_OSC_DIY 7h = CUST_NVM_VERIFY_CMD 9h = EN_OSC_DIY Ah = CUST_PROG_CMD |
POWER_UP_STATUS_REG is shown in Figure 6-71 and described in Table 6-62.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POWER_UP_FROM_FSD | POWER_UP_FROM_EN_PB_VSENSE | COLD_RESET_ISSUED | STATE | RETRY_COUNT | POWER_UP_FROM_OFF | ||
R/W1C-0h | R/W1C-0h | R/W1C-0h | R-0h | R-0h | R/W1C-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | POWER_UP_FROM_FSD | R/W1C | 0h | Is set if ON_REQ was triggered due to FSD 0h = No power-up via FSD detected 1h = Power-up via FSD detected |
6 | POWER_UP_FROM_EN_PB_VSENSE | R/W1C | 0h | Is set if ON_REQ was triggered due to EN/PB/VSENSE
pin 0h = No power-up via pin detected 1h = Power-up via pin detected |
5 | COLD_RESET_ISSUED | R/W1C | 0h | Is set if we received a COLD_RESET over pin or over
I2C 0h = No COLD RESET received 1h = COLD RESET received either through pin or I2C |
4-3 | STATE | R | 0h | Indicates the current device state 0h = Transition state 1h = INITIALIZE 2h = STANDBY 3h = ACTIVE |
2-1 | RETRY_COUNT | R | 0h | Reads the current retry count in the state machine. If RETRY_COUNT = 3 and is not masked, device does not power up. |
0 | POWER_UP_FROM_OFF | R/W1C | 0h | Indicates if we powered up from OFF state (POR was
asserted) 0h = OFF state not entered since the previous clearing of this bit 1h = OFF state was entered since the previous clearing of this bit |
SPARE_2 is shown in Figure 6-72 and described in Table 6-63.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPARE_2_1 | SPARE_2_2 | SPARE_2_3 | SPARE_2_4 | SPARE_2_5 | SPARE_2_6 | SPARE_2_7 | SPARE_2_8 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SPARE_2_1 | R/W | 0h | Spare bit in user non-NVM space |
6 | SPARE_2_2 | R/W | 0h | Spare bit in user non-NVM space |
5 | SPARE_2_3 | R/W | 0h | Spare bit in user non-NVM space |
4 | SPARE_2_4 | R/W | 0h | Spare bit in user non-NVM space |
3 | SPARE_2_5 | R/W | 0h | Spare bit in user non-NVM space |
2 | SPARE_2_6 | R/W | 0h | Spare bit in user non-NVM space |
1 | SPARE_2_7 | R/W | 0h | Spare bit in user non-NVM space |
0 | SPARE_2_8 | R/W | 0h | Spare bit in user non-NVM space |
SPARE_3 is shown in Figure 6-73 and described in Table 6-64.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPARE_3_1 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | SPARE_3_1 | R/W | 0h | Spare bit in user non-NVM space |
FACTORY_CONFIG_2 is shown in Figure 6-74 and described in Table 6-65.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NVM_REVISION | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | ||
R-X | R-X | R-X | R-X | R-X | R-X | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | NVM_REVISION | R | X | Specifies the version of the NVM configuration Note:
This register can be programmed only by the manufacturer. 0h = V0 1h = V1 ... |
4 | RESERVED | R | X | Reserved |
3 | RESERVED | R | X | Reserved |
2 | RESERVED | R | X | Reserved |
1 | RESERVED | R | X | Reserved |
0 | RESERVED | R | X | Reserved |