JAJSOR4B December 2022 – June 2024 TPS65220
PRODUCTION DATA
Input Capacitance - LDO3, LDO4
The input supply pin for LDO3 and LDO4 require an input decoupling capacitor to minimize input ripple voltage. These two LDOs share the same input supply pin. Using a minimum of 4.7-µF input capacitance is recommended. Depending on the input voltage of the LDO, a 6.3 V or higher rated capacitor can be used. The same input capacitance requirements applies when the LDO is configured as LDO or load-switch.
Output Capacitance - LDO3, LDO4
LDO outputs require an output capacitor to hold up the output voltage during a load step or changes to the input voltage. Using a 2.2-µF local capacitance for each LDO output with ESR of 10 mΩ or less is recommended. Local capacitance must not exceed 4uF (after derating). This requirement excludes any capacitance seen at the load and only refers to the capacitance seen close to the device. The total capacitance (local + point of load) that each LDO can support depends on the NVM configuration. Table 7-3 shows the maximum total output capacitance allowed. Refer to the Technical Reference Manual (TRM) for the specific orderable part number to identify the LDO configuration based on the register settings and the applicable maximum total capacitance.
Register setting | LDO ramp config | Max total capacitance (2.2uF local + point of load) |
---|---|---|
LDOx_SLOW_PU_RAMP | ||
0 | fast ramp | 15uF |
1 | slow ramp | 30uF |