JAJSOR4B December 2022 – June 2024 TPS65220
PRODUCTION DATA
POS | PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
Electrical Characteristics | |||||||
9.1.1 | VOL | Low-level Output Voltage (open-drain) | VIO = 3.6V, IOL = 2mA, GPO1, GPO2, GPIO, nRSTOUT, nINT | 0.40 | V | ||
9.1.2 | VIL | Low-level Input Voltage | EN/PB, MODE/STBY, MODE/RESET and VSEL_SD/VSEL_DDR, GPIO | 0.4 | V | ||
9.1.3 | VIH | High-level Input Voltage | EN/PB, MODE/STBY, MODE/RESET and VSEL_SD/VSEL_DDR, GPIO | 1.26 | V | ||
9.1.4 | VVSENSE | VSENSE Comparator Threshold (EN/PB/VSENSE) | 1.08 | 1.20 | 1.32 | V | |
9.1.5 | VVSENSE_HYS | VSENSE Comparator Hysteresis (EN/PB/VSENSE) | 8 | 30 | 55 | mV | |
9.1.6 | ILKG | Input leakage current (GPIO, EN/PB/VSENSE, MODE/STBY, MODE/RESET, VSEL_SD/VSEL/DDR) | VIN = 3.3 V | 1.0 | μA | ||
9.1.7 | CIN | Internal input pin capacitance (GPIO, EN/PB/VSENSE, MODE/STBY, MODE/RESET, VSEL_SD/VSEL/DDR) | 10 | pF | |||
9.1.8 | IPD | pull-down current, available 100us after VSYS is applied | on pins GPO1, GPO2, GPIO, MODE/STBY, MODE/RESET, VSEL_SD/VSEL_DDR, nINT, nRSTOUT | 18 | 25 | 35 | nA |
9.1.9 | ILKG_VSYS_ONLY | Pin leakage when VSYS is present, but digital supply VDD1P8 is not | SDA only | 1 | μA | ||
9.1.10 | VPIN_VSYS_ONLY | Pin voltage when VSYS is present, but digital supply VDD1P8 is not | GPO1, GPO2, GPIO, nRSTOUT, nINT, IOL=2mA | 0.4 | V | ||
Timing Requirements | |||||||
9.2.1a | tFALL | Output buffer fall time (90% to 10%) | GPO1, GPO2, GPIO, nRSTOUT, nINT, COUT = 10pF | 50 | ns | ||
9.2.1b | tRISE | GPIO Output buffer rise time (10% to 90%) | GPIO, applicable in Multi-PMIC-configuration | 5 | μs | ||
9.2.1.1 | tDLY_FALL | Output buffer falling time delay (input crossing 50% to output crossing 50%) |
COUT = 10pF | 50 | ns | ||
9.2.2.1 | tDLY_RISE | Open Drain Output buffer rising time delay (digital input to output crossing 50%) |
COUT = 10pF, RPU=1k (external pull up), VIO = 1.8V | 300 | ns | ||
9.2.2.3 | FLT_HIGHDuration | Time the digital has allotted for the test to see if the pin can be pulled high internally | COUT = 10pF | 15 | μs | ||
9.2.2.4 | FLT_LOWDuration | Time the digital has allotted for the test to see if the pin can be pulled low internally | COUT = 10pF | 15 | μs | ||
9.2.2a | tPB_ON_SLOW | EN/PB/VSENSE, Wait Time PB, ON request, slow | PB, falling Edge | 540 | 600 | 660 | ms |
9.2.2b | tPB_ON_FAST | EN/PB/VSENSE, Wait Time PB, ON request, fast | PB, falling Edge | 180 | 200 | 220 | ms |
9.2.3 | tPB_OFF | EN/PB/VSENSE, Wait Time PB, OFF request | PB, falling Edge | 7.2 | 8.0 | 8.8 | s |
9.2.4 | tPB_RISE_DEGL | EN/PB/VSENSE, Deglitch time PB, rising edge | PB, rising Edge, applicable after the successful long-press-OFF-request | 115 | 200 | 275 | ms |
9.2.5 | tPB_INT_DEGL | EN/PB/VSENSE, Deglitch time PB, rising or falling edge | PB, rising or falling Edge | 59 | 100 | 137 | ms |
9.2.6 | tDEGL_EN_Rise_Slow | EN/PB/VSENSE, DeglitchTime EN slow, rising | EN, rising Edge | 45 | 50 | 55 | ms |
9.2.7 | tDEGL_EN_Rise_Fast | EN/PB/VSENSE, DeglitchTime EN fast, rising | EN, rising Edge | 60 | 120 | 150 | μs |
9.2.8 | tDEGL_EN_Fall | EN/PB/VSENSE, DeglitchTime EN, falling | EN, falling Edge | 50 | 70 | 93 | μs |
9.2.9 | tDEGL_VSENSE_Rise | VSENSE rising: only gated by VSYSPOR_Rising and VSENSE-voltage | VSENSE, rising Edge | N/A | |||
9.2.10 | tDEGL_VSENSE_Fall | EN/PB/VSENSE, DeglitchTime VSENSE, falling, regardless of fast/slow setting | VSENSE, falling Edge | 50 | 70 | 93 | μs |
9.2.11 | tDEGL_EN/VSENSE_I2C | EN/VSENSE falling edge deglitch time after I2C-triggered shutdown | EN/VSENSE falling edge after previous shutdown request by I2C (shorter than 9.2.8) | 12.5 | 25 | 37.5 | μs |
9.2.12 | tDEGL_RESET | MODE/RESET, Deglitch Time RESET | RESET, rising and falling Edge | 90 | 120 | 150 | μs |
9.2.13 | tDEGL_MFP | Deglitch Time MODE/STBY, MODE(not/RESET), VSEL_SD/VSEL_DDR | Rising and falling Edge | 90 | 120 | 150 | μs |
9.2.14 | tDEGL_GPIO | Deglitch Time GPIO | Rising and falling Edge | 6.6 | 15.6 | 18 | μs |
9.2.15 | tREACTION_ON | ON-request propagation delay (after deglitch) | Includes oscillator startup, sampling delay and reaction delay (excluding deglitch) | 75 | 103 | µs | |
9.2.16 | tREACTION_OFF | OFF-request propagation delay (after deglitch) | Includes sampling delay and reaction delay (excluding deglitch) | 39 | 56 | 73.5 | µs |