SLVSD66
September 2015
TPS65233-1
PRODUCTION DATA.
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
I2C Interface Timing Requirements
6.7
Switching Characteristics
6.8
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Boost Converter
7.3.2
Linear Regulator and Current Limit
7.3.3
Charge Pump
7.3.4
Slew Rate Control
7.3.5
Short Circuit Protection, Hiccup, and Overtemperature Protection
7.4
Device Functional Modes
7.4.1
Tone Generation
7.4.2
Serial Interface
7.5
Programming
7.5.1
I2C Update Sequence
7.6
Register Map
7.6.1
Control Register 1 - Address: 0x00H
7.6.2
Control Register 2 - Address: 0x01H
7.6.3
Status Register 1 - Address: 0x02H
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Detailed Design Procedure
8.2.1.1
Capacitor Selection
8.2.2
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Community Resources
11.2
Trademarks
11.3
Electrostatic Discharge Caution
11.4
Glossary
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RTE|16
MPQF149D
サーマルパッド・メカニカル・データ
RTE|16
QFND525B
発注情報
slvsd66_oa
slvsd66_pm
4 Revision History
DATE
REVISION
NOTES
September 2015
*
Initial release.