JAJSFS2D November   2015  – May 2021 TPS65235

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Boost Converter
      2. 7.3.2  Linear Regulator and Current Limit
      3. 7.3.3  Boost Converter Current Limit
      4. 7.3.4  Charge Pump
      5. 7.3.5  Slew Rate Control
      6. 7.3.6  Short Circuit Protection, Hiccup and Overtemperature Protection
      7. 7.3.7  Tone Generation
      8. 7.3.8  Tone Detection
      9. 7.3.9  Disable and Enable
      10. 7.3.10 Component Selection
        1. 7.3.10.1 Boost Inductor
        2. 7.3.10.2 Capacitor Selection
        3. 7.3.10.3 Surge Components
        4. 7.3.10.4 Consideration for Boost Filtering and LNB Noise
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 TPS65235 I2C Update Sequence
    6. 7.6 Register Maps
      1. 7.6.1 Control Register 1 (address = 0x00H) [reset = 00010000]
      2. 7.6.2 Control Register 2 (address = 0x01H) [reset = 0000101]
      3. 7.6.3 Status Register (address = 0x02H) [reset = x0100000]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application for DiSEqc1.x Support
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
      4. 8.2.4 Typical Application for DiSEqc2.x Support
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
        3. 8.2.4.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.10.2 Capacitor Selection

TPS65235 has a 1 MHz non‐synchronous boost converter integrated and the boost converter features the internal compensation network. TPS65235 works well with both ceramic capacitor and electrolytic capacitor.

In TPS65235 application, the recommended ceramic capacitors rated are at least X7R/X5R, 35 V rating and 1206 size for the achieving lower LNB output ripple. Table 7-1 shows the recommended ceramic capacitors list for both 4.7uH and 10uH boost inductors.

If lower cost is demanded, a 100-µF electrolytic (Low ESR) and a 10-µF/35-V ceramic capacitor also work well, this solution provides lower system cost.

Table 7-1 Boost Inductor and Capacitor Selections
Boost InductorCapacitorsTolerance (%)Rating (V)Size
10 µH2 x 22 µF±10351206
2 x 10 µF±10351206
4.7 µH2 x 22 µF±10351206
2 x 10 µF±10351206
22 µF±10351206

Figure 7-6 and Figure 7-7 show a Bode plot of boost loop with 4.7 µH / 10 µH inductance and 4 µF, 5 µF, 7.5 µF, 10 µF, 15 µF and 20 µF of boost capacitance after degrading. As the boost capacitance increases, the phase margin decreases.

GUID-F8AD8767-B462-4DBA-8345-5C6FFD2A8B2A-low.gifFigure 7-6 Gain and Phase Margin of the Boost Loop With Different Boost Capacitance (VIN = 12 V, VOUT = 18.2 V, ILOAD = 1 A, FSW = 1 MHz, 4.7 µH, Typical Bode Plot)
GUID-FC56A8EB-9229-422B-9565-F43AAE988877-low.gifFigure 7-7 Gain and Phase Margin of the Boost Loop With Different Boost Capacitance (VIN = 12 V, VOUT = 18.2 V, ILOAD = 1 A, FSW = 1 MHz, 10 µH, Typical Bode Plot)