JAJSBH8G June   2010  – February 2018 TPS65251

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Adjustable Switching Frequency
      2. 8.3.2  Synchronization
      3. 8.3.3  Out-of-Phase Operation
      4. 8.3.4  Delayed Start-Up
      5. 8.3.5  Soft-Start Time
      6. 8.3.6  Adjusting the Output Voltage
      7. 8.3.7  Input Capacitor
      8. 8.3.8  Bootstrap Capacitor
      9. 8.3.9  Error Amplifier
      10. 8.3.10 Loop Compensation
      11. 8.3.11 Slope Compensation
      12. 8.3.12 Powergood
      13. 8.3.13 Current Limit Protection
      14. 8.3.14 Overvoltage Transient Protection
      15. 8.3.15 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low-Power Mode Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Loop Compensation Circuit
        2. 9.2.2.2  Selecting the Switching Frequency
        3. 9.2.2.3  Output Inductor Selection
        4. 9.2.2.4  Output Capacitor
        5. 9.2.2.5  Input Capacitor
        6. 9.2.2.6  Soft-Start Capacitor
        7. 9.2.2.7  Bootstrap Capacitor Selection
        8. 9.2.2.8  Adjustable Current Limiting Resistor Selection
        9. 9.2.2.9  Output Voltage and Feedback Resistors Selection
        10. 9.2.2.10 Compensation
        11. 9.2.2.11 3.3-V and 6.5-V LDO Regulators
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Power Dissipation
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

TJ = –40°C to 125°C, VIN = 12 V, fSW = 1 MHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY UVLO AND INTERNAL SUPPLY VOLTAGE
VIN Input Voltage range 4.5 18 V
IDDSDN Shutdown EN pin = low for all converters 1.3 mA
IDDQ Quiescent, low-power disabled (Lo) Converters enabled, no load
Buck 1 = 3.3 V, Buck 2 = 2.5 V, Buck 3 = 7.5 V,
L = 4.7 µH , fSW = 800 kHz		 20 mA
IDDQ_LOW_P Quiescent, low-power enabled (Hi) Converters enabled, no load
Buck 1 = 3.3 V, Buck 2 = 2.5 V, Buck 3 = 7.5 V,
L = 4.7 µH , fSW = 800 kHz		 1.5 mA
UVLOVIN VIN under voltage lockout Rising VIN 4.22 V
Falling VIN 4.1
UVLODEGLITCH Both edges 110 µs
V3V Internal biasing supply ILOAD = 0 mA 3.2 3.3 3.4 V
I3V Biasing supply output current VIN = 12 V 10 mA
V7V Internal biasing supply ILOAD = 0 mA 5.63 6.25 6.88 V
I7V Biasing supply output current VIN = 12 V 10 mA
V7VUVLO UVLO for internal V7V rail Rising V7V 3.8 V
Falling V7V 3.6
V7VUVLO_DEGLITCH Falling edge 110 µs
BUCK CONVERTERS (ENABLE CIRCUIT, CURRENT LIMIT, SOFT-START, SWITCHING FREQUENCY AND SYNC CIRCUIT, LOW-POWER MODE)
VIH Enable threshold high V3p3 = 3.2 V - 3.4 V, VENX rising 1.55 1.82 V
Enable high level External GPIO, VENX rising 0.66 x V3V
VIL Enable threshold low V3p3 = 3.2 V - 3.4 V, VENX falling 0.98 1.24 V
Enable low level External GPIO, VENX falling 0.33 x V3V
REN_DIS Enable discharge resistor –10% 2.1 10% kΩ
ICHEN Pullup current enable pin 1.1 µA
tD Discharge time enable pins Power-up 10 ms
ISS Soft-start pin current source 5 µA
FSW_BK Converter switching frequency range Set externally with resistor 0.3 2.2 MHz
RFSW Frequency setting resistor Depending on set frequency 50 600 kΩ
fSW_TOL Internal oscillator accuracy fSW = 800 kHz –10% 10%
VSYNCH External clock threshold high V3p3 = 3.3 V 1.55 V
VSYNCL External clock threshold Low V3p3 = 3.3 V 1.24 V
SYNCRANGE Synchronization range 0.2 2.2 MHz
SYNCCLK_MIN Sync signal minimum duty cycle 40%
SYNCCLK_MAX Sync signal maximum duty cycle 60%
VIHLOW_P Low-power mode threshold high V3p3 = 3.3 V, VENX rising 1.55 V
VILLOW_P Low-power mode threshold Low V3p3 = 3.3 V, VENX falling 0.98 1.24 V
FEEDBACK, REGULATION, OUTPUT STAGE
VFB Feedback voltage VIN = 12V TJ = 25°C –1% 0.8 1% V
VIN = 4.5 to 18 V –2% 0.8 2%
IFB Feedback leakage current 50 nA
tON_MIN Minimum on-time
(current sense blanking)		 80 120 ns
VLINEREG Line regulation - DC
∆VOUT/∆VINB 		VINB = 4.5 to 18 V,
IOUT = 1000 mA		 0.5 % VOUT
VLOADREG Load regulation - DC
∆VOUT/∆IOUT 		IOUT = 10 % - 90%
IOUT,MAX 		0.5 % VOUT/A
MOSFET (BUCK 1)
H.S. Switch Turn-On resistance high-side FET on CH1 VIN = 12 V, TJ = 25°C 95 mΩ
L.S. Switch Turn-On resistance low-side FET on CH1 VIN = 12 V, TJ = 25°C 50 mΩ
MOSFET (BUCK 2)
H.S. Switch Turn-On resistance high-side FET on CH2 VIN = 12 V, TJ = 25°C 120 mΩ
L.S. Switch Turn-On resistance low-side FET on CH2 VIN = 12 V, TJ = 25°C 80 mΩ
MOSFET (BUCK 3)
H.S. Switch Turn-On resistance high-side FET on CH3 VIN = 12 V, TJ = 25°C 120 mΩ
L.S. Switch Turn-On resistance low-side FET on CH3 VIN = 12 V, TJ = 25°C 80 mΩ
ERROR AMPLIFIER
gM Error amplifier transconductance –2 µA < ICOMP< 2 µA 130 µS
gmPS COMP to ILX gM ILX = 0.5 A 10 A/V
POWERGOOD RESET GENERATOR
VUVBUCKX Threshold voltage for buck under voltage Output falling (device will be disabled after tON_HICCUP ) 85%
Output rising (PG will be asserted) 90%
tUV_deglitch Deglitch time (both edges) Each buck 11 ms
tON_HICCUP Hiccup mode ON time VUVBUCKX asserted 12 ms
tOFF_HICCUP Hiccup mode OFF time before restart is attempted All converters disabled. Once tOFF_HICCUP elapses, all converters will go through sequencing again. 15 ms
VOVBUCKX Threshold voltage for buck overvoltage Output rising (high-side FET will be forced off) 109%
Output falling (high-side FET will be allowed to switch ) 107%
tRP Minimum reset period Measured after minimum reset period of all bucks power-up successfully 1 s
THERMAL SHUTDOWN
TTRIP Thermal shutdown trip point Rising temperature 160  °C
THYST Thermal shutdown hysteresis Device restarts 20 °C
TTRIP_DEGLITCH Thermal shutdown deglitch 110 µs
CURRENT LIMIT PROTECTION
RLIM1 Limit resistance range Buck 1 75 300 kΩ
RLIM2&3 Limit resistance range Bucks 2 and 3 100 300 kΩ
ILIM1 Buck 1 adjustable current limit range VIN = 12 V, fSW = 500 kHz,
see Figure 17 		1.2 5.5 A
ILIM2 Buck 2 adjustable current limit range VIN = 12 V, fSW = 500 kHz,
see Figure 18 		1 4.1 A
ILIM3 Buck 3 adjustable current limit range VIN = 12 V, fSW = 500 kHz,
see Figure 19 		1.3 4.4 A