JAJSH01 February   2019 TPS65295

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     代表的なアプリケーション
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 PWM Operation and D-CAP3 Control
      2. 8.3.2 Advanced Eco-mode Control
      3. 8.3.3 Soft Start and Prebiased Soft Start
      4. 8.3.4 Power Good
      5. 8.3.5 Overcurrent Protection and Undervoltage Protection
      6. 8.3.6 Overvoltage Protection
      7. 8.3.7 UVLO Protection
      8. 8.3.8 Output Voltage Discharge
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Light Load Operation for VDDQ Buck and VPP Buck
      2. 8.4.2 Output State Control
      3. 8.4.3 Output Sequence Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 External Component Selection
          1. 9.2.2.1.1 Inductor Selection
          2. 9.2.2.1.2 Output Capacitor Selection
          3. 9.2.2.1.3 Input Capacitor Selection
          4. 9.2.2.1.4 Bootstrap Capacitor and Resistor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information
      2. 13.1.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

TJ=-40oC to 125oC, VPVIN=12V, VPVIN_VPP=5V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY VOLTAGE
IVCC_5V VCC_5V supply current VSLP_S4 = VVTT_CNTL = 0 V 5 µA
VSLP_S4 = 5 V, VVTT_CNTL = 0 V, no load 110 µA
VSLP_S4 = VVTT_CNTL = 5 V, no load 150 µA
VIN PVIN input voltage range 4.5 18 V
UVLO
UVLO VCC_5V under-voltage lockout Wake up VCC_5V voltage 4.1 4.5 V
Shut down VCC_5V voltage 3.3 3.6 V
Hysteresis VCC_5V voltage 500 mV
VDDQ
VVDDQSNS VDDQ sense voltage 1.188 1.2 1.212 V
IVDDQSNS VDDQSNS input current VVDDQSNS =1.2 V 40 µA
IVDDQDIS VDDQ discharge current VSLP_S4 = VVTT_CNTL = 0 V, VVDDQSNS = 0.5 V 12 mA
tVDDQSS VDDQ soft-start time 1.6 2.65 ms
tVDDQDLY VDDQ ramp up delay time 2 ms
RDSONH High-side switch resistance TJ = 25°C, VPVIN = 19V, VVCC_5V = 5V 22 mΩ
RDSONL Low-side switch resistance TJ = 25°C, VPVIN = 19V, VVCC_5V = 5V 8.6 mΩ
IVDDQOCL Low-side valley current limited VOUT = 1.2 V, L = 0.68 µH 8.2 9.8 11.5 A
fsw VDDQ switching freqency 600 kHz
tOFF(MIN) Minimum off time 198 ns
PGOOD (VDDQ, VPP)
VTHPG PGOOD threshold VDDQSNS / VPPSNS falling (Fault) 87 %
VDDQSNS / VPPSNS rising (Good) 93 %
VDDQSNS / VPPSNS rising (Fault) 115 %
VDDQSNS / VPPSNS falling (Good) 110 %
IPGMAX PG sink current VPGOOD =0.5V, VSLP_S4 =VVTT_CNTL = 5 V, no load 46 mA
tPGDLY PG start-up delay PG from low to high 1 ms
VPP
VVPPSNS VPP sense voltage 2.45 2.5 2.55 V
IVPPSNS VPPSNS input current VVPPSNS =2.5 V 20 µA
IVPPDIS VPP discharge current VSLP_S4 = VVTT_CNTL = 0 V, VVPPSNS = 0.5 V 12 mA
tVPPSS VPP soft-start time 1 .0 2 ms
RDSONH High-side switch resistance TJ = 25°C, VPVIN_VPP = 5V, VVCC_5V = 5V 150 mΩ
RDSONL Low-side switch resistance TJ = 25°C, VPVIN_VPP=5V, VVCC_5V = 5V 120 mΩ
IVPPOCL Low-side valley current limited VOUT = 2.5 V, L = 4.7 µH 1.05 1.6 2.1 A
fsw VPP switching frequency 580 kHz
tOFF(MIN) Minimum off time 195 ns
tOOA OOA mode operation period VVPPSNS =2.5 V 31 µs
OVP AND UVP (VDDQ, VPP)
VOVP OVP threshold voltage OVP detect voltage 120 125 130 %
VUVP1 UVP threshold voltage UVP detect voltage 55 60 65 %
tOVPDLY OVP delay 20 µs
tUVPDLY UVP delay 250 µs
VTTREF OUTPUT
VVTTREF Output voltage 1/2* VVDDQSNS V
VVTTREF Output voltage tolerance to VDDQ TJ = 25°C, |IVTTREF| ≤100 µA, VVDDQSNS = 1.2 V 49.2 50.8 %
TJ = 25°C, |IVTTREF| ≤10mA, VVDDQSNS = 1.2 V 49 51
IVTTREFOCLSRC Source current limit VVDDQSNS = 1.2 V, VVTTREF= 0 V 10 18 mA
IVTTREFOCLSnk Sink current limit VVDDQSNS = 1.2 V, VVTTREF= 1.2 V 10 18 mA
IVTTREFDIS VTTREF discharge current TJ = 25°C, VSLP_S4 = VVTT_CNTL = 0 V, VVTTREF = 0.5 V 0.8 1.3 mA
VTT OUTPUT
VVTT Output voltage VVTTREF V
VVTTTOL Output voltage tolerance |IVTT| ≤10 mA, VVDDQSNS = 1.2 V, IVTTREF= 0 A –20 20 mV
TJ = 25°C,|IVTT| ≤1A, VVDDQSNS = 1.2 V, IVTTREF= 0 A –30 30
IVTTOCLSRC Source current limit VVDDQSNS = 1.2 V, VVTT= VVTTSNS= 0.5 V, IVTTREF=0 A 1 1.7 A
IVTTOCLSnk Sink current limit VVDDQSNS = 1.2 V, VVTT= VVTTSNS= 0.7 V, IVTTREF=0 A 1 1.7 A
IVTTLK Leakage current TJ = 25°C, VSLP_S4 = 5 V, VVTT_CNTL = 5 V, VVTT =VVTTREF 5 µA
IVTTSNSBIAS VTTSNS input bias current VSLP_S4 = 5 V, VVTT_CNTL = 5 V, VVTT =VVTTREF –0.5 0 0.5
IVTTSNSLK VTTSNS leakage current VSLP_S4 = 5 V, VVTT_CNTL = 0 V, VVTT =VVTTREF –1 0 1
IVTTDLY VTT output delay relative to VTT_CNTL 35 us
IVTTDIS VTT discharge current TJ = 25°C, VSLP_S4 = VVTT_CNTL = 0 V, VVDDQSNS = 1.2 V, VVTT =0.5V, IVTTREF =0 A 5.7 mA
SLP_S4, VTT_CNTL LOGIC THRESHOLD
VIH SLP_S4/VTT_CNTL high-level voltage 1.6 V
VIL SLP_S4/VTT_CNTL low-level voltage 0.5 V
RTOGND SLP_S4/VTT_CNTL resistance to GND 500 kΩ
THERMAL PROTECTION
TOTP OTP trip threshold 150 °C
TOTPHSY OTP hysteresis 20 °C