JAJSH01 February   2019 TPS65295

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     代表的なアプリケーション
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 PWM Operation and D-CAP3 Control
      2. 8.3.2 Advanced Eco-mode Control
      3. 8.3.3 Soft Start and Prebiased Soft Start
      4. 8.3.4 Power Good
      5. 8.3.5 Overcurrent Protection and Undervoltage Protection
      6. 8.3.6 Overvoltage Protection
      7. 8.3.7 UVLO Protection
      8. 8.3.8 Output Voltage Discharge
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Light Load Operation for VDDQ Buck and VPP Buck
      2. 8.4.2 Output State Control
      3. 8.4.3 Output Sequence Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 External Component Selection
          1. 9.2.2.1.1 Inductor Selection
          2. 9.2.2.1.2 Output Capacitor Selection
          3. 9.2.2.1.3 Input Capacitor Selection
          4. 9.2.2.1.4 Bootstrap Capacitor and Resistor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information
      2. 13.1.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.2 Output State Control

The TPS65295 has two enable input pins, SLP_S4 and VTT_CNTL, to provide simple control scheme of output state. All of VPP, VDDQ, VTTREF and VTT are turned on at S0 state (SLP_S4=VTT_CNTL=high). In S3 state (VTT_CNTL=low, SLP_S4=high), VPP, VDDQ, and VTTREF voltages are kept on while VTT is turned off and left at high impedance state (high-Z). The VTT output floats and does not sink or source current in this state. In S4/S5 states (SLP_S4=VTT_CNTL =low), all of the three outputs are turned off and discharged to GND. Each state code represents as follow: S0 = full ON, S3 = suspend to RAM (STR), S4 = suspend to disk (STD), S5 = soft OFF (see Table 1).

Table 1. VTT_CNTL and SLP_S4 Control for Output State

STATE VTT_CNTL SLP_S4 VPP VDDQ VTTREF VTT
S0 HI HI ON ON ON ON
S3 LO HI ON ON ON OFF (High-Z)
S5/S4 LO LO OFF (discharge) OFF (discharge) OFF (discharge) OFF (discharge)