JAJSH01 February   2019 TPS65295

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     代表的なアプリケーション
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 PWM Operation and D-CAP3 Control
      2. 8.3.2 Advanced Eco-mode Control
      3. 8.3.3 Soft Start and Prebiased Soft Start
      4. 8.3.4 Power Good
      5. 8.3.5 Overcurrent Protection and Undervoltage Protection
      6. 8.3.6 Overvoltage Protection
      7. 8.3.7 UVLO Protection
      8. 8.3.8 Output Voltage Discharge
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Light Load Operation for VDDQ Buck and VPP Buck
      2. 8.4.2 Output State Control
      3. 8.4.3 Output Sequence Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 External Component Selection
          1. 9.2.2.1.1 Inductor Selection
          2. 9.2.2.1.2 Output Capacitor Selection
          3. 9.2.2.1.3 Input Capacitor Selection
          4. 9.2.2.1.4 Bootstrap Capacitor and Resistor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information
      2. 13.1.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

RJE Package
18-Pin VQFN
Top View
TPS65295 pinout-01-rgy-pkg-slvsek0.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
VLDOIN 1 P Power supply input for VTT LDO. Connect VDDQ in typical application.
VTT 2 O VTT 1-A LDO output. Recommend to connect to 10-μF or larger capacitance for stability.
AGND 3 G Signal ground.
VTTSNS 4 I VTT output voltage feedback.
VDDQSNS 5 I VDDQ output voltage feedback.
VTTREF 6 O Buffered VTT reference output. Recommend to connect to 0.22-μF or larger capacitance for stability.
PVIN 7 P Input power supply for VDDQ buck.
PGOOD 8 O Power good signal open-drain output. PGOOD goes high when VPP and VDDQ output voltage are within the target range.
PGND 9 G Power ground for VDDQ buck.
VTT_CNTL 10 I VTT_CNTL signal input for VTT LDO enable control. For detail control setup, please refer toTable 1.
SLP_S4 11 I SLP_S4 signal input for VDDQ buck and VPP buck enable control. For detail control setup, please refer toTable 1.
VPPSNS 12 I VPP output voltage feedback.
VCC_5V 13 P Power supply for VPP and VDDQ buck converter control logic circuit.
PVIN_VPP 14 P Input power supply for VPP buck.
SW_VPP 15 O VPP switching node connection to the inductor and bootstrap capacitor.
PGND_VPP 16 G Power ground for VPP buck.
SW 17 O VDDQ switching node connection to the inductor and bootstrap capacitor.
BST 18 I High-side MOSFET gate driver bootstrap voltage input for VDDQ buck. Connect a capacitor between the BST pin and the SW pin.