Table 1. Switching Regulator Requirements

8.2.2.1 Duty Cycle

Use Equation 7 to calculate the duty cycle.

Equation 7.

where

• V_O = Output voltage
• V_I = Input voltage

8.2.2.2 Output Inductor Selection (L)

The minimum inductor value is calculated using the coefficient K_IND that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor, and so the typical range of this ripple current is in the range of K_IND = 0.2 to 0.3, depending on the ESR and the ripple-current rating of the output capacitor.

For this design example, use Equation 8 to calculate the inductor ripple current

Equation 8.

where

• I_O = Output current

Benefits of Low Inductor Value

• Low inductor value gives high di/dt, which allows for fewer output capacitors for good load transient response.
• Gives higher saturation current for the core due to fewer turns
• Fewer turns yields low DCR and therefore less dc inductor losses in the windings.
• High di/dt provides faster response to load steps.

Benefits of High Inductor Value

• Low ripple current leads to lower conduction losses in MOSFETs
• Low ripple; means lower RMS ripple current for capacitors
• Low ripple; yields low ac inductor losses in the core (flux) and windings (skin effect)
• Low ripple; gives continuous inductor current flow over a wide load range

For this design example a value of 10 µH was selected because of variations in temperature and manufacture. Use Equation 9 to find the value of L_Min.

Equation 9.

where

• f_SW is the regulator switching frequency
• I_Ripple = Allowable ripple current in the inductor, typically ±20% of maximum output load I_O

For this design example, use Equation 10 to calculate the inductor peak current.

Equation 10.

8.2.2.3 Output Capacitor Selection (C_O)

The selection of the output capacitor determines several parameters in the operation of the converter, the modulator pole, the voltage droop on the out capacitor, and the output ripple.

During a load step from no load to full load or changes in the input voltage, the output capacitor must hold up the output voltage above a certain level for a specified time and not issue a reset until the main regulator control loop responds to the change. The capacitance value determines the modulator pole and the roll-off frequency due to because of the LC output-filter double pole—the output ripple voltage is a product of the output capacitor ESR and ripple current.

Use Equation 11 to calculate the minimum capacitance required to maintain desired output voltage during a high-to-low load transition and prevent overshoot.

Equation 11.

where

• I_O-max is maximum output current
• I_O-min is minimum output current
• The difference between the output current, maximum to minimum, is the worst-case load step in the system.
• V_O-max is maximum tolerance of regulated output voltage
• V_O-min is the minimum tolerance of regulated output voltage

Use Equation 12 to calculate the output capacitor root-mean-square (RMS) ripple current I_{O_RMS}. This is to prevent excess heating or failure due to high ripple currents.

This parameter is sometimes specified by the manufacturer. Therfore, because of variations in temperature and manufacture, use a 10-µF capacitor with a voltage rating greater than the maximum 10-V output.

Equation 12.

8.2.2.4 External Schottky Diode (D)

The TPS65300-Q1 device requires an external ultrafast Schottky diode with fast reverse-recovery time connected between the PH and power ground pins. The diode conducts the output current during the off-state of the internal power switch. This diode must have a reverse breakdown higher than the maximum input voltage of the application. A Schottky diode is selected for lower forward voltage. The Schottky diode is selected based on the appropriate power rating, which factors in the DC-conduction losses and the AC losses because of the high switching frequencies. The power dissipation P_D is calculated with Equation 13.

Equation 13.

where

• V_FD = forward conducting voltage of Schottky diode
• C_J = junction capacitance of the Schottky diode

8.2.2.5 Input Capacitor (C_I)

The TPS65300-Q1 device requires an input ceramic decoupling capacitor type X5R or X7R and bulk capacitance to minimize input ripple voltage. The DC voltage rating of this input capacitance must be greater than the maximum input voltage. The capacitor must have an input ripple-current rating higher than the maximum input ripple current of the converter for the application. The input capacitors for power regulators are selected to have reasonable capacitance-to-volume ratio and to be fairly stable over temperature. The value of the input capacitance is based on the input voltage desired (∆V_I).

Use Equation 14 to calculate the input capacitance.

Equation 14.

Use Equation 15 to calculate the input-capacitor root-mean-square (RMS) ripple current I_{I_RMS}.

Because of variations in temperature and manufacture, use a 10-µF capacitor with a voltage rating greater than the maximum 45-V transient.

Equation 15.

8.2.2.6 Loop Compensation

The double pole is because of the output-filter components inductor and capacitor. The calculations for the following equations use values taken from Figure 14.

8.2.2.7 Loop-Control Frequency Compensation

Figure 14. Loop-Control Frequency Compensation

8.2.2.7.1 Type III Compensation

f_CO = f_SW × 0.1 (the cutoff frequency when the gain is 1 is called the unity-gain frequency).

f_CO is typically 1/5 to 1/10 of the switching frequency double-pole frequency response due to the LC output filter. The LC output filter gives a double pole, which has a –180° phase shift.

Make the two zeroes close to the double pole (LC), for example, f_Z1 ≈ f_Z2 ≈ 1/2π(LC_OUT)^1/2.

1. Make the first zero below the filter double pole (approximately 50% to 75% of f_LC)
2. Make the second zero at the filter double pole (f_LC)

Make the two poles above the crossover frequency f_CO.

3. Make the first pole at the ESR frequency (f_ESR)
4. Make the second pole at 0.5 the switching frequency

The following compensation components are integrated in the device with the following typical values. Guidelines for compensation components:

R3 = 8 kΩ, C4 = 140 pF, C2 = 20 pF

Use Equation 16 to calculate the double pole to calculate the output filter components LC.

Equation 16.

The ESR of the output capacitor C gives a zero that has a 90° phase shift. The ESR of the output capacitor must be in the range of 1 mΩ to 100 mΩ. Use Equation 17 to calculate the value of f_ESR.

Equation 17.

8.2.2.7.2 PWM Modulator Gain K

Equation 18.

where

• V_ramp = V_I / 10, V_I = Input operating voltage

8.2.2.7.3 Resistor Values

In this design example, select a value of 97.4 k Ω for R5 and use Equation 19 to calculate the value of R4.

Equation 19.

where

• V_ref = 2 V

Use Equation 20 to calculate the value of R2 for this design example.

Equation 20.

Calculate C3 based on placing a zero at 50% to 75% of the output-filter double-pole frequency (below set at 50%).

For this design example, use Equation 21 to calculate the value of C3 as 80 pF.

Equation 21.

8.2.2.7.4 Gain of Amplifier

Equation 22.

8.2.2.7.5 Poles and Zero Frequencies

The following equations were used in this design example:

Equation 23.

Figure 15. Typical Gain Versus Frequency

8.2.2.8 Power Dissipation

8.2.2.8.1 Switch-Mode Power-Supply Losses

The power dissipation losses are applicable for continuous-conduction mode operation (CCM).

1. Conduction losses
Equation 24. P_{5.3V_CON} = I_O² × R_ds(on) × (V_O/V_I)
where
• I_O = Output current
• V_O = VREG = Output voltage
• V_I = Input voltage
• f_SW = Switching frequency
2. Switching losses
Equation 25. P_{5.3V_SW} = ½ × V_I × I_O × (t_r + t_f) × f_SW
where
• t_r = FET switching rise time (t_r max = 20 ns)
• t_f = FET switching fall time (t_f max = 20 ns)
3. Gate drive losses
Equation 26. P_{5.3V_Gate} = V_drive × Qg × f_SW
where
• V_drive = FET gate-drive voltage (typically V_drive = 6 V and V_drive max = 8 V)
• Qg = 1 × 10^–9 (nC) (typical)
4. Supply losses
Equation 27. P_IC = V_I × I_q-normal

Therefore:

Equation 28. P_Total = P_CON + P_SW + P_Gate + P_{5V_Lin Reg} + P_IC

Equation 29. P_{5V_Lin Reg} = (VREG – 5 V) × I_O

Therefore, for this design, the following equations were used:

Equation 30.

For given operating ambient temperature T_A

Equation 31. T_J = T_A + R_th × P_Total

where

• T_J = Junction temperature in °C
• T_A = Ambient temperature in °C
• P_Total = Total power dissipation (watts)

For a given max junction temperature T_J-Max = 150°C

Equation 32. T_A-Max = T_J-Max – R_th × P_Total

where

• T_A-Max = Maximum ambient temperature in °C
• T_J-Max = Maximum junction temperature in °C
• R_th = Thermal resistance of package in (°C/W)

Other factors not included in the foregoing information which affect the overall efficiency and power losses are

• Inductor AC and DC losses
• Trace resistance and losses associated with the copper trace routing connection
• Schottky diode

Figure 16. Power Dissipation Derating Profile, 24-Pin PWP Package With Thermal Pad