SLVSBB6F March   2012  – July 2015 TPS65300-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Switching Characteristics
    8. 6.8  Typical Characteristics
    9. 6.9  5-V Linear Regulator (5VO)
    10. 6.10 3.3-V Linear Regulator Controller (3.3VO)
    11. 6.11 1.234-V Linear Regulator Controller (1.2VO)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Descriptions
      2. 7.3.2 Buck Converter
        1. 7.3.2.1  PWM Operation
        2. 7.3.2.2  Voltage-Mode Control Loop
        3. 7.3.2.3  Output Voltage 5.3 V (VREG)
        4. 7.3.2.4  Switching Frequency (RT/CLK)
        5. 7.3.2.5  Boost Capacitor (BOOT)
        6. 7.3.2.6  Soft Start (SS)
        7. 7.3.2.7  Power-On Delay (DELAY)
        8. 7.3.2.8  Reset (nRST)
        9. 7.3.2.9  Thermal Shutdown
        10. 7.3.2.10 Reset Function
      3. 7.3.3 Linear Regulators
        1. 7.3.3.1 Fixed Linear Regulator Output (5.3 V)
        2. 7.3.3.2 Fixed Linear Regulator Controller (3.3 V)
        3. 7.3.3.3 Fixed Linear Regulator Controller (1.2 V)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operational Mode
      2. 7.4.2 Buck Converter Modes of Operation
        1. 7.4.2.1 Continuous-Conduction Mode (CCM)
        2. 7.4.2.2 Discontinuous Mode (DCM)
        3. 7.4.2.3 Tracking Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Duty Cycle
        2. 8.2.2.2 Output Inductor Selection (L)
        3. 8.2.2.3 Output Capacitor Selection (CO)
        4. 8.2.2.4 External Schottky Diode (D)
        5. 8.2.2.5 Input Capacitor (CI)
        6. 8.2.2.6 Loop Compensation
        7. 8.2.2.7 Loop-Control Frequency Compensation
          1. 8.2.2.7.1 Type III Compensation
          2. 8.2.2.7.2 PWM Modulator Gain K
          3. 8.2.2.7.3 Resistor Values
          4. 8.2.2.7.4 Gain of Amplifier
          5. 8.2.2.7.5 Poles and Zero Frequencies
        8. 8.2.2.8 Power Dissipation
          1. 8.2.2.8.1 Switch-Mode Power-Supply Losses
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Inductor L
      2. 10.1.2 Input Filter Capacitors CI
      3. 10.1.3 Feedback
      4. 10.1.4 Traces and Ground Plane
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resource
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Detailed Description

7.1 Overview

The device integrates an asynchronous switch-mode power-supply converter with a internal FET that converts the input battery voltage to a 5.3-V pre-regulator output. This 5.3-V output supplies the other regulators. The frequency range is from 2 MHz to 3 MHz, allowing the use of low-profile inductors and low value input and output capacitors. External loop compensation provides flexibility which optimizes the converter response for the appropriate operating condition.

A fixed 5-V linear regulator with an internal FET is integrated as an external peripheral supply. A fixed 3.3-V linear regulator controller with external bi-polar transistor is used for an IO supply, for example. A fixed 1.234-V linear regulator controller with external bi-polar transistor is used for a CPU Core supply, for example. The device has a voltage supervisor which monitors the output of the switch-mode power supply, the 3.3-V linear regulator, and the 1.234-V linear regulator.

An external timing capacitor sets the power-on delay and the release of the reset output nRST. This reset output is also used to indicate if the switch-mode supply, the 3.3-V linear regulator supply, or the 1.234-V linear regulator supply is outside the set limits. The 5-V regulator tracks the 3.3-V linear regulator within the specified limits.

7.2 Functional Block Diagram

TPS65300-Q1 FBD_SLVSBB6.gifFigure 11. Internal Functional Blocks

7.3 Feature Description

7.3.1 Detailed Pin Descriptions

    Buck Supply, VIN_D The buck supply is an input power source for the internal high-side MOSFET of the switch-mode power supply.
    Phase Node for Buck Regulator, PH This pin provides the floating voltage reference for the internal drive circuitry.
    Bootstrap, BOOT The ceramic capacitor on this pin acts a as a voltage supply for the internal high-side MOSFET gate-drive circuitry. The capacitor connects between the BOOT and PH pins. Operating with a duty cycle of 100% automatically reduces the duty cycle to approximately 95% on every fifth cycle to allow this capacitor to recharge.
    Voltage-Sense Node, VSENSE An internal resistor between VREG and this pin and another internal resistor between this pin and ground form the voltage-sense network. This pin is the inverting input for the error amplifier of the control loop. This input is compared to an internal reference of 2 V for the control circuitry.
    Error Amplifier Output, COMP The error amplifier output forms a compensation network for the voltage mode control topology. The amplifier changes state with increase in voltage output on this pin.
    Internal Regulated Boot Supply, BOOT_LDO The internally regulated supply acts as a refresh power source for the bootstrap capacitor every switching cycle. An external capacitor to ground is needed to stabilize the voltage source.
    Clock Pulse, RT/CLK A resistor to ground on this pin sets the buck converter switching frequency. Alternatively, an external clock input on this pin overrides the internal free-running clock (default value) by detecting positive edges of consecutive pulses and synchronizing to the external input signal. If the external clock input is removed, the system synchronizes to the internal clock signal of 2.2 MHz.
    Output Voltage, VREG This pin represents the buck (step-down) output voltage VREG of the converter. The output voltage of the buck-mode regulator is fixed at 5.3 V. This output requires a ceramic capacitor (4.7 µF to 10 µF range).
    Ignition Enable Input, IGN_EN The IGN_EN pin acts as an enable/disable input to activate the step-down power-supply output. The input is high-voltage tolerant up to 45 V. An internal resistor limits current into this pin for such high input voltage.
    Logic Level Enable Input, EN The EN pin is a logic-level disable input to all outputs when IGN_EN is low and all outputs are active.
    Regulated Output, 5V This pin is the regulated output and requires a low-ESR ceramic capacitor to ground for loop stabilization. This capacitor must be placed close to the pin of the IC. The output requires larger capacitance to compensate for wide load transient steps.
    Power-On Delay, DELAY A capacitor on this pin sets the desired delay time. The output of this pin provides a source current to charge the external capacitor once the VREG, 3.3 V and 1.234 V supplies have all exceeded the internally set threshold (0.9 × their respective regulated supply values).
    3.3-V Drive Output, 3.3VDRIVE This pin provides an output to drive an external bipolar transistor (BJT) for the 3.3 V supply. The output is protected by current limiting of both the source and sink capabilities.
    3.3-V Voltage Sense, 3.3VSENSE This pin is the voltage node of 3.3 V supply. Voltage of approximately 1.65 V on this pin initiates a current foldback during shorts on the regulated output.
    1.2-V Drive Output, 1.2VDRIVE This pin provides an output to drive an external bipolar transistor (BJT) for the 1.234 V supply. The output is protected by current limiting of both the source and sink capabilities.
    1.2-V Voltage Sense, 1.2VSENSE This pin is the voltage node of 1.234 V supply. Voltage of approximately 0.6 V on this pin initiates a current foldback during shorts on the regulated output.
    Soft Start, SS A ceramic capacitor is connected from this pin to ground to set a soft-start timer for the buck regulator supply. There is an internal pullup current source of 50 µA typical, which is activated on IGN_EN to charge the external capacitor on the SS pin.
    Input Voltage, VIN The VIN pin is the input power source for the device. This pin must be externally protected against voltage levels greater than 45 V and against a reversed battery. This input line requires a filter capacitor to minimize noise. Additionally, for EMI considerations, an input filter inductor may also be required.
    Reset Indicator, nRST The nRST pin is an open-drain output. The power-on reset output is asserted low until the output voltages on the VREG, 3.3 V, and 1.234 V supplies exceed their set thresholds and the power-on delay timer has expired. Additionally, whenever the IGN_EN and EN_LIN_REG pins are low or open, nRST is immediately asserted low regardless of the output voltage. If a thermal shutdown occurs due to excessive thermal, conditions this pin is asserted low.
    Ignition Input Status, IGN_ST The IGN_ST pin is an open-drain output. This output indicates whether input signal IGN_EN is present. Additionally, whenever the IGN pin is low or open, IGN_ST is immediately asserted low.
    Power Ground, PGND Power ground pin, which is internally connected to the exposed thermal pad.
    Ground, GND Signal ground pin, which is internally connected to the exposed thermal pad.

7.3.2 Buck Converter

7.3.2.1 PWM Operation

The switch-mode power supply (SMPS) operates in a fixed-frequency adaptive on-time control pulse-width modulation (PWM). The switching frequency is set by an external resistor or synchronized with an external clock input. The internal N-channel MOSFET is turned on (SET) at the beginning of each cycle. This MOSFET is turned off (RESET) when the PWM comparator resets the latch. When the high external FET is turned OFF, the external Schottky diode recirculates the energy stored in the inductor for the remainder of the switching period.

The external bootstrap capacitor acts as a voltage supply for the internal high side MOSFET. This capacitor is recharged on every recirculation cycle (when the internal high-side MOSFET is turned OFF). In the case of commanding 100% duty cycle for the internal high side MOSFET, the device automatically reverts to 87% to allow the bootstrap capacitor to recharge.

7.3.2.2 Voltage-Mode Control Loop

The voltage-mode control monitors the set output voltage and processes the signal to control the internal MOSFET. A voltage feedback signal is compared to a constant ramp waveform, resulting in a PWM modulation pulse. An input line-voltage feedforward technique is incorporated to compensate for changes in the input voltage and ensures the output voltage is stable by adjusting the ramp waveform for the correct duty cycle. The internal MOSFET is protected from excess power dissipation with a current-limit and frequency foldback circuitry during an output-to-ground short-circuit event.

A combination of internal and external components forms a compensation network to ensure error-amplifier gain does not cause instability because of input voltage changes or load perturbations.

7.3.2.3 Output Voltage 5.3 V (VREG)

The output voltage VREG is generated by the converter supplied from the battery voltage VIN and the external components (L, C). The output is sensed through an internal resistor divider and compared with an internal reference voltage.

This output requires larger output capacitors (4.7-µF to 10-µF range) to ensure that during load transients the output does not drop below the reset threshold for a period longer than the reset deglitch filter time.

An internal load is enabled for a short period when the following occurs:

  • A start-up condition occurs, that is, during power up or when IGN_EN or EN is toggled.
  • An overvoltage condition exists on this output.

7.3.2.4 Switching Frequency (RT/CLK)

The oscillator frequency of the buck regulator is selectable by means of a resistor placed at the RT/CLK pin to ground. The switching frequency (fSW) can be set in the range 2 MHz to 3 MHz in this resistor mode. Alternatively, if there is an external clock input signal, the internal oscillator synchronizes to this signal within 10 µs.

The Equation 1 calculates the value of resistor (RT) for the required switching frequency fSW.

Equation 1. TPS65300-Q1 Eq04-RT_SLVSBB6.gif

7.3.2.5 Boost Capacitor (BOOT)

This capacitor provides the gate-drive voltage for the internal MOSFET switch. X7R and X5R grade dielectrics are recommended because of their stable values over temperature. Selecting a lower value of boost capacitor for low-Vreg, high-frequency, or both types of applications, or selecting a higher value for high-Vreg, low-frequency, or both types of applications (for example, 100 nF for 500 kHz/5 V and 220 nF for 500 kHz/8 V) may be necessary. In general, a 0.1-µF capacitor is used for the boot capacitor.

7.3.2.6 Soft Start (SS)

To limit the start-up inrush current for the switch-mode supply, an internal soft-start circuit is used to ramp up the reference voltage from 0 V to the final value of 0.8 V. The regulator uses the internal reference or the SS-pin voltage as the power-supply reference voltage to regulate the output accordingly. Use Equation 2 to calculate the soft-start timing.

Equation 2. TPS65300-Q1 Eq05-Time_SLVSBB6.gif

where

  • C = Capacitor on the SS pin, typically 0.1 µF or lower

7.3.2.7 Power-On Delay (DELAY)

The power-on delay function delays the release of the nRST line. The method of operation is to detect when all VREG (5.3-V), 3.3-V, and 1.234-V power-supply outputs are above 90% (typical) of the set value. This detection then triggers a current source to charge the external capacitor on the DELAY pin. When this capacitor is charged to approximately 2 V, the nRST line is asserted high. The delay time is calculated using Equation 3.

Equation 3. TPS65300-Q1 Eq06-tDELAY_SLVSBB6.gif

where

  • C = capacitor on DELAY pin.

7.3.2.8 Reset (nRST)

The nRST pin is an open-drain output. The power-on reset signal is a voltage-supervisor output to indicate the output voltages on VREG (5.3 V), 3.3 V, and 1.234 V are within the specified tolerance of the set regulated voltages. Additionally, whenever both the IGN_EN and EN pins are low or open, the nRST pin is immediately asserted low regardless of the output voltage. If a thermal shutdown occurs because of excessive thermal conditions, this pin is asserted low.

Conversely on power down, when the VREG or 3.3-V or 1.234-V output voltage falls below 90% of the respective set threshold, the nRST pin is pulled low after a de-glitch filter delay of approximately 15 µs (maximum). This feature is implemented to prevent nRST from being invoked because of noise on the output supplies.

7.3.2.9 Thermal Shutdown

This device has independent two thermal sensing circuits for the VREG (5.3 V), 5-V regulators; if either one of these circuits detects the power FET junction temperature to be greater than the set threshold, that particular output-power switch is turned OFF. The appropriate FET turns back ON once it is allowed to cool sufficiently. The thermal sensing and shutdown circuitry is only activated when nRST is high.

7.3.2.10 Reset Function

TPS65300-Q1 Reset-func_SLVSBB6.gifFigure 12. Reset Function

7.3.3 Linear Regulators

7.3.3.1 Fixed Linear Regulator Output (5.3 V)

This linear regulator is a fixed, regulated output of 5.3 V ±2% over temperature and input supply using a precision voltage-sense resistor network. A low-ESR ceramic capacitor is required for loop stabilization; this capacitor must be placed close to the pin of the IC. This output is protected against shorts to ground by a foldback current limit for safe operating conditions, and a current-limit for limiting inrush current because of depleted charge on the output capacitor. Initial IGN_EN or EN initiates power cycle of the soft-start circuit on this regulator. This typically is in the 1-ms to 2-ms range. This output may require a larger output capacitor to ensure that during load transients the output does not drop below the required regulated specifications.

7.3.3.2 Fixed Linear Regulator Controller (3.3 V)

The linear regulator controller requires an external NPN bipolar pass transistor of sufficient gain stage to support the maximum load current required. The base-drive output current is protected by current limiting both the source and sink drive circuitry. The 3.3VSENSE pin is the remote sense input of the output of the REG3 supply and controls the 3.3VDRIVE output accordingly. This regulator is a fixed 3.3-V with ±2% tolerance using a precision voltage-sense resistor network. A low-ESR ceramic output capacitor is used for loop compensation of the regulator. A voltage on this pin of less than approximately 50% of the regulated value initiates a current limit on the 3.3VDRIVE output.

This output may require larger output capacitors to support load transients, so the output does not drop below 90% of 3.3 V.

7.3.3.3 Fixed Linear Regulator Controller (1.2 V)

The linear regulator controller requires an external NPN bipolar pass transistor of sufficient gain stage to support the maximum load current required. The 1.2VSENSE pin is the remote sense input of the output of 1.234-V supply and controls the 1.2VDRIVE output accordingly. This regulator output is 1.234 V with ±2% tolerance using a precision voltage-sense resistor network. A low-ESR ceramic output capacitor is used for loop compensation of the regulator. A voltage on this pin of less than approximately 50% of the regulated value initiates a current limit on the 1.2VDRIVE output.

This output may require larger output capacitors to support load transients, so the output does not drop below 90% of 1.234 V.

7.4 Device Functional Modes

7.4.1 Operational Mode

The purpose of the EN input is to keep the regulated supplies ON for a period for the microprocessor to log information into the memory locations when the ignition input is disabled. The microprocessor disables the power supplies by pulling EN low after this activity is complete.

7.4.2 Buck Converter Modes of Operation

The converter operates in different modes based on load current, input voltage, and component selection.

7.4.2.1 Continuous-Conduction Mode (CCM)

This mode of operation is typically when the inductor current is non-zero and the load current is greater than IL CCM.

Equation 4. TPS65300-Q1 Eq01-Iindccm_SLVSBB6.gif

where

  • IIND_CCM = Inductor current in continuous-conduction mode
  • D = duty cycle
  • VREG = output voltage
  • L = Inductor
  • fSW = switching frequency

In this mode, the duty cycle must always be greater than the minimum tON or the converter may go into burst mode.

7.4.2.2 Discontinuous Mode (DCM)

Equation 5. TPS65300-Q1 Eq02-Iinddcm_SLVSBB6.gif

This mode of operation is typically when the inductor current goes to zero and the load current is less than IIND DCM.

7.4.2.3 Tracking Mode

When the input voltage is low and the converter approaches approximately 100% duty cycle, Equation 6 calculates the output voltage.

Equation 6. TPS65300-Q1 Eq03-VREG_SLVSBB6.gif

where

  • T = Period
  • RDS = Internal FET resistance
  • ILOAD = output load current