JAJSDI8B October   2015  – June 2017 TPS65321-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Buck Regulator
        1. 7.3.1.1  Fixed-Frequency PWM Control
        2. 7.3.1.2  Slope Compensation Output
        3. 7.3.1.3  Pulse-Skip Eco-mode™ Control Scheme
        4. 7.3.1.4  Dropout Mode Operation and Bootstrap Voltage (BOOT)
        5. 7.3.1.5  Error Amplifier
        6. 7.3.1.6  Voltage Reference
        7. 7.3.1.7  Adjusting the Output Voltage
        8. 7.3.1.8  Soft-Start Pin (SS)
        9. 7.3.1.9  Reset Output, nRST
        10. 7.3.1.10 Overload-Recovery Circuit
        11. 7.3.1.11 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
        12. 7.3.1.12 Overcurrent Protection and Frequency Shift
        13. 7.3.1.13 Selecting the Switching Frequency
        14. 7.3.1.14 How to Interface to RT/CLK Pin
        15. 7.3.1.15 Overvoltage Transient Protection
        16. 7.3.1.16 Small-Signal Model for Loop Response
        17. 7.3.1.17 Simple Small-Signal Model for Peak-Current Mode Control
        18. 7.3.1.18 Small-Signal Model for Frequency Compensation
      2. 7.3.2 LDO Regulator
        1. 7.3.2.1 Charge-Pump Operation
        2. 7.3.2.2 Low-Voltage Tracking
        3. 7.3.2.3 Adjusting the Output Voltage
      3. 7.3.3 Thermal Shutdown
      4. 7.3.4 Enable and Undervoltage Lockout
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Soft-Start Discharge
      2. 8.1.2 Passive Discharge Through a Resistor in Parallel With the SS Capacitor
      3. 8.1.3 Active Discharge Through A NPN Transistor
    2. 8.2 Typical Application
      1. 8.2.1 2.2-MHzSwitching Frequency, 9-V to 16-V Input, 3.3-V Output Buck Regulator, 5-V Output LDO Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Switching Frequency Selection for the Buck Regulator
          2. 8.2.1.2.2  Output Inductor Selection for the Buck Regulator
          3. 8.2.1.2.3  Output Capacitor Selection for the Buck Regulator
          4. 8.2.1.2.4  Catch Diode Selection for the Buck Regulator
          5. 8.2.1.2.5  Input Capacitor Selection for the Buck Regulator
          6. 8.2.1.2.6  Soft-Start Capacitor Selection for the Buck Regulator
          7. 8.2.1.2.7  Bootstrap Capacitor Selection for the Buck Regulator
          8. 8.2.1.2.8  Output Voltage and Feedback Resistor Selection for the Buck Regulator
          9. 8.2.1.2.9  Frequency Compensation Selection for the Buck Regulator
          10. 8.2.1.2.10 LDO Regulator
          11. 8.2.1.2.11 Power Dissipation
            1. 8.2.1.2.11.1 Power Dissipation Losses of the Buck Regulator
          12. 8.2.1.2.12 Power Dissipation Losses of the LDO Regulator
          13. 8.2.1.2.13 Total Device Power Dissipation Losses and Junction Temperature
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design Example With 500-kHz Switching Frequency
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Selecting the Switching Frequency
          2. 8.2.2.2.2 Output Inductor Selection
          3. 8.2.2.2.3 Output Capacitor
          4. 8.2.2.2.4 Compensation
        3. 8.2.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PWP|14
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

TI recommends the guidelines that follow for PCB layout of the TPS65321-Q1 device.

  • Inductor

    • Use a low-EMI inductor with a ferrite-type shielded core. Other types of inductors can also be used, however, these inductors must have low-EMI characteristics and be located away from the low-power traces and components in the circuit.

  • Input Filter Capacitors

    • Locate input ceramic filter capacitors close to the VIN pin. TI recommends surface-mount capacitors to minimize lead length and reduce noise coupling.

  • Feedback

    • Route the feedback trace for minimum interaction with any noise sources associated with the switching components. TI recommends to place the inductor away from the feedback trace to prevent creating an EMI noise source.

  • Traces and Ground Plane

    • All power (high-current) traces must be as thick and short as possible. The inductor and output capacitors must be as close to each other as possible to reduce EMI radiated by the power traces because of high switching currents. In a two-sided PCB, TI recommends using ground planes on both sides of the PCB to help reduce noise and ground loop errors. The ground connection for the input capacitors, output capacitors, and device ground should connect to this ground plane, where the connection between input capacitors and the catch-diode is the most critical. In a multi-layer PCB, the ground plane separates the power plane (where high switching currents and components are) from the signal plane (where the feedback trace and components are) for improved performance. Also, arrange the components such that the switching-current loops curl in the same direction. Place the high-current components such that during conduction the current path is in the same direction. This placement prevents magnetic field reversal caused by the traces between the two half-cycles, and helps reduce radiated EMI.

10.2 Layout Example

TPS65321-Q1 layout_slvscf0.gif Figure 29. TPS65321-Q1 Layout Example
TPS65321-Q1 layout_front_slvscf0_tps65321.gif Figure 30. TPS65321-Q1 Layout Example
Top Side
TPS65321-Q1 layout_back_slvscf0.gif Figure 31. TPS65321-Q1 Layout Example
Bottom Side