The TPS65381-Q1 device is a multirail power supply designed to supply microcontrollers (MCUs) in safety-relevant applications, such as those found in automotive and industrial markets. The device supports Texas Instruments’ Hercules™ TMS570 MCU and C2000™ MCU families, and various other MCUs with dual-core lockstep (LS) or loosely-coupled architectures (LC).
The TPS65381-Q1 device integrates multiple supply rails to power the MCU, controller area network (CAN), or FlexRay, and an external sensor. An asynchronous-buck switch-mode power-supply converter with an internal FET converts the input supply (battery) voltage to a 6-V preregulator output. This 6-V preregulator supplies the other regulators. The device supports wakeup from IGNITION or wakeup from the CAN transceiver.
The integrated, fixed 5-V linear regulator with internal FET can be used for a CAN or FlexRay transceiver supply for example. A second linear regulator, also with an internal FET, regulates to a selectable 5-V or 3.3-V output which, for example, can be use for the MCU I/O voltage.
The TPS65381-Q1 device includes an adjustable linear-regulator controller, requiring an external FET and resistor divider, that regulates to an adjustable voltage of between 0.8 V and 3.3 V which may be used for the MCU core supply.
The integrated sensor supply can be run in tracking mode or adjustable output mode and includes short-to-ground and short-to-battery protection. Therefore, this regulator can power a sensor outside the module or electronic control unit (ECU).
The integrated charge pump provides overdrive voltage for the internal regulators. The charge pump can also be used in a reverse-battery protection circuit by using the charge-pump output to control an external NMOS transistor. This solution allows for a lower minimum-battery-voltage operation compared to a traditional reverse-battery blocking diode when the device must be operational at the lowest possible supply voltages.
The device monitors undervoltage and overvoltage on all regulator outputs, battery voltage, and internal supply rails. A second bandgap reference, independent from the main bandgap reference, is used for the undervoltage and overvoltage monitoring, to avoid any drifts in the main bandgap reference from being undetected. In addition, regulator current-limits and temperature protections are implemented.
The TPS65381-Q1 device has monitoring and protection functions, which include the following: watchdog with trigger and question and answer modes, MCU error-signal monitor, clock monitoring on internal oscillators, self-check on the clock monitor, cyclic redundancy check (CRC) on nonvolatile memory, a diagnostic output pin allowing the MCU to observe internal analog and digital signals of the device, a reset circuit and output pin for the MCU, and an enable drive output to disable the safing-path or external-power stages on detected faults. A built-in self-test (BIST) monitors the device functionality automatically at power-up. A dedicated DIAGNOSTIC state allows the MCU to check TPS65381-Q1 monitoring and protection functions.
The TPS65381-Q1 device is offered in a 32-pin HTSSOP PowerPAD package.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS65381-Q1 | HTSSOP (32) | 11.00 mm × 6.20 mm |
Changes from F Revision (May 2016) to G Revision
Changes from E Revision (July 2015) to F Revision
Changes from D Revision (May 2015) to E Revision
Changes from C Revision (March 2015) to D Revision
Changes from B Revision (July 2014) to C Revision
Changes from A Revision (December 2013) to B Revision
Changes from * Revision (May 2012) to A Revision
Changes from * Revision (July 2016) to A Revision
The pin configuration drawing in this section is not to scale. For package dimensions, see the mechanical data in Section 10.
POS | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
M1.1 | Protected-battery voltage | VBATP, VBAT_SAFING, VSIN | –0.3 | 40 | V |
M1.2 | Charge-pump voltage | VCP, CP1(3) | –0.3 | lesser of VBATP + 16 or 52 | V |
M1.3 | Charge-pump pumping capacitor voltage | CP2 | –0.3 | 40 | V |
M1.3a | Charge-pump overdrive voltage | VCP(3)-VBATP | –0.3 | 16 | V |
M1.4 | VDD6 switching-node voltage | SDN6 | –0.3 | 40 | V |
M1.5 | VDD6 output voltage | VDD6 | –0.3 | 40 | V |
M1.6 | VDD5 output voltage | VDD5 | –0.3 | 7 | V |
M1.7 | VDD3/5 output voltage | VDD3/5 | –0.3 | 7 | V |
M1.8 | VDD1_G voltage | VDD1_G | –0.3 | 15 | V |
M1.10 | VDD1_SENSE voltage | VDD1_SENSE | –0.3 | 7 | V |
M1.11 | Sensor supply tracking voltage | VTRACK1 | –0.3 | 40 | V |
M1.12 | Sensor supply output and feedback voltage | VSOUT1, VSFB1(4) | –2 | 18 | V |
M1.14 | Analog/digital reference output voltage | DIAG_OUT | –0.3 | 7 | V |
M1.15 | Logic I/O voltage | VDDIO, ERROR/WDI, ENDRV, NRES, NCS, SDI, SDO, SCLK, RSTEXT | –0.3 | 7 | V |
M1.16 | SEL_VDD3/5 | –0.3 | 40 | V | |
M1.17 | IGN wakeup | IGN | –7 | 40 | V |
M1.18 | CAN wakeup | CANWU | –0.3 | 40 | V |
M1.19 | Operating virtual junction temperature, TJ | 150 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
POS. | VALUE | UNIT | ||||
---|---|---|---|---|---|---|
M1.21 | V(ESD) | Electrostatic discharge | Human body model (HBM), per AEC Q100-002(1) | All pins except VSOUT1 (17) and VSFB1 (15) | ±2000 | V |
M1.20 | On sensor supply pins VSOUT1 (17) and VSFB1 (15) | ±4000 | ||||
M1.22 | Charged device model (CDM), per AEC Q100-011 | Corner pins (1, 16, 17, and 32) | ±750 | |||
M1.23 | All pins | ±500 |
POS | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
M1.20a | Operating ambient temperature, TA | –40 | 125 | °C | |
R1.1 | Minimum input supply voltage on VBATP for initial power up (POS 6.2, VBATP_UVon)(2)(3) | 5.8(4) | V | ||
R1.2 | Input supply voltage on VBATP (2)(3)(1)
|
5.8 | 34(6) | V | |
R1.3 | Input supply voltage on VBATP after initial power up, functional operation during low input supply voltage events, (POS 6.1, VBATP_UVoff):(2)(5)
|
4.5 | 5.8 | V | |
R1.4 | VDDIO supply-voltage range | 3.3 | 5 | V | |
R1.5 | Current consumption in standby mode (all regulator outputs disabled) IGN = 0 V, CANWU = 0 V, 5.8 V ≤ VBAT ≤ 20 V for TJ < 85°C or 5.8 V ≤ VBAT ≤ 14 V tor TJ = 125°C |
75 | µA |
THERMAL METRIC(1) | TPS65381-Q1 | UNIT | |
---|---|---|---|
DAP (HTSSOP) | |||
32 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 26.3 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 14.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 6 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 6.2 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 0.5 | °C/W |
POS | PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|---|
VDD6-BUCK WITH INTERNAL FET | ||||||||
AN | CVDD6 | Value of output ceramic capacitor(1) | ESR range 100 mΩ to 300 mΩ(2) | 22 | 47 | µF | ||
AN | LVDD6 | Value of inductor | 22 | 33 | µH | |||
1.1 | VDD6 | VDD6 output voltage | Average DC value excluding ripple and load transients, VBAT > 7 V, 0 < IVDD6 < 1.3 A, including dc line and load regulation, temperature drift, and long-term drift where VBAT = VBATP = VBAT_SAFING | 5.4 | 6 | 6.6 | V | |
1.1a | VDD6ripple | VDD6 ripple voltage | Peak-to-peak, ensured by design VBATP = VBAT_SAFING = 14 V, L = 33 µH, C = 22 µF |
200 | mV | |||
1.2 | IVDD6 | VDD6 output current IVDD5 + IVDD3/5 + IVDD1+ IVSOUT1(6) | 1.3 | A | ||||
1.3 | Vdropout6 | VDD6 output dropout voltage Vdropout6 = (VBATP – SDN6) | IVDD6 = 1.3 A (example: RDS(on) = 0.46 Ω) |
0.6 | V | |||
1.4 | IVDD6_limit | Peak current out of SDN6 pin(21) | 1.5 | 2.5 | A | |||
1.5 | ƒclk_VDD6 | Clock Frequency (5) | 396 | 440 | 484 | kHz | ||
1.6 | DCVDD6 | ton/tperiod | 0 < IVDD6 < 1.3 A VDD6 enters dropout mode (100% duty cycle) for VBATP < 7 V |
7%(22) | 100% | |||
1.7 | TprotVDD6 | Temperature protection threshold(7) | 175 | 210 | °C | |||
VDD5 – LDO WITH INTERNAL FET | ||||||||
AN | CVDD5 | Value of output ceramic capacitor | ESR range 0 mΩ to 100 mΩ | 1 | 5 | µF | ||
2.1 | VDD5 | VDD5 output voltage(8) | 0 < IVDD5 < 300 mA | 4.9 | 5 | 5.1 | V | |
2.2 | IVDD5 | VDD5 output current, including load from the internal resistor of 660 Ω (typical) | 300 | mA | ||||
2.3 | VDD5dyn | VDD5 output voltage dynamic | Load step 20% to 80% in 5 µs, with CVDD5 = 5 µF | 4.85 | 5 | 5.15 | V | |
2.4 | VDD5max | Maximum VDD5 output voltage during VBATP step from 5.5 V to 13.5 V within 10 μs | CVDD5 = 5 µF, IVDD5 < 300 mA | 5.5 | V | |||
2.5 | Vdropout5 | VDD5 output dropout voltage Vdropout5 = (VDD6 – VDD5) | IVDD5 < 300 mA | 0.3 | V | |||
2.6 | PSRRVDD5 | Power supply rejection ratio | 50 < f < 20 kHz, VBATP = 10 V, U = 4 Vpp, CVDD5 = 5 μF, 0 < IVDD5 < 300 mA |
> 40 | dB | |||
2.7 | LnRegVDD5 | Line regulation (IVDD5 constant) | 0 < IVDD5 < 300 mA, 8 V < VBATP < 19 V |
–25 | 25 | mV | ||
2.8 | LdRegVDD5 | Load regulation (VDD6 constant) | 0 < IVDD5 < 300 mA, 8 V < VBATP < 19 V |
–25 | 25 | mV | ||
2.9 | TmpCoVDD5 | Temperature drift | Normalized to 25°C value | –0.5% | 0.5% | |||
2.11 | dVDD5/dt | dV/dt at VDD5 at startup | Between 10% and 90% of VDD5 end-value | 5 | 50 | V/ms | ||
2.13 | TprotVDD5 | Temperature protection threshold(9) | 175 | 210 | °C | |||
2.14 | IVDD5_limit | Current-limit(26) | 350 | 650 | mA | |||
VDD3/5 – LDO WITH INTERNAL FET | ||||||||
AN | CVDD3/5 | Value of output ceramic capacitor | ESR range 0 mΩ to 100 mΩ | 1 | 5 | µF | ||
3.1a | VDD3/5 | VDD3/5 output voltage, SEL_VDD3/5 pin: open = 3.3 V setting, ground = 5 V setting | 0 < IVDD3/5 < 300 mA | 3.3-V Setting | 3.234 | 3.3 | 3.366 | V |
3.1b | 5-V Setting | 4.9 | 5 | 5.1 | ||||
3.2 | IVDD3/5 | VDD3/5 output current, including load from the internal resistor of 440 Ω (typ.) for 3.3 V setting or 660 Ω (typ.) for 5 V setting(23) | 300 | mA | ||||
3.3a | VDD3/5dyn | VDD3/5 output voltage dynamic | Load step 20% to 80% in 5 µs, with CVDD3/5 = 5 µF |
3.3-V Setting | 3.15 | 3.3 | 3.43 | V |
3.3b | 5-V Setting | 4.85 | 5 | 5.15 | ||||
3.4 | VDD3/5max | Maximum VDD3/5 output voltage during VBATP step from 5.5 V to 13.5 V within 10 μs | CVDD3/5 = 5 µF, IVDD3/5 < 300 mA | 3.3-V Setting | 3.6 | V | ||
5-V Setting | 5.5 | |||||||
3.5 | Vdropout3/5 | VDD3/5 output dropout voltage Vdropout3/5 = (VDD6–VDD3/5) | IVDD3/5 < 300 mA | 0.3 | V | |||
3.6 | PSRRVDD3/5 | Power-supply rejection ratio | 50 < f < 20 kHz, VBATP = 10 V, U = 4 Vpp CVDD3/5 = 5 μF, 0 < IVDD3/5 < 300 mA |
> 40 | dB | |||
3.7 | LnRegVDD3/5 | Line regulation (IVDD3 constant) | 0 < IVDD3/5 < 300 mA, 8 V < VBATP < 19 V |
–25 | 25 | mV | ||
3.8 | LdRegVDD3/5 | Load regulation (VDD6 constant) | 0 < IVDD3/5 < 300 mA 8 V < VBATP < 19 V |
–25 | 25 | mV | ||
3.9 | TmpCoVDD3/5 | Temperature drift | Normalized to 25°C value | –0.5% | 0.5% | |||
3.11 | dVDD35/dt | dV/dt at VDD3/5 at start-up | Between 10% and 90% of VDD3/5 end-value | 3.3-V Setting | 3 | 30 | V/ms | |
5-V Setting | 5 | 50 | ||||||
3.13 | TprotVDD3/5 | Temperature protection threshold(10) | 175 | 210 | °C | |||
3.14 | IVDD3/5_limit | Current-limit(27) | 350 | 650 | mA | |||
3.15 | Ipu_SEL_VDD3/5 | Pullup current on SEL_VDD3/5 pin | 20 | µA | ||||
VDD1 – LDO WITH EXTERNAL FET | ||||||||
AN | Vgs(th) | Gate threshold voltage, external FET | ID = 1 mA | 0.3 | 3 | V | ||
AN | Ciss | Gate capacitance, external FET | VGS = 0 V | 3200 | pF | |||
AN | Qgate | Gate Charge, external FET | VGS = 0 V to 10 V | 70 | nC | |||
AN | gfs | Forward transconductance, external FET | ID = 50 mA | 0.4 | S | |||
AN | CVDD1 | Value of output ceramic capacitor | ESR range 0 mΩ to 100 mΩ | 5 | 40 | µF | ||
4.1 | VDD1 | VDD1 output voltage, depends on external resistive divider | 0.8 | 3.3 | V | |||
4.2 | VDD1SENSE | VDD1 reference voltage(11) | 10 mA < IVDD1 < 600 mA | 0.792 | 0.8 | 0.808 | V | |
4.2a | VDD1SENSE_BIAS | Bias current of VDD1SENSE | –6.6 | –10 | µA | |||
4.3 | IVDD1 | VDD1 output current | Minimum current realized with external resistive divider | 10 | 600 | mA | ||
4.4 | VDD1G | VDD1_G output voltage | Referenced to GND | 15 | V | |||
4.5 | VDD1G_off | VDD1_G voltage in OFF condition | 20 µA into VDD1_G pin | 0.3 | V | |||
4.6 | I_VDD1G | VDD1_G DC load current | 200 | µA | ||||
4.7 | VDD1dyn | VDD1 output voltage dynamic | Load step 10% to 90% in 1 μs, with CVDD1 = 40 μF(24) | ± 4% | ||||
4.8 | VDD1max | Maximum VDD1 output voltage during VBATP step from 5.5 V to 13.5 V within 10 μs | CVDD1 > 6 µF, IVDD1< 600 mA | VDD1 = 0.8-V output | 0.898 | V | ||
VDD1 = 1.23-V output | 1.287 | |||||||
VDD1 = 3.3-V output | 3.435 | |||||||
4.9 | PSRRVDD1 | Power-supply rejection ratio | 50 < f < 20 kHz, VBATP = 10 V, U = 4 Vpp, CVDD1 = 10 μF, 10 mA < IVDD1 < 600 mA |
> 40 | dB | |||
4.10 | LnRegVDD1 | Line regulation on VDD1_SENSE (IVDD1 constant) | 10 mA < IVDD1< 600 mA, 8 V < VBATP < 19 V | –7 | 7 | mV | ||
4.11 | LdRegVDD1 | Load regulation on VDD1_SENSE (VDD6 constant) | 10 mA < IVDD1 < 600 mA, 8 V < VBATP < 19 V | –7 | 7 | mV | ||
4.12 | TmpCoVDD1 | Temperature drift | Normalized to 25°C value | –0.5% | 0.5% | |||
4.14 | dVDD1/dt | dV/dt at VDD1_SENSE at start-up | Between 10% and 90% of VDD1 end-value | 0.8 | 8 | V/ms | ||
VSOUT1 – LDO WITH PROTECTED INTERNAL FET | ||||||||
AN | CVSOUT1 | Value of output ceramic capacitor | ESR range 0 mΩ to 100 mΩ | 0.5 | 10 | µF | ||
5.1 | VSOUT1 | VSOUT1 output voltage, depends on external resistive divider and tracking or non-tracking mode | 3.3 | 9.5 | V | |||
5.2 | MVVSOUT1 | For tracking mode: Matching output error MVVSOUT1 = (VTRACK1 – VSFB1)(12) |
0 < IVSOUT1 < 100 mA | –35 | 35 | mV | ||
5.3 | VSFB1 | For non-tracking mode: VSOUT1 reference voltage(13) | 10 mA < IVSOUT1 < 100 mA | 2.45 | 2.5 | 2.55 | V | |
5.3a | VTRACK1th | Threshold for selecting tracking/non-tracking mode (VTRACK1 > VTRACK1th_max V for tracking mode, VTRACK1 < VTRACK1th_min V non-tracking mode) |
|
1.1 | 1.2 | 1.3 | V | |
5.3b | VTRACK1pd | Internal pulldown resistance on VTRACK1 pin | 100 | kΩ | ||||
5.4 | IVSOUT1 | VSOUT1 output current, including internal resistor to dissipate minimum current(25) | 100 | mA | ||||
5.5 | VdrS1 | VSOUT1 dropout voltage VdrS1 = (VSIN-VSOUT1) | 0 < IVSOUT1 < 100 mA | 0.75 | V | |||
5.6 | PSRRVSOUT1 | Power-supply rejection ratio | With VTRACK1 = GND, VSOUT1 = 4.5V, 50 < f < 20 kHz, VSIN = 10 V, U = 4 Vpp CVSOUT1 = 1 μF, 0 < IVSOUT1 < 100 mA, |
> 40 | dB | |||
5.7 | LnRegVSOUT1 | Line regulation (IVSOUT1 constant) | 0 < IVSOUT1 < 100 mA, 8 V < VSIN < 19 V | –25 | 25 | mV | ||
5.8 | LdRegVSOUT1 | Load regulation (VSIN constant) | 0 < IVSOUT1 < 100 mA, 8 V < VSIN < 19 V | –35 | 35 | mV | ||
5.9 | TmpCoVSOUT1 | Temperature drift | Normalized to 25°C value | –0.5% | 0.5% | |||
5.11 | VSOUT1SH | Output short circuit voltage range | VSOUT1 (VSFB1 configured for regulation)(28) | –2 | 18 | V | ||
5.12 | –IVSIN | Output reverse current | VSOUT1 = 14 V and VBATP = 0 V, regulator switched off | 20 | mA | |||
5.13 | TprotVSOUT1 | Temperature protection threshold(14) | 175 | 210 | °C | |||
5.14 | IVSOUT1_limit | Current-limit | 120 | 500 | mA | |||
VOLTAGE MONITORING | ||||||||
6.1 | VBATP_UVoff | VBATP and VBAT_SAFING level for indication by VBAT_UV comparitor(15) | VBATP = VBAT_SAFING | 4.2 | 4.5 | V | ||
6.2 | VBATP_UVon | VBATP and VBAT_SAFING level for indication by VBAT_UV comparitor(15) | VBATP = VBAT_SAFING | 5.4 | 5.8 | V | ||
6.3 | VBATP_UVhys | Undervoltage hysteresis | VBATP = VBAT_SAFING | 1.1 | 1.4 | V | ||
6.4 | VBATP_OVrise | VBATP level for setting VBAT_OV flag(16) | VBATP = VBAT_SAFING | 34.7 | 36.7 | V | ||
6.5 | VBATP_OVfall | VBATP level for clearing VBAT_OV flag(17) | VBATP = VBAT_SAFING | 34.4 | 36.3 | V | ||
6.8 | VDD5_UV | VDD5 undervoltage level | VBATP = VBAT_SAFING | 4.5 | 4.85 | V | ||
6.8a | Hysteresis | VBATP = VBAT_SAFING | 140 | mV | ||||
6.9 | VDD5_UVhead | VDD5 undervoltage headroom (VDD5act – VDD5_UVact) | VBATP = VBAT_SAFING | 200 | mV | |||
6.10 | VDD5_OV | VDD5 overvoltage level | VBATP = VBAT_SAFING | 5.2 | 5.45 | V | ||
6.10a | Hysteresis | VBATP = VBAT_SAFING | 140 | mV | ||||
6.11 | VDD5_OVhead | VDD5 overvoltage headroom (VDD5_OVact – VDD5act) | VBATP = VBAT_SAFING | 200 | mV | |||
6.12 | VDD3/5_UV | VDD3/5 undervoltage level | VBATP = VBAT_SAFING | 3.3-V setting | 3 | 3.17 | V | |
5-V setting | 4.5 | 4.85 | ||||||
6.12a | Hysteresis | VBATP = VBAT_SAFING | 3.3-V setting | 100 | mV | |||
5-V setting | 140 | |||||||
6.13 | VDD3/5_UVhead | VDD3/5 undervoltage headroom (VDD3/5act – VDD3/5_UVact) |
VBATP = VBAT_SAFING | 3.3-V setting | 155 | mV | ||
5-V setting | 200 | |||||||
6.14 | VDD3/5_OV | VDD5_3 overvoltage level | VBATP = VBAT_SAFING | 3.3-V setting | 3.43 | 3.6 | V | |
5-V setting | 5.2 | 5.5 | ||||||
Hysteresis | VBATP = VBAT_SAFING | 3.3-V setting | 100 | mV | ||||
6.14a | 5-V setting | 140 | ||||||
6.15 | VDD3/5_UVhead | VDD3/5 undervoltage headroom (VDD3/5_OVact – VDD3/5act) |
VBATP = VBAT_SAFING | 3.3-V setting | 170 | mV | ||
5-V setting | 200 | |||||||
6.16 | VDD1_UV | VDD1 undervoltage level | VBATP = VBAT_SAFING. Sensed on VDD1_SENSE pin. Relative thresholds are with respect to nominal 800-mV VDD1SENSE (Pos 4.2) | 752 | 784 | mV | ||
6.16a | Hysteresis | VBATP = VBAT_SAFING. Sensed on VDD1_SENSE pin. Relative thresholds are with respect to nominal 800-mV VDD1SENSE (Pos 4.2) | 10 | mV | ||||
6.17 | VDD1_OV | VDD1 overvoltage level | VBATP = VBAT_SAFING. Sensed on VDD1_SENSE pin. Relative thresholds are with respect to nominal 800-mV VDD1SENSE (Pos 4.2) | 816 | 848 | mV | ||
6.17a | Hysteresis | VBATP = VBAT_SAFING. Sensed on VDD1_SENSE pin. Relative thresholds are with respect to nominal 800-mV VDD1SENSE (Pos 4.2) | 9 | mV | ||||
6.19 | VSOUT1_UV | VSOUT1 undervoltage level | Sensed on VSFB1 pin. Relative thresholds (ratio) are:
|
0.88 | 0.94 | VSOUT1 | ||
6.20 | VSOUT1_OV | VSOUT1 overvoltage level | Sensed on VSFB1 pin. Relative thresholds (ratio) are:
|
1.06 | 1.12 | VSOUT1 | ||
6.22 | VDD6_UV | VDD6 undervoltage level(18) | 5.2 | 5.4 | V | |||
6.22a | Hysteresis | 115 | mV | |||||
6.23 | VDD6_OV | VDD6 overvoltage level(18) | 7.8 | 8.2 | V | |||
6.23a | Hysteresis | 115 | mV | |||||
IGNITION AND CAN WAKE-UP | ||||||||
7.1 | IGN_WUP | IGN wake-up threshold(19) | VBATP = VBAT_SAFING =12 V | 2 | 3 | V | ||
7.2 | CAN_WUP | CAN wake-up threshold(19) | VBATP = VBAT_SAFING =12 V | 2 | 3 | V | ||
7.3 | WUP_hyst | Wake-up hysteresis | VBATP = VBAT_SAFING =12 V | 50 | 200 | mV | ||
7.4 | I_IGN | IGN pin forward leakage current | IGN pin at 36 V, VBATP = VBAT_SAFING = 12V | 50 | µA | |||
7.5 | I_IGN_rev | IGN reverse current | IGN at –7 V, VBATP = VBAT_SAFING =12 V | –1 | mA | |||
7.7 | I_CANWU | CANWU pin forward leakage current | CANWU pin at 36 V, VBATP = VBAT_SAFING = 12V | 50 | µA | |||
7.8 | I_CAN_rev | CANWU reverse current | CANWU at –0.3 V, VBATP = VBAT_SAFING =12 V | mA | ||||
CHARGE PUMP | ||||||||
AN | Cpump | Pumping capacitor (between CP1 and CP2) | 10 | nF | ||||
AN | Cstore | Storage capacitor (between VCP and VBATP) | 100 | nF | ||||
8.1 | VCPon | VCP output voltage in on-state | VBATP > 5.8 V | VBATP + 4 | VBATP + 15 | V | ||
8.2 | ICP | External load | Load coming from RGS of Reverse Battery Protection | 100 | µA | |||
8.3 | fCP | Charge-pump switching frequency | 225 | 250 | 275 | kHz | ||
RESET AND ENABLE OUTPUTS | ||||||||
9.1 | VNRES_ENDRV_L | NRES / ENDRV low-output level | With external 2-mA open-drain current | 0.2 | V | |||
9.2 | RNRES_ENDRV_PULLUP | NRES / ENDRV internal pullup resistance | 3 | 6 | kΩ | |||
9.2a | RDS(on)_ENDRV_NRES | RDS(on) NRES/ENDRV pulldown transistor | 40 | Ω | ||||
9.3 | RRSTEXT | Value of external reset extension resistor, in case of open-connect, device stays in RESET state(20) | 0 | 22 | kΩ | |||
9.5 | VENDRV_NRES_TH | ENDRV and NRES input readback logic 1 threshold | Read-back muxed to DIAG_OUT pin | 350 | 400 | 450 | mV | |
DIGITAL INPUT / OUTPUT | ||||||||
10.1 | VDIGIN_HIGH | Digital input, high level for NCS, SDI, SCLK, ERROR/WDI and SEL_VDD3/5 | 2 | V | ||||
10.2 | VDIGIN_LOW | Digital input, low level for NCS, SDI, SCLK, ERROR/WDI and SEL_VDD3/5 | 0.8 | V | ||||
10.3 | VDIGIN_HYST | Digital input hysteresis for NCS, SCI, SCLK and ERROR/WDI(3) | 0.1 | V | ||||
10.4 | RDIAGOUT_AMUX | Output resistance at DIAG_OUT pin in AMUX mode | BG1 selected on AMUX, < 200 nA current in or out of DIAG_OUT pin | 15 | kΩ | |||
10.5 | VDIGOUT_HIGH | Digital output, high level(4) | IOUT = –2 mA (out of pin) | VDDIO – 0.2 | V | |||
10.6 | VDIGOUT_LOW | Digital output, low level(4) | IOUT = 2 mA (into pin) | 0.2 | V | |||
SERIAL PERIPHERAL INTERFACE | ||||||||
13.12 | RPULL_UP | Internal pullup resistor on NCS input pin | 40 | 70 | 100 | kΩ | ||
13.13 | RPULL_DOWN | Internal pulldown resistor on SDI and SCLK input pins | 40 | 70 | 100 | kΩ |
POS | MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|---|
VDD5 – LDO WITH INTERNAL FET | |||||||
2.12 | tdelayVDD5 | VDD5 voltage stabilization delay | Maximum delay between rising edge on CANWU pin until VDD5 reaches the end-value within 2% | 5 | ms | ||
VDD3/5 – LDO WITH INTERNAL FET | |||||||
3.12 | tVDD3/5 | VDD3/5 voltage stabilization delay | Maximum delay after CANWU wakeup for VDD3/5 output to settle | 5 | ms | ||
VDD1 – LDO WITH EXTERNAL FET | |||||||
4.15 | tdelayVDD1 | VDD1 voltage stabilization delay | Maximum delay after CANWU wakeup for VDD1 output to settle | 5 | ms | ||
VOLTAGE MONITORING | |||||||
6.7 | VBATP_deglitch | VBATP undervoltage and overvoltage monitor deglitch time | 180 | 240(1) | 260 | µs | |
6.18 | VDDx_deglitch | VDDx undervoltage and overvoltage monitor deglitch time | 10 | 40 | µs | ||
6.21 | VSOUT1_deglitch | VSOUT1 undervoltage and overvoltage monitor deglitch time | 10 | 40 | µs | ||
IGNITION AND CAN WAKE-UP (IGN AND CANWU) | |||||||
7.6 | IGN_deg | IGN deglitch filter time | 7.5 | 22 | ms | ||
7.9 | CANWU_deg | CANWU deglitch filter time | 100 | 350 | µs | ||
RESET AND ENABLE OUTPUTS | |||||||
9.4 | tRSTEXT(22kΩ) | Reset extension delay | 22 kΩ | 4.05 | 4.5 | 4.95 | ms |
9.4a | tRSTEXT(0kΩ) | Reset extension delay | 0 kΩ | 0.98 | 1.4 | 1.89 | ms |
INTERNAL SYSTEM CLOCK | |||||||
11.1 | ƒSysclk | System clock frequency (2) | 3.8 | 4 | 4.2 | MHz | |
WINDOW WATCHDOG | |||||||
12.2 | tWD_pulse | Deglitch time on ERROR/WDI pin for watchdog-trigger input signal | 14.25 | 30 | 32 | µs | |
SERIAL PERIPHERAL INTERFACE TIMING(3) | |||||||
13.1 | ƒSPI | SPI clock (SCLK) frequency | VDDIO = 3.3 V | 5(4) | MHz | ||
VDDIO = 5 V | 6 | ||||||
13.2 | tSPI | SPI clock period | VDDIO = 3.3 V | 200 | ns | ||
VDDIO = 5 V | 167 | ||||||
13.3 | thigh | High time: SCLK logic high duration | See Figure 4-2 | 85.7 | ns | ||
13.4 | tlow | Low time: SCLK logic low duration | 45 | ns | |||
13.5 | tsucs | Setup time NCS: time between falling edge of NCS and rising edge of SCLK | 45 | ns | |||
13.7 | tsusi | Setup time at SDI: setup time of SDI before the falling edge of SCLK | 15 | ns | |||
13.9 | thcs | Hold time: time between the falling edge of SCLK and rising edge of NCS | 45 | ns | |||
13.10 | thlcs | SPI transfer inactive time (time between two transfers) during which NCS must remain high | 788 | ns |
POS | PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
Serial Peripheral Interface Timing(1) | |||||||
13.6 | td1 | Delay time: time delay from falling edge of NCS to SDO transitioning from tri-state to 0 | See Figure 4-2 | 53.3 | ns | ||
13.8 | td2 | Delay time: time delay from rising edge of SCLK to data valid at SDO | 0 | 85.7 | ns | ||
13.11 | ttri | Tri-state delay time: time between rising edge of NCS and SDO in tri-state | 53.3 | ns |