JAJSD95A July   2016  – May 2017 TPS65381A-Q1

PRODUCTION DATA.  

  1. 1 デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 代表的なアプリケーションの図
  2. 2 改訂履歴
  3. 3 Pin Configuration and Functions
  4. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Timing Requirements
    7. 4.7 Switching Characteristics
    8. 4.8 Typical Characteristics
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 VDD6 Buck Switch-Mode Power Supply
      2. 5.3.2 VDD5 Linear Regulator
      3. 5.3.3 VDD3/5 Linear Regulator
      4. 5.3.4 VDD1 Linear Regulator
      5. 5.3.5 VSOUT1 Linear Regulator
      6. 5.3.6 Charge Pump
      7. 5.3.7 Wake-Up
      8. 5.3.8 Reset Extension
    4. 5.4 Device Functional Modes
      1. 5.4.1  Power-Up and Power-Down Behavior
      2. 5.4.2  Safety Functions and Diagnostics Overview
      3. 5.4.3  Voltage Monitor (VMON)
      4. 5.4.4  TPS65381A-Q1 Internal Error Signals
      5. 5.4.5  Loss-of-Clock Monitor (LCMON)
      6. 5.4.6  Analog Built-In Self-Test (ABIST)
      7. 5.4.7  Logic Built-In Self-Test (LBIST)
      8. 5.4.8  Junction Temperature Monitoring and Current Limiting
      9. 5.4.9  Diagnostic MUX and Diagnostic Output Pin (DIAG_OUT)
        1. 5.4.9.1 Analog MUX (AMUX)
        2. 5.4.9.2 Digital MUX (DMUX)
        3. 5.4.9.3 Diagnostic MUX Output State (by MUX_OUT bit)
        4. 5.4.9.4 MUX Interconnect Check
      10. 5.4.10 Watchdog Timer (WD)
      11. 5.4.11 Watchdog Fail Counter, Status, and Fail Event
      12. 5.4.12 Watchdog Sequence
      13. 5.4.13 MCU to Watchdog Synchronization
      14. 5.4.14 Trigger Mode (Default Mode)
      15. 5.4.15 Q&A Mode
        1. 5.4.15.1 Watchdog Q&A Related Definitions
        2. 5.4.15.2 Watchdog Sequence in Q&A Mode
        3. 5.4.15.3 Question (Token) Generation
        4. 5.4.15.4 Answer Comparison and Reference Answer
          1. 5.4.15.4.1 Sequence of the 2-bit Watchdog Answer Counter
        5. 5.4.15.5 Watchdog Q&A Mode Sequence Events and WD_STATUS Register Updates
      16. 5.4.16 MCU Error Signal Monitor (MCU ESM)
        1. 5.4.16.1 TMS570 Mode
        2. 5.4.16.2 PWM Mode
      17. 5.4.17 Device Configuration Register Protection
      18. 5.4.18 Enable and Reset Driver Circuit
      19. 5.4.19 Device Operating States
      20. 5.4.20 STANDBY State
      21. 5.4.21 RESET State
      22. 5.4.22 DIAGNOSTIC State
      23. 5.4.23 ACTIVE State
      24. 5.4.24 SAFE State
      25. 5.4.25 State Transition Priorities
      26. 5.4.26 Power on Reset (NPOR)
    5. 5.5 Register Maps
      1. 5.5.1 Serial Peripheral Interface (SPI)
        1. 5.5.1.1 SPI Command Transfer Phase
        2. 5.5.1.2 SPI Data-Transfer Phase
        3. 5.5.1.3 Device Status Flag Byte Response
        4. 5.5.1.4 Device SPI Data Response
        5. 5.5.1.5 SPI Frame Overview
      2. 5.5.2 SPI Register Write Access Lock (SW_LOCK command)
      3. 5.5.3 SPI Registers (SPI Mapped Response)
        1. 5.5.3.1 Device Revision and ID
          1. 5.5.3.1.1 DEV_REV Register
          2. 5.5.3.1.2 DEV_ID Register
        2. 5.5.3.2 Device Status
          1. 5.5.3.2.1 DEV_STAT Register
        3. 5.5.3.3 Device Configuration
          1. 5.5.3.3.1 DEV_CFG1 Register
          2. 5.5.3.3.2 DEV_CFG2 Register
      4. 5.5.4 Device Safety Status and Control Registers
        1. 5.5.4.1  VMON_STAT_1 Register
        2. 5.5.4.2  VMON_STAT_2 Register
        3. 5.5.4.3  SAFETY_STAT_1 Register
        4. 5.5.4.4  SAFETY_STAT_2 Register
        5. 5.5.4.5  SAFETY_STAT_3 Register
        6. 5.5.4.6  SAFETY_STAT_4 Register
        7. 5.5.4.7  SAFETY_STAT_5 Register
        8. 5.5.4.8  SAFETY_ERR_CFG Register
        9. 5.5.4.9  SAFETY_BIST_CTRL Register
        10. 5.5.4.10 SAFETY_CHECK_CTRL Register
        11. 5.5.4.11 SAFETY_FUNC_CFG Register
        12. 5.5.4.12 SAFETY_ERR_STAT Register
        13. 5.5.4.13 SAFETY_ERR_PWM_H Register
        14. 5.5.4.14 SAFETY_ERR_PWM_L Register
        15. 5.5.4.15 SAFETY_PWD_THR_CFG Register
        16. 5.5.4.16 SAFETY_CFG_CRC Register
        17. 5.5.4.17 Diagnostics
          1. 5.5.4.17.1 DIAG_CFG_CTRL Register
          2. 5.5.4.17.2 DIAG_MUX_SEL Register
      5. 5.5.5 Watchdog Timer
        1. 5.5.5.1 WD_TOKEN_FDBK Register
        2. 5.5.5.2 WD_WIN1_CFG Register
        3. 5.5.5.3 WD_WIN2_CFG Register
        4. 5.5.5.4 WD_TOKEN_VALUE Register
        5. 5.5.5.5 WD_STATUS Register
        6. 5.5.5.6 WD_ANSWER Register
      6. 5.5.6 Sensor Supply
        1. 5.5.6.1 SENS_CTRL Register
  6. 6 Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 VDD6 Preregulator
        2. 6.2.2.2 VDD1 Linear Controller
        3. 6.2.2.3 VSOUT1 Tracking Linear Regulator, Configured to Track VDD5
        4. 6.2.2.4 Alternative Use for VSOUT1 Tracking Linear Regulator, Configured for 6-V Output Tracking VDD3/5 In 3.3-V Mode
        5. 6.2.2.5 Alternative Use for VSOUT1 Tracking Linear Regulator, Configured for 9-V Output Tracking to 5-V Input from VDD5
        6. 6.2.2.6 Alternative Use for VSOUT1 Tracking Linear Regulator, Configured in Non-tracking Mode Providing a 4.5-V Output
      3. 6.2.3 Application Curves
    3. 6.3 System Examples
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 VDD6 Buck Preregulator
      2. 8.1.2 VDD1 Linear Regulator Controller
      3. 8.1.3 VDD5 and VDD3/5 Linear Regulators
      4. 8.1.4 VSOUT1 Tracking Linear Regulator
      5. 8.1.5 Charge Pump
      6. 8.1.6 Other Considerations
    2. 8.2 Layout Example
    3. 8.3 Power Dissipation and Thermal Considerations
  9. 9 デバイスおよびドキュメントのサポート
    1. 9.1 ドキュメントのサポート
      1. 9.1.1 関連資料
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 Community Resources
    4. 9.4 商標
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 Glossary
  10. 10メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Specifications

4.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)(2)
POS MIN MAX UNIT
M1.1 Protected-battery voltage VBATP, VBAT_SAFING, VSIN –0.3 40 V
M1.2 Charge-pump voltage VCP, CP1(3) –0.3 lesser of VBATP + 16 or 52 V
M1.3 Charge-pump pumping capacitor voltage CP2 –0.3 40 V
M1.3a Charge-pump overdrive voltage VCP(3)-VBATP –0.3 16 V
M1.4 VDD6 switching-node voltage SDN6 –0.3 40 V
M1.5 VDD6 output voltage VDD6 –0.3 40 V
M1.6 VDD5 output voltage VDD5 –0.3 7 V
M1.7 VDD3/5 output voltage VDD3/5 –0.3 7 V
M1.8 VDD1_G voltage VDD1_G –0.3 15 V
M1.10 VDD1_SENSE voltage VDD1_SENSE –0.3 7 V
M1.11 Sensor supply tracking voltage VTRACK1 –0.3 40 V
M1.12 Sensor supply output and feedback voltage VSOUT1, VSFB1(4) –2 18 V
M1.14 Analog/digital reference output voltage DIAG_OUT –0.3 7 V
M1.15 Logic I/O voltage VDDIO, ERROR/WDI, ENDRV, NRES, NCS, SDI, SDO, SCLK, RSTEXT –0.3 7 V
M1.16 SEL_VDD3/5 –0.3 40 V
M1.17 IGN wakeup IGN –7 40 V
M1.18 CAN wakeup CANWU –0.3 40 V
M1.19 Operating virtual junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground pin unless otherwise noted.
(3) VCP and CP1 are output pins, no external voltage should be applied to these pins. Absolute Maximum ratings for these pins are what may appear on the pins.
(4) VSOUT1 is connected to VSFB1 directly (for unity gain) or through resistor divider (tracking mode gain or non-tracking mode output voltage adjusting). In case of a short to supply fault, the voltage on VSOUT1 is equal to the supply to the device (VBATP, VBAT_SAFING, and VSIN where VSIN is connected to VBATP as it's supply instead of VDD6) and VSFB1 voltage will follow VSOUT1 based on the use case, directly (for unity gain) or via resistor divider (tracking mode gain or non-tracking mode output voltage adjusting).

4.2 ESD Ratings

POS. VALUE UNIT
M1.21 V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) All pins except VSOUT1 (17) and VSFB1 (15) ±2000 V
M1.20 On sensor supply pins VSOUT1 (17) and VSFB1 (15) ±4000
M1.22 Charged device model (CDM), per AEC Q100-011 Corner pins (1, 16, 17, and 32) ±750
M1.23 All pins ±500
(1) AEC Q100-002 indicates that HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 Specification.

4.3 Recommended Operating Conditions

Over operating temperature range and with respect to the GND and PGND (GND = PGND) pins (unless otherwise noted)
POS MIN MAX UNIT
M1.20a Operating ambient temperature, TA –40 125 °C
R1.1 Minimum input supply voltage on VBATP for initial power up (POS 6.2, VBATP_UVon)(2)(3) 5.8(4) V
R1.2 Input supply voltage on VBATP (2)(3)(1)
  • To support operation when VBATP is between 5.8 V and 7 V, the device remains functional. Some rails can be in dropout or undervoltage depending on actual input supply and the configuration of the specific regulator.
  • VDD6 can be in dropout mode (100% duty cycle)
  • VDD3/5 configured for 5-V output can be in dropout. If the output reaches VDD3/5_UV threshold, the device transitions to the RESET state because of a VDD3/5 undervoltage event. If VDD3/5 is configured for 3.3-V output it remains functional.
  • VDD5 can be in dropout. If output reaches the VDD5_UV threshold, the device indicates the undervoltage event through the VDD5_UV status bit.
  • VSOUT1 can be in dropout depending on configuration. If output reaches VSOUT1_UV threshold, the device indicates the undervoltage event through the VSOUT1_UV status bit.
5.8 34(6) V
R1.3 Input supply voltage on VBATP after initial power up, functional operation during low input supply voltage events, (POS 6.1, VBATP_UVoff):(2)(5)
  • The device remains functional. Some rails can be in dropout or undervoltage depending on actual input supply and the configuration of the specific regulator.
  • VDD6 is in dropout mode (100% duty cycle).
  • VDD3/5 configured for 5-V output can be in dropout. If the output reaches VDD3/5_UV threshold, the device transitions to the RESET state because of a VDD3/5 undervoltage event. If VDD3/5 is configured for 3.3-V output it remains functional.
  • VDD5 can be in dropout. If the output reaches VDD5_UV threshold, the device indicates the undervoltage event through the VDD5_UV status bit.
  • VSOUT1 may be in dropout depending on configuration, if output reaches VSOUT1_UV threshold the device indicates the undervoltage event through the VSOUT1_UV status bit.
 4.5 5.8 V
R1.4 VDDIO supply-voltage range 3.3 5 V
R1.5 Current consumption in standby mode (all regulator outputs disabled)
IGN = 0 V, CANWU = 0 V, 5.8 V ≤ VBAT ≤ 20 V for TJ < 85°C or 5.8 V ≤ VBAT ≤ 14 V tor TJ = 125°C		 75 µA
(1) Under slow VBAT ramp-down and when VDD3/5 rail is configured as a 5-V rail, the NRES output can be pulled low when VBAT is at approximately 6.3 V. This occurs because of an undervoltage transient on the VDD3/5 rail.
Under slow VBAT ramp-up and when VDD3/5 rail is configured as a 5-V rail, the NRES output can be pulled low when VBAT is at approximately 6.6 V. This occurs because of an undervoltage transient on VDD3/5 rail. Under similar conditions, undervoltage transients are observed on VDD5 and VSOUT1 rails (refer to Device Behavior Under Slow VBAT Ramp-Up and Ramp-Down).
(2) VBATP should be connected to VBAT_SAFING.
(3) VBAT_SAFING has a supply high enough to power the VMON block and internal rail AVDD_VMON above AVDD_VMON_UV.
(4) The device may power up when VBATP is less than 5.8 V, but it will always power up when VBATP is 5.8V or greater, while VBAT_SAFING has a supply high enough to power the VMON block and internal rail AVDD_VMON above AVDD_VMON_UV.
(5) The device will remain on if VBATP drops from 5.8V down to VBATP_UVoff threshold or another voltage monitor detects an undervotlage on a specific rail and changes the device state. VBAT_UVoff can be detected at 4.5 V but could be detected as low as 4.2 V. VBAT_SAFING has a supply high enough to power the VMON block and internal rail AVDD_VMON above AVDD_VMON_UV.
(6) The recommended maximum operating voltage for VBATP and VBAT_SAFING is listed as 34 V, just below the overvoltage detection thresholds for VBATP, VBATP_OVrise and VBATP_OVfall. TI recommends enabling overvoltage detection on VBATP (default is enabled, MASK_VBATP_OV = 0). TI also recommends evaluating the thermal and power dissipation of the device in the application and ensure the design has adequate thermal management for operation at the necessary supply voltage level.

4.4 Thermal Information

THERMAL METRIC(1) TPS65381A-Q1 UNIT
DAP (HTSSOP)
32 PINS
RθJA Junction-to-ambient thermal resistance 26.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 14.1 °C/W
RθJB Junction-to-board thermal resistance 6 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 6.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
TPS65381A-Q1 power_dissipation_slvsbc4.gif
1. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TAmax) is dependent on the maximum-operating junction temperature (TJmax), the maximum power dissipation of the device in the application (PDmax), and the junction-to-ambient thermal resistance of the part/package in the application (RθJA), as given by the following equation: TAmax = TJmax – (RθJA × PDmax).
2. Maximum power dissipation is a function of TJmax, RθJA, and TA. The maximum-allowable power dissipation at any allowable ambient temperature is PD = (TJmax – TA) / RθJA.
Figure 4-1 Derating Profile for Power Dissipation Based on High-K JEDEC PCB

4.5 Electrical Characteristics

Over operating ambient temperature TA = –40°C to the maximum-operating junction temperature TJ = 150°C, and with VBATP = VBAT_SAFING in the recommended operating range (see R1.2 in Section 4.3) (unless otherwise noted)
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD6-BUCK WITH INTERNAL FET
AN CVDD6 Value of output ceramic capacitor(1) ESR range 100 mΩ to 300 mΩ(2) 22 47 µF
AN LVDD6 Value of inductor 22 33 µH
1.1 VDD6 VDD6 output voltage Average DC value excluding ripple and load transients, VBAT > 7 V, 0 < IVDD6 < 1.3 A, including dc line and load regulation, temperature drift, and long-term drift where VBAT = VBATP = VBAT_SAFING 5.4 6 6.6 V
1.1a VDD6ripple VDD6 ripple voltage Peak-to-peak, ensured by design
VBATP = VBAT_SAFING = 14 V, L = 33 µH, C = 22 µF		 200 mV
1.2 IVDD6 VDD6 output current IVDD5 + IVDD3/5 + IVDD1+ IVSOUT1(6) 1.3 A
1.3 Vdropout6 VDD6 output dropout voltage Vdropout6 = (VBATP – SDN6) IVDD6 = 1.3 A
(example: RDS(on) = 0.46 Ω)		 0.6 V
1.4 IVDD6_limit Peak current out of SDN6 pin(21) 1.5 2.5 A
1.5 ƒclk_VDD6 Clock Frequency (5) 396 440 484 kHz
1.6 DCVDD6 ton/tperiod 0 < IVDD6 < 1.3 A
VDD6 enters dropout mode (100% duty cycle) for VBATP < 7 V 		7%(22) 100%
1.7 TprotVDD6 Temperature protection threshold(7) 175 210 °C
VDD5 – LDO WITH INTERNAL FET
AN CVDD5 Value of output ceramic capacitor ESR range 0 mΩ to 100 mΩ 1 5 µF
2.1 VDD5 VDD5 output voltage(8) 0 < IVDD5 < 300 mA 4.9 5 5.1 V
2.2 IVDD5 VDD5 output current, including load from the internal resistor of 660 Ω (typical) 300 mA
2.3 VDD5dyn VDD5 output voltage dynamic Load step 20% to 80% in 5 µs, with CVDD5 = 5 µF 4.85 5 5.15 V
2.4 VDD5max Maximum VDD5 output voltage during VBATP step from 5.5 V to 13.5 V within 10 μs CVDD5 = 5 µF, IVDD5 < 300 mA 5.5 V
2.5 Vdropout5 VDD5 output dropout voltage Vdropout5 = (VDD6 – VDD5) IVDD5 < 300 mA 0.3 V
2.6 PSRRVDD5 Power supply rejection ratio 50 < f < 20 kHz, VBATP = 10 V, U = 4 Vpp,
CVDD5 = 5 μF, 0 < IVDD5 < 300 mA		 > 40 dB
2.7 LnRegVDD5 Line regulation (IVDD5 constant) 0 < IVDD5 < 300 mA,
8 V < VBATP < 19 V 		–25 25 mV
2.8 LdRegVDD5 Load regulation (VDD6 constant) 0 < IVDD5 < 300 mA,
8 V < VBATP < 19 V 		–25 25 mV
2.9 TmpCoVDD5 Temperature drift Normalized to 25°C value –0.5% 0.5%
2.11 dVDD5/dt dV/dt at VDD5 at startup Between 10% and 90% of VDD5 end-value 5 50 V/ms
2.13 TprotVDD5 Temperature protection threshold(9) 175 210 °C
2.14 IVDD5_limit Current-limit(26) 350 650 mA
VDD3/5 – LDO WITH INTERNAL FET
AN CVDD3/5 Value of output ceramic capacitor ESR range 0 mΩ to 100 mΩ 1 5 µF
3.1a VDD3/5 VDD3/5 output voltage, SEL_VDD3/5 pin: open = 3.3 V setting, ground = 5 V setting 0 < IVDD3/5 < 300 mA 3.3-V Setting 3.234 3.3 3.366 V
3.1b 5-V Setting 4.9 5 5.1
3.2 IVDD3/5 VDD3/5 output current, including load from the internal resistor of 440 Ω (typ.) for 3.3 V setting or 660 Ω (typ.) for 5 V setting(23) 300 mA
3.3a VDD3/5dyn VDD3/5 output voltage dynamic Load step 20% to 80% in 5 µs, with
CVDD3/5 = 5 µF 		3.3-V Setting 3.15 3.3 3.43 V
3.3b 5-V Setting 4.85 5 5.15
3.4 VDD3/5max Maximum VDD3/5 output voltage during VBATP step from 5.5 V to 13.5 V within 10 μs CVDD3/5 = 5 µF, IVDD3/5 < 300 mA 3.3-V Setting 3.6 V
5-V Setting 5.5
3.5 Vdropout3/5 VDD3/5 output dropout voltage Vdropout3/5 = (VDD6–VDD3/5) IVDD3/5 < 300 mA 0.3 V
3.6 PSRRVDD3/5 Power-supply rejection ratio 50 < f < 20 kHz, VBATP = 10 V, U = 4 Vpp
CVDD3/5 = 5 μF, 0 < IVDD3/5 < 300 mA		 > 40 dB
3.7 LnRegVDD3/5 Line regulation (IVDD3 constant) 0 < IVDD3/5 < 300 mA,
8 V < VBATP < 19 V 		–25 25 mV
3.8 LdRegVDD3/5 Load regulation (VDD6 constant) 0 < IVDD3/5 < 300 mA
8 V < VBATP < 19 V 		–25 25 mV
3.9 TmpCoVDD3/5 Temperature drift Normalized to 25°C value –0.5% 0.5%
3.11 dVDD35/dt dV/dt at VDD3/5 at start-up Between 10% and 90% of VDD3/5 end-value 3.3-V Setting 3 30 V/ms
5-V Setting 5 50
3.13 TprotVDD3/5 Temperature protection threshold(10) 175 210 °C
3.14 IVDD3/5_limit Current-limit(27) 350 650 mA
3.15 Ipu_SEL_VDD3/5 Pullup current on SEL_VDD3/5 pin 20 µA
VDD1 – LDO WITH EXTERNAL FET
AN Vgs(th) Gate threshold voltage, external FET ID = 1 mA 0.3 3 V
AN Ciss Gate capacitance, external FET VGS = 0 V 3200 pF
AN Qgate Gate Charge, external FET VGS = 0 V to 10 V 70 nC
AN gfs Forward transconductance, external FET ID = 50 mA 0.4 S
AN CVDD1 Value of output ceramic capacitor ESR range 0 mΩ to 100 mΩ 5 40 µF
4.1 VDD1 VDD1 output voltage, depends on external resistive divider 0.8 3.3 V
4.2 VDD1SENSE VDD1 reference voltage(11) 10 mA < IVDD1 < 600 mA 0.792 0.8 0.808 V
4.2a VDD1SENSE_BIAS Bias current of VDD1SENSE –6.6 –10 µA
4.3 IVDD1 VDD1 output current Minimum current realized with external resistive divider 10 600 mA
4.4 VDD1G VDD1_G output voltage Referenced to GND 15 V
4.5 VDD1G_off VDD1_G voltage in OFF condition 20 µA into VDD1_G pin 0.3 V
4.6 I_VDD1G VDD1_G DC load current 200 µA
4.7 VDD1dyn VDD1 output voltage dynamic Load step 10% to 90% in 1 μs, with CVDD1 = 40 μF(24) ± 4%
4.8 VDD1max Maximum VDD1 output voltage during VBATP step from 5.5 V to 13.5 V within 10 μs CVDD1 > 6 µF, IVDD1< 600 mA VDD1 = 0.8-V output 0.898 V
VDD1 = 1.23-V output 1.287
VDD1 = 3.3-V output 3.435
4.9 PSRRVDD1 Power-supply rejection ratio 50 < f < 20 kHz, VBATP = 10 V, U = 4 Vpp,
CVDD1 = 10 μF, 10 mA < IVDD1 < 600 mA		 > 40 dB
4.10 LnRegVDD1 Line regulation on VDD1_SENSE (IVDD1 constant) 10 mA < IVDD1< 600 mA, 8 V < VBATP < 19 V –7 7 mV
4.11 LdRegVDD1 Load regulation on VDD1_SENSE (VDD6 constant) 10 mA < IVDD1 < 600 mA, 8 V < VBATP < 19 V –7 7 mV
4.12 TmpCoVDD1 Temperature drift Normalized to 25°C value –0.5% 0.5%
4.14 dVDD1/dt dV/dt at VDD1_SENSE at start-up Between 10% and 90% of VDD1 end-value 0.8 8 V/ms
VSOUT1 – LDO WITH PROTECTED INTERNAL FET
AN CVSOUT1 Value of output ceramic capacitor ESR range 0 mΩ to 100 mΩ 0.5 10 µF
5.1 VSOUT1 VSOUT1 output voltage, depends on external resistive divider and tracking or non-tracking mode 3.3 9.5 V
5.2 MVVSOUT1 For tracking mode:
Matching output error MVVSOUT1 = (VTRACK1 – VSFB1)(12)		 0 < IVSOUT1 < 100 mA –35 35 mV
5.3 VSFB1 For non-tracking mode: VSOUT1 reference voltage(13) 10 mA < IVSOUT1 < 100 mA 2.45 2.5 2.55 V
5.3a VTRACK1th Threshold for selecting tracking/non-tracking mode (VTRACK1 > VTRACK1th_max V for tracking mode, VTRACK1 < VTRACK1th_min V non-tracking mode)
1.1 1.2 1.3 V
5.3b VTRACK1pd Internal pulldown resistance on VTRACK1 pin 100 kΩ
5.4 IVSOUT1 VSOUT1 output current, including internal resistor to dissipate minimum current(25) 100 mA
5.5 VdrS1 VSOUT1 dropout voltage VdrS1 = (VSIN-VSOUT1) 0 < IVSOUT1 < 100 mA 0.75 V
5.6 PSRRVSOUT1 Power-supply rejection ratio With VTRACK1 = GND, VSOUT1 = 4.5V,
50 < f < 20 kHz, VSIN = 10 V, U = 4 Vpp
CVSOUT1 = 1 μF, 0 < IVSOUT1 < 100 mA, 		> 40 dB
5.7 LnRegVSOUT1 Line regulation (IVSOUT1 constant) 0 < IVSOUT1 < 100 mA, 8 V < VSIN < 19 V –25 25 mV
5.8 LdRegVSOUT1 Load regulation (VSIN constant) 0 < IVSOUT1 < 100 mA, 8 V < VSIN < 19 V –35 35 mV
5.9 TmpCoVSOUT1 Temperature drift Normalized to 25°C value –0.5% 0.5%
5.11 VSOUT1SH Output short circuit voltage range VSOUT1 (VSFB1 configured for regulation)(28) –2 18 V
5.12 –IVSIN Output reverse current VSOUT1 = 14 V and VBATP = 0 V, regulator switched off 20 mA
5.13 TprotVSOUT1 Temperature protection threshold(14) 175 210 °C
5.14 IVSOUT1_limit Current-limit 120 500 mA
VOLTAGE MONITORING
6.1 VBATP_UVoff VBATP and VBAT_SAFING level for indication by VBAT_UV comparitor(15) VBATP = VBAT_SAFING 4.2 4.5 V
6.2 VBATP_UVon VBATP and VBAT_SAFING level for indication by VBAT_UV comparitor(15) VBATP = VBAT_SAFING 5.4 5.8 V
6.3 VBATP_UVhys Undervoltage hysteresis VBATP = VBAT_SAFING 1.1 1.4 V
6.4 VBATP_OVrise VBATP level for setting VBAT_OV flag(16) VBATP = VBAT_SAFING 34.7 36.7 V
6.5 VBATP_OVfall VBATP level for clearing VBAT_OV flag(17) VBATP = VBAT_SAFING 34.4 36.3 V
6.8 VDD5_UV VDD5 undervoltage level VBATP = VBAT_SAFING 4.5 4.85 V
6.8a Hysteresis VBATP = VBAT_SAFING 140 mV
6.9 VDD5_UVhead VDD5 undervoltage headroom (VDD5act – VDD5_UVact) VBATP = VBAT_SAFING 200 mV
6.10 VDD5_OV VDD5 overvoltage level VBATP = VBAT_SAFING 5.2 5.45 V
6.10a Hysteresis VBATP = VBAT_SAFING 140 mV
6.11 VDD5_OVhead VDD5 overvoltage headroom (VDD5_OVact – VDD5act) VBATP = VBAT_SAFING 200 mV
6.12 VDD3/5_UV VDD3/5 undervoltage level VBATP = VBAT_SAFING 3.3-V setting 3 3.17 V
5-V setting 4.5 4.85
6.12a Hysteresis VBATP = VBAT_SAFING 3.3-V setting 100 mV
5-V setting 140
6.13 VDD3/5_UVhead VDD3/5 undervoltage headroom
(VDD3/5act – VDD3/5_UVact) 		VBATP = VBAT_SAFING 3.3-V setting 155 mV
5-V setting 200
6.14 VDD3/5_OV VDD5_3 overvoltage level VBATP = VBAT_SAFING 3.3-V setting 3.43 3.6 V
5-V setting 5.2 5.5
Hysteresis VBATP = VBAT_SAFING 3.3-V setting 100 mV
6.14a 5-V setting 140
6.15 VDD3/5_UVhead VDD3/5 undervoltage headroom
(VDD3/5_OVact – VDD3/5act) 		VBATP = VBAT_SAFING 3.3-V setting 170 mV
5-V setting 200
6.16 VDD1_UV VDD1 undervoltage level VBATP = VBAT_SAFING. Sensed on VDD1_SENSE pin. Relative thresholds are with respect to nominal 800-mV VDD1SENSE (Pos 4.2) 752 784 mV
6.16a Hysteresis VBATP = VBAT_SAFING. Sensed on VDD1_SENSE pin. Relative thresholds are with respect to nominal 800-mV VDD1SENSE (Pos 4.2) 10 mV
6.17 VDD1_OV VDD1 overvoltage level VBATP = VBAT_SAFING. Sensed on VDD1_SENSE pin. Relative thresholds are with respect to nominal 800-mV VDD1SENSE (Pos 4.2) 816 848 mV
6.17a Hysteresis VBATP = VBAT_SAFING. Sensed on VDD1_SENSE pin. Relative thresholds are with respect to nominal 800-mV VDD1SENSE (Pos 4.2) 9 mV
6.19 VSOUT1_UV VSOUT1 undervoltage level Sensed on VSFB1 pin. Relative thresholds (ratio) are:
  • For non-tracking mode, with respect to nominal 2.5-V VSFB1 (Pos 5.3)
  • For tracking mode, with respect to voltage applied on VTRACK1 pin
  • In tracking mode, VSOUT1_UV comparator output is valid for VTRACK1 DC condition
 0.88 0.94 VSOUT1
6.20 VSOUT1_OV VSOUT1 overvoltage level Sensed on VSFB1 pin. Relative thresholds (ratio) are:
  • For non-tracking mode, with respect to nominal 2.5-V VSFB1 (Pos 5.3)
  • For tracking mode, with respect to voltage applied on VTRACK1 pin
  • In tracking mode, VSOUT1_OV comparator output is valid for VTRACK1 DC condition
 1.06 1.12 VSOUT1
6.22 VDD6_UV VDD6 undervoltage level(18) 5.2 5.4 V
6.22a Hysteresis 115 mV
6.23 VDD6_OV VDD6 overvoltage level(18) 7.8 8.2 V
6.23a Hysteresis 115 mV
IGNITION AND CAN WAKE-UP
7.1 IGN_WUP IGN wake-up threshold(19) VBATP = VBAT_SAFING =12 V 2 3 V
7.2 CAN_WUP CAN wake-up threshold(19) VBATP = VBAT_SAFING =12 V 2 3 V
7.3 WUP_hyst Wake-up hysteresis VBATP = VBAT_SAFING =12 V 50 200 mV
7.4 I_IGN IGN pin forward leakage current IGN pin at 36 V, VBATP = VBAT_SAFING = 12V 50 µA
7.5 I_IGN_rev IGN reverse current IGN at –7 V, VBATP = VBAT_SAFING =12 V –1 mA
7.7 I_CANWU CANWU pin forward leakage current CANWU pin at 36 V, VBATP = VBAT_SAFING = 12V 50 µA
7.8 I_CAN_rev CANWU reverse current CANWU at –0.3 V, VBATP = VBAT_SAFING =12 V mA
CHARGE PUMP
AN Cpump Pumping capacitor (between CP1 and CP2) 10 nF
AN Cstore Storage capacitor (between VCP and VBATP) 100 nF
8.1 VCPon VCP output voltage in on-state VBATP > 5.8 V VBATP + 4 VBATP + 15 V
8.2 ICP External load Load coming from RGS of Reverse Battery Protection 100 µA
8.3 fCP Charge-pump switching frequency 225 250 275 kHz
RESET AND ENABLE OUTPUTS
9.1 VNRES_ENDRV_L NRES / ENDRV low-output level With external 2-mA open-drain current 0.2 V
9.2 RNRES_ENDRV_PULLUP NRES / ENDRV internal pullup resistance 3 6 kΩ
9.2a RDS(on)_ENDRV_NRES RDS(on) NRES/ENDRV pulldown transistor 40 Ω
9.3 RRSTEXT Value of external reset extension resistor, in case of open-connect, device stays in RESET state(20) 0 22 kΩ
9.5 VENDRV_NRES_TH ENDRV and NRES input readback logic 1 threshold Read-back muxed to DIAG_OUT pin 350 400 450 mV
DIGITAL INPUT / OUTPUT
10.1 VDIGIN_HIGH Digital input, high level for NCS, SDI, SCLK, ERROR/WDI and SEL_VDD3/5 2 V
10.2 VDIGIN_LOW Digital input, low level for NCS, SDI, SCLK, ERROR/WDI and SEL_VDD3/5 0.8 V
10.3 VDIGIN_HYST Digital input hysteresis for NCS, SCI, SCLK and ERROR/WDI(3) 0.1 V
10.4 RDIAGOUT_AMUX Output resistance at DIAG_OUT pin in AMUX mode BG1 selected on AMUX, < 200 nA current in or out of DIAG_OUT pin 15 kΩ
10.5 VDIGOUT_HIGH Digital output, high level(4) IOUT = –2 mA (out of pin) VDDIO – 0.2 V
10.6 VDIGOUT_LOW Digital output, low level(4) IOUT = 2 mA (into pin) 0.2 V
SERIAL PERIPHERAL INTERFACE
13.12 RPULL_UP Internal pullup resistor on NCS input pin 40 70 100 kΩ
13.13 RPULL_DOWN Internal pulldown resistor on SDI and SCLK input pins 40 70 100 kΩ
(1) Capacitance is effective capacitance after derating for operating voltage, temperature, and lifetime.
(2) ESR is total effective series resistance of the capacitors and if necessary added series resistor.
(3) SEL_VDD3/5 is sampled and latched at device power up hysteresis, VDIGIN_HYST , does not apply.
(4) For pins SDO and DIAG_OUT in DMUX mode.
(5) Actual switching on SND6 depends on whether output voltage on VDD6 is above or below hysteretic PWM comparator threshold at the moment of the rising edge of the Fclk_VDD6 clock. If no switching is needed when the risking edge of the Fclk_VDD6 clock occurs, SDN6 will not switch on. SDN6 turn off is determined by the hysteretic PWM comparator threshold, when the actual VDD6 voltage is above the threshold SDN6 will turn off.
(6) IVDD6 is the load current from VDD5, VDD3/5, VDD1 and VSOUT1 on VDD6 regulator; VDD6 is not recommended to be loaded directly for applications or peripherals that cannot operate with wider tolerance and ripple since VDD6 is a pre-regulator. However, LDOs or DC-DC converters may be connected directly as along as the total load current on VDD6, IVDD6, does not exceed the specification for VDD6 load current.
(7) Protection of VDD6, shared with VDD3/5 overtemperature protection.
(8) VDD5 output regulation includes line and load regulation, temperature drift.
(9) Protection of VDD5. In case of detected overtemperature, only VDD5 will be switched off.
(10) Protection of VDD3/5, treated as global overtemperature (shutdown for all regulators).
(11) VDD1 regulation including line and load regulation, temperature drift and long-term drift. Does not include tolerance of resistor divider to set VDD1 output voltage.
(12) Referenced to VTRACK1 input, including long-term and temperature drift.
(13) VSOUT1 including line and load regulation, temperature drift and long-term drift.
(14) Protection of VSOUT1 Sensor Supply. Only VSOUT1 switch-offs off.
(15) VBATP_UVoff and VBATP_UVon are the threshold levels for VBATP where UV will be indicated by the VBAT_UV bit in VMON_STAT_1 register. The VBATP level that will allow device power up is outlined by R1.1.
(16) Brings device into the RESET state and sets flag in SPI
(17) Clears flag in SPI
(18) Information in SPI register only
(19) For device wake up, VBATP and VBAT_SAFING must be operating range, Recommended Operating Conditions R1.1 and R1.3a, and then a level on either IGN or CANWU to allow the device to start up, especially when VBATP and VBAT_SAFING are ramping.
(20) The maximum resistance recommend for RSTEXT to ground is 120 kΩ.
(21) VDD6 current limit is based on the peak current through SDN6 switch, it will not directly correspond to an average current limit.
(22) When the VDD6 control loop turns the SDN6 switch on at the rising edge of a fclk_VDD6 clock cycle, SDN6 will remain on with a minimum duty cycle of 7%. However, if the control loop skips a clock cycle the duty cycle will be 0% for that fclk_VDD6 clock cycle.
(23) Less than 50% of maximum loading of IVDD3/5 should be placed on the VDD3/5 regulator before NRES goes high during device power up.
(24) VDD1dyn will depend on external FET choice
(25) VSOUT1 maximum power dissipation for the internal FET must not exceed 0.6 W to avoid overtemperature. Special consideration must be taken for output voltages greater than 5 V and when VBATP is used to supply VSIN instead of VDD6.
(26) IVDD5_limit current limit has snap back behavior. During a short circuit condition, a transient current higher than the maximum will occur until the current limit snaps back into the specified range.
(27) IVDD3/5_limit current limit has snap back behavior. During a short circuit condition, a transient current higher than the maximum will occur until the current limit snaps back into the specified range.
(28) VSOUT1 is connected to VSFB1 directly (for unity gain) or through resistor divider (tracking mode gain or non-tracking mode output voltage adjusting). In case of a short to supply fault, the voltage on VSOUT1 is equal to the supply to the device (VBATP, VBAT_SAFING, and VSIN where VSIN is connected to VBATP as it's supply instead of VDD6) and VSFB1 voltage will follow VSOUT1 based on the use case, directly (for unity gain) or via resistor divider (tracking mode gain or non-tracking mode output voltage adjusting).

4.6 Timing Requirements

Over operating ambient temperature TA = –40°C to the maximum-operating junction temperature TJ = 150°C, and VBATP = VBAT_SAFING in the recommended operating range (see R1.2 in the Section 4.3) (unless otherwise noted)
POS MIN NOM MAX UNIT
VDD5 – LDO WITH INTERNAL FET
2.12 tdelayVDD5 VDD5 voltage stabilization delay Maximum delay between rising edge on CANWU pin until VDD5 reaches the end-value within 2% 5 ms
VDD3/5 – LDO WITH INTERNAL FET
3.12 tVDD3/5 VDD3/5 voltage stabilization delay Maximum delay after CANWU wakeup for VDD3/5 output to settle 5 ms
VDD1 – LDO WITH EXTERNAL FET
4.15 tdelayVDD1 VDD1 voltage stabilization delay Maximum delay after CANWU wakeup for VDD1 output to settle 5 ms
VOLTAGE MONITORING
6.7 VBATP_deglitch VBATP undervoltage and overvoltage monitor deglitch time 180 240(1) 260 µs
6.18 VDDx_deglitch VDDx undervoltage and overvoltage monitor deglitch time 10 40 µs
6.21 VSOUT1_deglitch VSOUT1 undervoltage and overvoltage monitor deglitch time 10 40 µs
IGNITION AND CAN WAKE-UP (IGN AND CANWU)
7.6 IGN_deg IGN deglitch filter time 7.5 22 ms
7.9 CANWU_deg CANWU deglitch filter time 100 350 µs
RESET AND ENABLE OUTPUTS
9.4 tRSTEXT(22kΩ) Reset extension delay 22 kΩ 4.05 4.5 4.95 ms
9.4a tRSTEXT(0kΩ) Reset extension delay 0 kΩ 0.98 1.4 1.89 ms
INTERNAL SYSTEM CLOCK
11.1 ƒSysclk System clock frequency (2) 3.8 4 4.2 MHz
WINDOW WATCHDOG
12.2 tWD_pulse Deglitch time on ERROR/WDI pin for watchdog-trigger input signal 14.25 30 32 µs
SERIAL PERIPHERAL INTERFACE TIMING(3)
13.1 ƒSPI SPI clock (SCLK) frequency VDDIO = 3.3 V 5(4) MHz
VDDIO = 5 V 6
13.2 tSPI SPI clock period VDDIO = 3.3 V 200 ns
VDDIO = 5 V 167
13.3 thigh High time: SCLK logic high duration See Figure 4-2 85.7 ns
13.4 tlow Low time: SCLK logic low duration 45 ns
13.5 tsucs Setup time NCS: time between falling edge of NCS and rising edge of SCLK 45 ns
13.7 tsusi Setup time at SDI: setup time of SDI before the falling edge of SCLK 15 ns
13.9 thcs Hold time: time between the falling edge of SCLK and rising edge of NCS 45 ns
13.10 thlcs SPI transfer inactive time (time between two transfers) during which NCS must remain high 788 ns
(1) 240 µs for VBAT-UV deglitch and 260 µs for VBAT-OV deglitch
(2) The system clock is also used to derive the clock for the watchdog timer, so the system clock tolerance also impacts the watchdog-timer tolerance.
(3) Capacitance at CSDO = 100 pF
(4) MAX SPI Clock tolerance is ±10%

4.7 Switching Characteristics

Over operating ambient temperature TA = –40°C to the maximum-operating junction temperature TJ = 150°C, and VBATP = VBAT_SAFING in the recommended operating range (see R1.2 in Section 4.3) (unless otherwise noted)
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Serial Peripheral Interface Timing(1)
13.6 td1 Delay time: time delay from falling edge of NCS to SDO transitioning from tri-state to 0 See Figure 4-2 53.3 ns
13.8 td2 Delay time: time delay from rising edge of SCLK to data valid at SDO 0 85.7 ns
13.11 ttri Tri-state delay time: time between rising edge of NCS and SDO in tri-state 53.3 ns
(1) Capacitance at CSDO = 100 pF
TPS65381A-Q1 SPI_Tim_lvsbc4.gif Figure 4-2 SPI Timing Parameters
TPS65381A-Q1 C001_SLVSBC4.gif Figure 4-3 SPI SDO Buffer Source and Sink Current

4.8 Typical Characteristics

TPS65381A-Q1 D001_slvsbc4.gif
Figure 4-4 VDD6 BUCK Efficiency