SLVSCQ2 Data sheet

SLVSCQ2 July 2015 TPS65400-Q1

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RGZ|48
- MPQF123F

サーマルパッド・メカニカル・データ

RGZ|48
- QFND014T

発注情報

8 Detailed Description

8.1 Overview

The TPS65400-Q1 is an integrated PMU optimized for applications that require small form factor and high-power conversion efficiency enabling small space-constrained equipment with high-ambient operating temperature without cooling. It provides high-power efficiency at a system level by enabling a single-stage conversion from an intermediate distribution bus with an optimized combination of regulators.

The TPS65400-Q1 consists of four high-current buck-switching regulators (SW1, SW2, SW3, and SW4) with integrated FETs. The switching power supplies are intended for powering high-current digital circuits such as the processor, FPGA, ASIC, memory, and digital I/Os. SW1 and SW2 support 4 A each, and SW3 and SW4 support 2 A each. Each regulator’s switching frequency is independently adjustable up to 2.2 MHz.

Current limit programmability on each switcher enables optimization of inductor ratings for a particular application configuration not requiring the maximum current capability.

The TPS65400-Q1 can be powered from a single-input voltage rail between 4.5 and 18 V, making it suitable for applications running off a 5- or 12-V intermediate power distribution bus.

Sequencing requirements can be met using the individual enable pins or by programming the sequence through the I²C bus into the onboard EEPROM. Output voltages can be set through external resistor networks and VREF can be programmed from 0.6 to 1.87 V in 10-mV steps. All control and status info can be accessed through a PMBus-compatible I²C bus.

The TPS65400-Q1 provides a high level of flexibility for monitoring and control through the I²C bus while providing the option of programmability through the use of external components and voltage levels for systems not using I²C.

8.2 Functional Block Diagrams

Figure 5. TPS65400-Q1 Functional Block Diagram

TPS65400-Q1 fbd_simplified_control_SLVSCQ9.gif

A. All other switchers follow the same pattern

Figure 6. Simplified Control Block Diagram for Switcher1

8.3 Feature Description

8.3.1 Startup Timing and Power Sequencing

8.3.1.1 Startup Timing

Figure 7 shows the startup timing of the TPS65400-Q1. Upon power-up or the rising edge of CE, the internal power rails VDDA, VDDG, and VDDD startup during the time labeled t_start. Following t_start, a delay of t₁ follows (which is defined by the user through the timing of RST_N). During time t_start and t₁, the COMP terminal is internally discharged through a 1-kΩ resistor. At the rising edge of RST_N, the TPS65400-Q1 begins two actions:

The TPS65400-Q1 begins its precharge of the COMP terminal (indicated by t_precharge). The length of t_precharge needed to precharge the COMP terminal depends on the time constant of the R and C components. The internal precharge voltage source remains on even during normal operation, preventing the COMP terminal from falling below 0.6 V except during faults (OVP, OCP, and so forth).
The TPS65400-Q1 begins its configuration sequence (indicated by t_config), and loads parameters from the EEPROM. Parameters to be set include Vout, switching frequency, soft-start timing, and current limit.

After t_config is complete, t_{reset_delay} begins. The length of t_{reset_delay} is user-configurable through PMBus register DCh. After t_{reset_delay} is complete, the TPS65400-Q1 begins its startup sequence. The startup sequence is EEPROM-configurable, so any of the four switchers could be the first to startup with a configurable delay. In this particular example, SW1 is configured to startup first after a delay of t_{SW1_TON_DELAY}, which is configurable through PMBus register (DDh) TON_TOFF_DELAY.

TPS65400-Q1 tim_showing_startup_CE_SLVSCQ9.gif

A. PGOOD1 and ENSW2 are tied together externally, and t_{ON_DELAY1} and t_{ON_DELAY2} are configured through PMBus.

Figure 7. Timing Showing Startup from CE

To summarize, the length of time from rising edge of CE to soft-start of the first switcher in the sequence is:

Equation 1. t_{CE_to_SS} = t_start+ t₁ + t_config + t_{reset_delay} + t₂ + t_{SW1_ON_DELAY}

The delays, t_{reset_delay} and t_{SW1_ON_DELAY}, are both configurable through PMBus. The delay, t_config, is typically 1.1 ms. The delays, t₁ and t₂, are determined by the user-defined timing of RST_N and ENSW1. They can both be set to 0 by pulling RST_N high before the end of t_start and ENSW1 high before the end of t_{reset_delay}. One simple way to do this would be to tie both signals to VDDD.

8.3.1.2 External Sequencing

To use external sequencing, either connect all the enable pins (ENSW1, ENSW2, ENSW3, and ENSW4) to an external sequencing controller, or connect them to PGOOD outputs as shown in Figure 8. By default, t_{ON_DELAY} and t_{OFF_DELAY} are both set to 5 ms. This allows the user complete flexibility of sequencing order and timing with the ENSWx pins without modifying any of the default settings in the TPS65400-Q1.

A. Default behavior (external sequencing)

Figure 8. Example of Sequencing Where Timing is Controlled by an External Sequencer With ENSWx Pins

8.3.1.3 Internal Sequencing

The default settings for SEQUENCE_ORDER (see (D5h) SEQUENCE_ORDER) effectively disable sequencing by setting all switchers to start at the same time. Therefore, to use internal sequencing, the default values for SEQUENCE_ORDER must be changed to the desired sequence. In addition, the user can configure the start or stop sequence to have a dependence on the PGOOD output of the previous switcher, or to wait for a set delay. If configured to have a dependence on PGOOD, the soft-start for the next switcher begins after PGOOD of the previous goes high and the wait time determined by t_{ON_DELAY} is complete. If configured to wait for a set delay, the wait time determined by t_{ON_DELAY} begins immediately upon the enabling of the previous switcher.

In addition, each supply can be disabled such that it is bypassed in the power-up sequence. For example, if the sequence is SW1-SW2-SW3-SW4, and SW2 is disabled, then SW3 will be powered up after SW1. The initial configuration of the TPS65400-Q1 (for first-time power-up) needs to be done using one of the methods described in Initial Configuration.

8.3.2 UVLO and Precision Enables

The TPS65400-Q1 implements a UVLO function that prevents startup when the voltage at VIN (terminal 22) is below 4 V. In most applications, VIN and all of the power rails (PVIN1, PVIN2, PVIN3, and PVIN4) are tied to the same source and this single UVLO function is sufficient. However, in some applications, the power rails may be tied to different input voltages, and there is the possibility that the TPS65400-Q1 may attempt to startup a switcher even when its associated PVINx rail has not reached a high-enough voltage. In these cases, the precision enable threshold on each ENSWx can be used to precisely set the startup threshold for each individual switcher with a simple resistor divider to PVINx.

In cases where a single UVLO threshold is needed for all four switchers, but at a different level than 4 V, the TPS65400-Q1 can be configured for single-terminal enable (PMBus register D2h, bits 0:1 = 10) where the ENSW1/ENSEQ terminal is used as a sequence enable terminal. Then, a resistor divider to the appropriate PVINx rail can be used to set a precise UVLO threshold that applies to all four switchers.

8.3.3 Soft-Start and Prebiased Startup

The TPS65400-Q1 implements a soft-start function that minimizes discharge of the output when starting up in a prebiased condition. Soft-start time, t_SS, is set by t_{ON_TRANSITION_RATE} (digital soft-start) or by a capacitor connected to the corresponding SSx pin (analog soft-start). In this setup, the SSx pin sources a 5-µA current charging the capacitor, and the voltage at the SSx pin limits the reference voltage at the input of the error amplifier.

At the beginning of the soft-start, the soft-start input to the error amplifier is set to 0. The SSx input is raised gradually and reaches its target value during the time t_ss. If V_FB > V_SS, then no switching occurs. After the Soft-Start signal crosses VFB, the switching begins. The first switching pulse is on the low-side FET, which charges the high-side bootstrap capacitor. The unit runs in discontinuous conduction mode (DCM) with the zero-cross detector enabled on the low side (diode emulation). The high-side FET is pulsed according to the error amplifier output on the COMP pin. If the IC is configured for continuous conduction mode (CCM) operation (default), the low-side FET pulses gradually transition to normal CCM operation; at each successive switching cycle, the low-side gate pulse is gradually ramped until full synchronous switching occurs. At this point, the switcher enters normal CCM operation.

TPS65400-Q1 tim_softstart_CCM_LVSCQ9.gif

Figure 9. Soft-Start Under Prebiased Condition and CCM Mode Programmed

TPS65400-Q1 tim_softstart_DCM_LVSCQ9.gif

Figure 10. Soft-Start Under Prebiased Condition and DCM Mode Programmed

8.3.3.1 Analog Soft-Start (Default) and Digital Soft-Start

The TPS65400-Q1 has the ability to use an analog-based soft-start ramp based on external capacitors (one input for each switcher) or to use internal signals based on digital logics and DACs to perform the soft-start function.

When using external soft-start configuration (default configuration), the SSx pins are connected to the soft-start input of the error amplifier.

When using the internal digital soft-start signal, the soft-start input to the error amplifier increases step-by-step at a rate set according to the value set in TON_RAMP_RATE (see (DEh) TON_TRANSITION_RATE).

TPS65400-Q1 internal_ss_input_to_ea_SLVSCQ9.gif

Figure 11. Internal Soft-Start Input to Error Amplifier When Digital Soft-Start is Selected

ΔVSS_step is 10 mV. Tss_step depends on the soft-start time option selected. See (DEh) TON_TRANSITION_RATE for more details.

8.3.3.2 Soft-Start Capacitor Selection

When using external soft-start capacitor to set the soft-start time, use Equation 2.

Equation 2. TPS65400-Q1 eq_1_tss_LVSCQ9.gif

Css is the value of the capacitor connected between the SSx pin and AGND. VREF is the value of the reference voltage (default is 0.8 V). I_SS is the current sourced by the SS1/PG1 pin during soft-start.

8.3.4 PWM Switching Frequency Selection

The master clock frequency, F_OSC, can be set by external resistor on the RCLOCK_SYNC terminal, or by synchronizing with an external clock. To set using an external resistor, use this formula.

Equation 3. F_SW (kHz) = 138664 R_OSC (kΩ)^–0.948

Figure 12. Frequency vs R_osc

To sync to an external source, an AC-coupled signal should be applied to the terminal. A fixed resistor should still be connected to set a minimum frequency. The frequency of the input signal to synchronize with should always be higher than the minimum frequency. If the internal PLL cannot synchronize, the switchers will fall back to the minimum frequency set by the resistor. The CLK_OUT terminal outputs the master clock F_OSC.

The PWM frequency of each switcher is determined by this master clock frequency and an I²C-programmable choice of 4 divider ratios (1, 2, 4, or 8) by setting CLK_DIV (see (D7h) FREQUENCY_PHASE).

TPS65400-Q1 tim_pwm_clock_gen_SLVSCQ9.gif

A. The frequency modulator is used for external clock synchronization.

Figure 13. Diagram of PWM Clock Generation

The intent of the individual divider ratios is to allow users to set the frequency of each switcher independently. For example, with a master clock F_OSC of 1.1 MHz, SW1 and SW2 have a divider ratio of 4 for a 275-kHz PWM, and SW3 and SW4 have a divider ratio of 1 for a PWM frequency of 1.1 MHz. Select the divider ratio so that the PWM frequency stays within the range of 275 kHz to 2.2 MHz for whichever master clock frequency is set.

In addition to selecting the frequency, each switcher can have its PWM frequency delayed. This enables the designer to minimize ripple current by properly selecting the delays so that the switching frequencies are out of phase. The default switching frequency is at CLK_DIV = F_OSC / 1 with PHASE_DELAY for SW1 at 0˚, SW2 at 180˚, SW3 at 90˚, and SW4 at 270˚. More information on frequency selection and delay is given in (D7h) FREQUENCY_PHASE.

8.3.5 Clock Synchronization

The RCLOCK_SYNC terminal can be used to synchronize the master clock switching frequency, F_OSC, with an external clock source or another TPS65400-Q1. The external clock signal (which can come from another TPS65400-Q1 CLK_OUT terminal) should be AC coupled to the RCLOCK_SYNC terminal as shown in Figure 14. Choose the ROSC value so that the fixed frequency is nominally 30% lower than the external synchronizing clock frequency. An internal protection diode clamps the low level of the synchronizing signal to approximately –0.5 V. The internal clock synchronizes to the rising edge of the external clock.

TPS65400-Q1 AC_coupled_clk_sync_SVLSCQ9.gif

Figure 14. AC-Coupled Clock Synchronization

TI recommends to choose an AC-coupling capacitance in the range of 50 to 100 pF. Exceeding the recommended capacitance may inject excessive energy through the internal clamping diode structure present on the RCLOCK_SYNC terminal. The typical trip level of the synchronization terminal is 1.5 V. To ensure proper synchronization and to avoid damaging the IC, the peak-to-peak value (amplitude) should be between 2.5 V and V_DDA. The minimum duration of this pulse must be greater than 200 ns, and its maximum duration must be 200 ns less than the period of the switching cycle.

The external clock synchronization process begins after the TPS65400-Q1 is enabled and an external clock signal is detected. The frequency modulator adjusts the oscillator frequency to match the frequency of the pulses into the RCLOCK_SYNC terminal. It generally takes 50 cycles before the PWM frequency locks. If the external clock signal is removed after frequency synchronization, the master clock F_OSC drifts to the frequency selected by ROSC.

8.3.6 Phase Interleaving

The TPS65400-Q1 offers the ability to output rails of higher currents by connecting SW1 and SW2 in parallel, or by connecting SW3 and SW4 in parallel. To configure this option, the COMP2 or COMP4 terminal must be tied to VDDA through a 4-kΩ resistor.

Upon the initialization sequence after a reset, the TPS65400-Q1 attempts to discharge the COMP terminal through a 2-kΩ internal resistor. When it detects that the COMP terminal is pulled high, it configures itself to operate in current sharing mode. If SW2 is set to current sharing mode, its PWM output is controlled by the error amplifier and COMP1 terminal of SW1 and set to the same frequency as SW1. Likewise, if SW4 is set to current sharing mode, its PWM output is controlled by the error amplifier and COMP3 terminal of SW3 and set to the same frequency as SW3. This means that the frequency settings for SW2 and SW4 in the EEPROM are ignored in that mode of operation.

When current sharing mode is detected on a particular pair, the output slave’s I²C access is invalid and the output slave’s default settings follow that of its master (see (00h) PAGE). The only exception is that the slave switcher PWM is a fixed 180° phase-shift from its master.

Table 1. Programmable Options When Current Sharing Enabled

Pair	Output	Current Sharing Relationship	Switching Frequency	Switching Phase
SW1-SW2	SW1	Master	Programmable	Programmable
SW1-SW2	SW2	Slave	Follows master	Master + 180°
SW3-SW4	SW3	Master	Programmable	Programmable
SW3-SW4	SW4	Slave	Follows master	Master + 180°

8.3.7 Fault Handling

OVP, OCP, and undervoltage protection (UVP) are handled for each switcher independently. OVP or OCP faults that occur on one switcher do not affect the other outputs. There are two exceptions:

If current-sharing mode (ISHARE) is detected for a switcher that faults, both switchers in parallel have the same response to OVP or OCP.
When using internal sequencing, in the case of faults occurring during the initial power-up sequence, all switchers are disabled for 500 ms, after which, the startup sequence is restarted.

During the soft-start time for a switcher, all fault signals (OVP, OCP, and UVP) are disabled and reset to the unfaulted condition. The first moment when faults can be triggered is after the end of the soft-start sequence.

OVP thresholds are set as a percentage of VREF. A deglitching time of 50 μs is used for the overvoltage. When an overvoltage occurs at the OVP upper threshold limit, the high-side FET and the low-side FET are disabled for that switcher until the OVP falling threshold is reached. When the OVP falling threshold is reached, the low-side FET turns on for 200 ns to ensure that the bootstrap capacitor is recharged before resuming normal operation of the converter.

Output voltage falling below the UVP thresholds causes the corresponding PGOOD output to fall, but the switcher continues to operate as it tries to increase the output voltage. However, if the PGOOD terminal is tied to the enable ENSWx signal of another switcher on the PCB (for external sequencing), the output for that ENSWx-PGOOD-tied switcher is disabled until output voltage is nominal and PGOOD is good.

OTP shuts down all switchers. When the temperature drops below the hysteresis level, a soft reset is triggered and the chip restarts from the startup sequence.

Fault Monitoring describes fault reporting and clearing of fault status registers.

The OVP and UVP sensing is deglitched to prevent unwanted tripping. The faults need to be sustained for more than 55 μs typically (60 μs max) to be registered and trigger protection circuits and PGOOD output to fall. Fault detection is disabled on a given switcher when its VREF is being ramped (as result of an I²C command to change VREF). An additional 100-μs fault blanking time results after VREF has been adjusted to its target level.

8.3.8 OCP for SW1 to SW4

The OCP is I²C-programmable and set by the IOUT_MAX command. By default, the peak current IOUT_MAX for SW1 and SW2 is 6 A, and for SW3 and SW4 it is 3 A. When the current reaches this threshold, the unit immediately turns off the high-side FET and keeps the low-side FET off for the remainder of the switching cycle. The following cycle are skipped (high-side FET off, low-side FET off) regardless of the inductor current. If the current in the inductor is still higher than the IOUT_MAX after the skipped cycle, the following cycles are also skipped until the current reach below the IOUT_MAX.

If the IOUT_MAX is reached more than 256 active cycles continuously, the switcher shut downs for 20 ms and restarts. If the switcher is running in interleaved operation, both the switcher that tripped the IOUT_MAX threshold and its interleaved counterpart shut down for 20 ms. After that period of time, the unit restarts and goes through soft-start operation. For very-low duty cycle operation and faulty operation with very-fast current increase during the high-side FET on-time (due to inductor saturation and so forth), OCP is also enforced on the low side to ensure no runaway condition exists.

Table 2. Current Limit Options

SWITCHER	IOUT_MAX
SW1, SW2	2 A
	3 A
	4 A
	5 A
	6 A (default)
SW3, SW4	0.5 A
	1 A
	2 A
	3 A (default)

While the converter is shut down following an OCP event spanning more than 256 cycles, the COMP terminal is pulled low for 1.1 ms prior to precharge and re-enabling of the converter. At the same time, the SSx pin is discharged to AGND for 1.1 ms. If the soft-start is digital (SSx pins used as PGOODx outputs), the soft-start value is reset.

Figure 15. Inductor Current During Overcurrent Event

At high switching frequency (>1 MHz) and particularly when there is a fault in the converter such as saturation of the inductor, the current sensor might not sense the overcurrent event. To ensure that current protection is provided in all operating scenarios, low-side current sensing is also present to provide overcurrent detection and protection when the low-side FET is on. If over-current is detected when the low-side FET is on, the low-side FET stays on (and the high-side FET off) until the current drops below the threshold. A new cycle will then begin (high side on, low side off) when the next switching cycle occurs as driven by the internal clock derived from the oscillator (internal or external synchronization). A dedicated counter records the low-side OCP events and initiates a shutdown of the converter after 256 OCP event counts. Six consecutive cycles without a low-side OCP event resets the counter.

TPS65400-Q1 ind_curr_OC_low_side_LVSCQ9.gif

Figure 16. Inductor Current During Overcurrent Event With Low-Side Detection

8.3.9 Overcurrent Protection for SW1 to SW4 in Current Sharing Operation

When the converter is running in interleaved operation, an OCP event will not trigger the COMP terminal to be pulled low to 0.6 V. Instead, the error amplifier is switched off (tri-stated). This ensures that the COMP terminal voltage remains constant so that the other phase continues to operate during the OCP event. An OCP event on one switcher lasting more than 256 cycles triggers the shutdown of both switchers running in interleaved mode.

8.3.10 Recovery on Power Loss

All contents of the registers are saved and stored in the data store (non-volatile memory) with the exceptions listed in Table 4 (Supported PMBus Commands) when STORE_DEFAULT_ALL is issued. Contents of the registers are copied from the data store when power is restored. This allows the system processor to turn on the power supplies as needed with the same default settings before power was lost.

8.3.11 Feedback Compensation

Figure 17. Simplified Equivalent Feedback Compensation Network

A typical compensation circuit could be type II (R_C and C_C) to have a phase margin between 60° and 90°, or type III (R_C, C_C, and C_ff) to improve the converter transient response. C_Roll adds a high-frequency pole to attenuate high-frequency noise when needed. C_Roll should be set to at least twice the crossover frequency to avoid interacting with the feedback compensation. It may also prevent noise coupling from other rails if there is possibility of cross coupling in between rails when layout is very compact.

Table 3 shows the recommended values for the compensation network components as an initial start. These result in the compensating zero of the Type II to match the dominant pole of the converter.

Table 3. Compensation Calculation Table

	TYPE II	TYPE III
Select cross over frequency to be less than 1/5 of switching frequency (typical is 1/10)
Set R_C
Set C_C
Add C_Roll if needed to remove large signal coupling to high impedance COMP node.
C_ff compensating capacitor for type III compensation network. Choose ƒz_ff same as F_C.	N/A

8.3.12 Adjusting Output Voltage

The output voltage of each buck is set with a resistor divider from BUCK output to FB pin and ground. TI recommends to use a 1% tolerance resistor or better one to get higher output voltage accuracy.

Figure 18.

With RFB1 and RFB2, output voltage is determined by:

Equation 4. TPS65400-Q1 eq_8_Vout_LVSCQ9.gif

Default Vref in TPS65400-Q1 is 0.8 V. It can be programed from 0.6 to 1.87 V by digital interface PMBus. See (D8h) VREF_COMMAND for more detailed information.

8.3.13 Digital Interface – PMBus

TPS65400-Q1 implements a PMBus-compatible I²C digital interface. The PMBus specification referenced by this section is PMBus Power System Management Protocol Specification Part I – General Requirements, Transport and Electrical Interface, Revision 1.2, dated 6 September 2010. The specification is published by the Power Management Bus Implementers Forum and is available from http://pmbus.org/Specifications. See details in PMBus and Register Maps.

8.3.14 Initial Configuration

The recommended method of configuring the TPS65400-Q1 the first time is through an external programmer through a separate I²C programming header (as shown in Figure 19). The programming header needs to connect to the SCL, SDA, CE, VDDD, and DGND lines, and can be done using a USB-to-I²C tool. This enables the user to tailor the settings of the TPS65400-Q1 for each PCB specifically after PCB assembly, before the first power-up of the board.

An alternative method is to use the firmware in an on-board microcontroller to do the initial configuration. To do this, the user has two options:

Power the microcontroller and the TPS65400-Q1 (VDDD, CE, and DGND connections needed) from an external source not controlled by the TPS65400-Q1.
Design the PCB so that the default settings of the TPS65400-Q1 allow the microcontroller to be powered when power is applied to the TPS65400-Q1 the first time. The designer also needs to ensure that the default power-up sequence, ramp-rates, and other default parameters do not damage any components when power is applied the first time. After configuration, the microcontroller should pull CE low, and then all future power-ups result in the newly configured power-up scheme to occur.

Using either method for the microcontroller requires the firmware to check if the TPS65400-Q1 has been previously configured, or if a modification needs to be made to an already programmed configuration. Users may use USER_DATA_BYTE_00 and/or USER_DATA_BYTE_01 to store a version number to identify which version of the configuration is stored in the TPS65400-Q1.

A hybrid option may also be done where the initial configuration is done using an external programmer, and the subsequent revisions are done through the microcontroller firmware. This eliminates the risk from damage caused by the default configuration during the first power-up, but still allows the microcontroller firmware to modify settings such as the VREF settings for subsequent power-ups.

TPS65400-Q1 tim_int_seq_ON_OFF_LVSCQ9.gif

A. Configuration:

Enable pins ENSWx set to inactive in PIN_CONFIG_00
Start sequence order SW1-SW2-SW3-SW4 in SEQUENCE_ORDER
Stop sequence order SW4-SW3-SW2-SW1 in SEQUENCE_ORDER

Figure 19. Example of Internal On Sequencing and Off Sequencing With the Default START_PGOOD Dependence

OPERATION (SWx) refers to OPERATION register in the corresponding PMBus PAGE. See (01h) OPERATION for more information on the OPERATION register.

TPS65400-Q1 sch_int_seq_w_host_LVSCQ2.gif

Figure 20. Internal Sequencing Schematic With Host

TPS65400-Q1 sch_int_seq_wo_host_LVSCQ2.gif

Figure 21. Internal Sequencing Schematic Without Host

8.4 Device Functional Modes

8.4.1 CCM Operation Mode

When the VIN/PVINx are above UVLO threshold and ENSWx are above the threshold, all four switchers operate in continuous current mode(CCM) with IOUT_MODE(see (D6h) IOUT_MODE) setting default. In CCM, the converters work in peak current mode for easy loop compensation and cycle-by-cycle high side MOSFET current limit.

8.4.2 CCM/DCM Operation Mode

When DCM mode is enabled by setting IOUT_MODE (see (D6h) IOUT_MODE), the switchers transition to DCM operation at light loads. During DCM mode, the low-side FET is turned off to prevent negative inductor current. This increases light-load efficiency, but output ripple and transient response during DCM or during transitions between DCM and CCM mode can be degraded.

At light load, the COMP terminal is driven by the error amplifier to the minimum clamp voltage. When the COMP voltage reaches below 0.6 V and the error amplifier is sinking more than 5 μA, both the high-side and low-side FET will be tri-stated to prevent the output voltage from rising above the set value. The FET function is re-enabled when the GM amplifier sinks less than 3 μA. This results in a burst mode operation at light load. The low-side FET has a 200-ns one-shot ON-time to ensure that the bootstrap capacitor is charged before the normal function of the converter is resumed.

8.4.3 Current Sharing Mode

When SW1/SW2 pair output and/or SW3/SW4 pair output are shared, the responding pairs current sharing mode is enabled and the ENABLE_PIN_CONFIG is set to single ENABLE. For the detail configuration, see Current Sharing Typical Application.

8.5 Register Maps

Table 4 lists the PMBus commands. Commands 00h through CFh are defined in the PMBus Specification and are considered to be core commands that are standardized for all manufacturers and products. Commands D0h through FEh are manufacturer-specific and may be unique for each manufacturer and product. Commands that are not supported by the device are not listed.

Table 4. Supported PMBus Commands

Code	Name	SMBUS Transaction Type: Writing Data	SMBUS Transaction Type: Reading Data	Data Bytes	PAGE Support	Saved to Data Flash	Description
00h	PAGE	Write byte	Read byte	1	—	No	Selects output rail (see (00h) PAGE)
01h	OPERATION	Write byte	Read byte	1	00-03, FF	No	Starts or stops output (see (01h) OPERATION)
03h	CLEAR_FAULTS	Send byte	—	0	00-03, FF	—	Clears all faults (see (03h) CLEAR_FAULTS)
10h	WRITE_PROTECT	Write byte	Read byte	1	—	No	Used to lock bus writes (see (10h) WRITE_PROTECT)
11h	STORE_DEFAULT_ALL	Send byte	—	0	—	—	Stores operating memory to default store (see (11h) STORE_DEFAULT_ALL)
19h	CAPABILITY	—	Read byte	1	—	—	Describes PMBUS capabilities (see (19h) CAPABILITY)
78h	STATUS_BYTE	—	Read byte	1	00-03, FF	—	Fault register (see (78h) STATUS_BYTE)
79h	STATUS_WORD	—	Read word	2	00-03, FF	—	Fault register (see (79h) STATUS_WORD)
7Ah	STATUS_VOUT	—	Read byte	1	00-03, FF	—	Output fault register (see (7Ah) STATUS_VOUT)
80h	STATUS_MFR_SPECIFIC	—	Read byte	1	—	—	Status register (PGOOD#_N) (see (80h) STATUS_MFR_SPECIFIC)
98h	PMBUS_REVISION	—	Read byte	1	—	—	PMBUS revision support (see (98h) PMBUS_REVISION)
ADh	IC_DEVICE_ID	—	Read block	7	—	—	IC part number in ASCII (see (ADh) IC_DEVICE_ID)
AEh	IC_DEVICE_REV	—	Read block	2	—	—	IC part revision code (see (AEh) IC_DEVICE_REV)
D0h	USER_DATA_BYTE_00	Write byte	Read byte	1	—	Yes	User-defined data (see (D0h) USER_DATA_BYTE_00)
D1h	USER_DATA_BYTE_01	Write byte	Read byte	1	—	Yes	User-defined data (see (D1h) USER_DATA_BYTE_01)
D2h	PIN_CONFIG_00	Write byte	Read byte	1	—	Yes	Configures pin behavior (see (D2h) PIN_CONFIG_00)
D3h	PIN_CONFIG_01	Write byte	Read byte	1	00-03	Yes	Configures rail-specific pin behavior (see (D3h) PIN_CONFIG_01)
D4h	SEQUENCE_CONFIG	Write byte	Read byte	1	—	Yes	Configures sequence behavior (see (D4h) SEQUENCE_CONFIG)
D5h	SEQUENCE_ORDER	Write byte	Read byte	1	00-03	Yes	Configures sequence order (see (D5h) SEQUENCE_ORDER)
D6h	IOUT_MODE	Write byte	Read byte	1	00-03	Yes	Sets CCM / DCM, current sharing status (see (D6h) IOUT_MODE)
D7h	FREQUENCY_PHASE	Write byte	Read byte	1	00-03	Yes	Sets switcher frequency and phase (see (D7h) FREQUENCY_PHASE)
D8h	VREF_COMMAND	Write byte	Read byte	1	00-03	Yes	Sets reference voltage (V_REF) (see (D8h) VREF_COMMAND)
D9h	IOUT_MAX	Write byte	Read byte	1	00-03	Yes	Sets current limit (see (D9h) IOUT_MAX)
DAh	USER_RAM_00	Write byte	Read byte	1	—	No	RESET notification (see (DAh) USER_RAM_00)
DBh	SOFT_RESET	Send byte	—	0	—	—	Soft resets device (see (DBh) SOFT_RESET)
DCh	RESET_DELAY	Write byte	Read byte	1	—	Yes	Sets delay after reset (see (DCh) RESET_DELAY)
DDh	TON_TOFF_DELAY	Write byte	Read byte	1	00-03	Yes	Sets delay before output begins to turn ON/OFF (see (DDh) TON_TOFF_DELAY)
DEh	TON_TRANSITION_RATE	Write byte	Read byte	1	00-03	Yes	Sets soft-start time (see (DEh) TON_TRANSITION_RATE)
DFh	VREF_TRANSITION_RATE	Write byte	Read byte	1	00-03	Yes	Sets ramping parameters for real-time Vref settings in output (see (DFh) VREF_TRANSITION_RATE)
E0h-EFh	—	—	—	—	—	—	Reserved
F0h	SLOPE_COMPENSATION	Write byte	Read byte	1	00-03	Yes	Adjusts control loop compensation (see (F0h) SLOPE_COMPENSATION)
F1h	ISENSE_GAIN	Write byte	Read byte	1	00-03	Yes	Adjusts control loop current sense (see (F1h) ISENSE_GAIN)
FCh	DEVICE_CODE	—	Read word	2	—	—	IC part revision code (see (FCh) DEVICE_CODE)

Table 5. Command Bit-Mapping

Code	Name	Default Value		Byte	Bits
Code	Name	Default Value		Byte	7 (MSB)	6	5	4	3	2	1	0 (LSB)
00h	PAGE	0xFF		0	PAGE
01h	OPERATION	0x80		0	OPERATION				x	x	x	x
03h	CLEAR_FAULTS				—
10h	WRITE_PROTECT	0x40		0	WRITE_PROTECT
11h	STORE_DEFAULT_ALL				—
19h	CAPABILITY	0xA0		0	PEC	BUS		SMB_ALERT	x	x	x	x
78h	STATUS_BYTE	0b0XXXX0XX		0	x	OFF	VOUT_OV	IOUT_OC	TEMPERATURE	x	CML	NONE OF THE ABOVE
79h	STATUS_WORD	0b0XXXX0XX		0	x	OFF	VOUT_OV	IOUT_OC	TEMPERATURE	x	CML	NONE OF THE ABOVE
79h	STATUS_WORD	0bX00XX000		1	VOUT	x	x	MFR	POWER_GOOD_N	x	x	x
7Ah	STATUS_VOUT	0bX00X0000		0	VOUT_OV	x	x	VOUT_UV	x	x	x	x
80h	STATUS_MFR_SPECIFIC	0b0000XXXX		1	x	x	x	x	POWER_GOOD4_N	POWER_GOOD3_N	POWER_GOOD2_N	POWER_GOOD1_N
98h	PMBUS_REVISION	0x22		0	Part I Revision				Part II Revision
ADh	IC_DEVICE_ID	0x07		0	Length
		0x4C		1	‘L’
		0x4D		2	‘M’
		0x32		3	‘2’
		0x36		4	‘6’
		0x34		5	‘4’
		0x33		6	‘3’
		0x30		7	‘0’
AEh	IC_DEVICE_REV	0x02		0	Length
		0xFX		1	DEVICE_CODE_ID				DEVICE_CODE_REV
		0x00		2	DEVICE_CODE_ID
D0h	USER_DATA_BYTE_00	0x00		0	USER_DATA_BYTE_00
D1h	USER_DATA_BYTE_01	0x00		0	USER_DATA_BYTE_01
D2h	PIN_CONFIG_00	0x3C		0	x	PGOOD_PIN_CONFIG					ENABLE_PIN_CONFIG
D3h	PIN_CONFIG_01	0x00		0	x	x	x	x	x	x	x	SSPG_PIN_CONFIG
D4h	SEQUENCE_CONFIG	0x00		0	x	x	x	x	x	x	x	START_PGOOD
D5h	SEQUENCE_ORDER	0x00		0	x	x	x	x	STOP_ORDER		START_ORDER
D6h	IOUT_MODE	0b000000X1		0	x	x	x	x	x	x	IOUT_SHARE	CCM
D7h	FREQUENCY_PHASE	PAGE	Val	0	x	PHASE_DELAY					CLK_DIV
		0x00	0x00
		0x01	0x08
		0x02	0x04
		0x03	0x0C
D8h	VREF_COMMAND	0x14		0	x	VREF_COMMAND
D9h	IOUT_MAX	PAGE	Val	0	x	x	x	x	x	IOUT_MAX
		0x00	0x04
		0x01	0x04
		0x02	0x03
		0x03	0x03
DAh	USER_RAM_00	0x00		0	x	x	x	x	x	x	x	USER_RAM_00
DBh	SOFT_RESET			—
DCh	RESET_DELAY	0x00		0	x	x	x	x	x	RESET_DELAY
DDh	TON_TOFF_DELAY	0x01		0	x	x	TON_DELAY			TOFF_DELAY
DEh	TON_TRANSITION_RATE	0x02		0	x	x	x	x	x	x	TON_RAMP_RATE
DFh	VREF_TRANSITION_RATE	0x98		0	VREF_RAMP_ENABLE	x	VREF_RAMP_TIMESTEP			VREF_RAMP_BITSTEP
F0h	SLOPE_COMPENSATION	0x01		0	x	x	x	x	x	x	SLOPE_COMPENSATION
F1h	ISENSE_GAIN	0x01		0	x	x	x	x	x	x	ISENSE_GAIN
FCh	DEVICE_CODE	0xFX		0	DEVICE_CODE_ID				DEVICE_CODE_REV
FCh	DEVICE_CODE	0x00		1	DEVICE_CODE_ID

8.5.1 PMBus

8.5.1.1 Overview

The TPS65400-Q1 implements a lightweight PMBus-compliant layer supporting packet error checking, high-speed bus, and group commands.

8.5.1.2 PMBus Protocol

The PMBus specification follows SMBus version 2.0. Figure 22 through Figure 29 show all supported command transactions.

8.5.1.2.1 PMBus Protocol

Figure 22. Send Byte Protocol With PEC

1	7	1	1	8	1	8	1	1
Start	Slave address	Wr	Ack	Command code	Ack	PEC	Ack	Stop

Figure 23. Write Byte Protocol With PEC

1	7	1	1	8	1	8	1	8	1	1
Start	Slave address	Wr	Ack	Command code	Ack	Data byte	Ack	PEC	Ack	Stop

Figure 24. Read Byte Protocol With PEC

1	7	1	1	8	1	1
Start	Slave address	Wr	Ack	Command code	Ack	Restart

7	1	1	8	1	8	1	1
Slave address	Rd	Ack	Data byte	Ack	PEC	Nack	Stop

Figure 25. Read Word Protocol With PEC

1	7	1	1	8	1	1	7	1	1
Start	Slave address	Wr	Ack	Command code	Ack	Restart	Slave address	Rd	Ack

8	1	8	1	8	1	1
Data word (low)	Ack	Data word (high)	Ack	PEC	Nack	Stop

8.5.1.2.2 Transactions (No PEC)

Figure 26. Send Byte Protocol

1	7	1	1	8	1	1
Start	Slave address	Wr	Ack	Command code	Ack	Stop

Figure 27. Write Byte Protocol

1	7	1	1	8	1	8	1	1
Start	Slave address	Wr	Ack	Command code	Ack	Data byte	Ack	Stop

Figure 28. Read Byte Protocol

1	7	1	1	8	1	1
Start	Slave address	Wr	Ack	Command code	Ack	Restart

7	1	1	8	1	1
Slave address	Rd	Ack	Data byte	Nack	Stop

Figure 29. Read Word Protocol

1	7	1	1	8	1	8	7	1	1
Start	Slave address	Wr	Ack	Command code	Ack	Restart	Slave address	Rd	Ack

8	1	8	1	1
Data word (low)	Ack	Data word (high)	Nack	Stop

8.5.1.2.3 Addressing

The 7-bit I²C address is set through the I2CADDR terminal with a resistor RADDR connected to AGND. Table 6 shows the connection between the voltage at the I2CADDR terminal and the set I²C address at V_DDD = 3 V. The I²C address is determined only upon startup during t_{RESET_DELAY} after rising edge of CE or RST_N. This makes it immune to noise that may occur during normal operation. TI recommends resistors with 5% or lower tolerance. If I²C is not necessary in the application, TI recommends to tie the I2CADDR terminal directly to VDDD.

Table 6. I²C Address Selection

R_ADDR	7-bit Address
180 kΩ	1101 111
120 kΩ	1101 110
82 kΩ	1101 101
56 kΩ	1101 100
39 kΩ	1101 011
22 kΩ	1101 010
10 kΩ	1101 001
2 kΩ	Test mode (factory-use only)

8.5.1.2.4 Startup

After CE is asserted and V_DDD has reached 3.3 V, there is approximately a 320 μs delay before the PMBus interface is active. During this time the TPS65400-Q1 is restoring its configuration from the EEPROM.

8.5.1.2.5 Bus Speed

100- and 400-kHz bus speeds are supported.

8.5.1.2.6 I2CALERT Terminal

When a timeout condition occurs, the I2CALERT terminal is pulsed low for 200 μs. A timeout condition is defined as per SMBUS 2.0, t_TIMEOUT. In addition to SCL, a timeout condition also occurs when the SDA line is asserted low. If the timeout condition persists, I2CALERT continues to pulse every t_TIMEOUT. The TPS65400-Q1 never intentionally pulls the SCL low beyond t_LOW:SEXT

(1) t_LOW:SEXT: Cumulative clock low extend time (slave device). See more details on SMBus specification http://smbus.org/specs/.

, as that violates timing specifications. Therefore, the I2CALERT terminal acts as a watchdog for other devices sharing the same bus that violate the cumulative clock low extend time. On a system level, it can be seen as a non-maskable interrupt (NMI) signal for the I²C bus.

Table 7. Timeout Specifications

PARAMETER		MIN	MAX	UNIT
t_TIMEOUT:SCL	Detect clock low timeout	25	35	ms
t_TIMEOUT:SDA	Detect data low timeout	25	35	ms

8.5.1.2.7 CONTROL Terminal

The TPS65400-Q1 enable terminals ENSWx are equivalent to the CONTROL terminals in the fault handling. The enable terminals behave as follows:

Unit does not power up until commanded by the enable terminal and OPERATION command. By default, the OPERATION command is ON, so the powering up of the unit depends on the enable terminal state.
To start, the unit requires that the on/off portion of the OPERATION command is instructing the unit to run. Depending on PIN_CONFIG_00, the unit may also require the enable terminal to be asserted for the unit to start and energize the output.
Polarity of the enable terminal is active high. If unconnected, the terminal goes high.
When commanding the unit to turn on or off through the enable terminals, the programmed turn on delays, turn off delays are always observed.

There are differences in enable terminal functionality depending on terminal configuration PIN_CONFIG_00. For more information, refer to OPERATION and PIN_CONFIG_00.

8.5.1.2.8 Packet Error Checking

The TPS65400-Q1 supports an optional PEC code to be validated at the end of every write and to be appended to the end of every read. TI highly recommends it, but it is not required.

8.5.1.2.9 Group Commands

Fully-compliant group commands are supported.

8.5.1.2.10 Unsupported Features

All undocumented, optional features are not supported. Extended commands are not supported.

8.5.2 PMBus Register Descriptions

The PMBus specification referenced by this section is PMBus Power System Management Protocol Specification Part II – Command Language, Revision 1.2, dated 6 September 2010. The specification is published by the Power Management Bus Implementers Forum and is available from http://pmbus.org/specifications.

8.5.2.1 Overview

The following parameters can be programmed and read. These are individually available for each power supply output (SW1-SW4):

Voltage reference
Start sequencing
Stop sequencing
Switching frequency
Switching phase
Soft-start time
Current limit
Current sharing operation with SW1-SW2 and/or SW3-SW4 pairs
Power Good
Fault status

Each power supply has its own set of PMBus commands. Paging is supported to allow device selection for a PMBus session ((00h) PAGE). Table 4 lists supported PMBus commands and paging values.

8.5.2.2 Memory Model

Supported PMBus Commands describes the memory model for PMBus devices. Values used by the PMBus device are loaded into volatile operating memory from the following places:

Values hard-coded into an IC design
Values programmed from hardware terminals
A non-volatile memory called the default store
Communications from the PMBus

On-board data flash memory is used to implement the hard-coded values and the default store values. Values in the default store may be changed using the STORE_DEFAULT_ALL command described in (11h) STORE_DEFAULT_ALL. The user store is not supported. Table 4 describes the ordering of memory loading and precedence. In general, the hard-coded parameters are loaded into operating memory first. Second, any terminal-programmable settings take effect. Third, values from the default store are loaded. Later, commands issued from the PMBus take effect. In all cases, an operation on a parameter overwrites any prior value that was already in the operating memory.

Figure 30. Memory Model

8.5.2.3 Data Formats

Data is sent as a byte, an 8-bit binary value, a word, a 16-bit binary value, or a block of bytes whose length is specified by a length byte.

8.5.2.4 Fault Monitoring

Registers (78h) STATUS_BYTE, (79h) STATUS_WORD, (7Ah) STATUS_VOUT of the PMBus specification describe fault monitoring for PMBus devices. The TPS65400-Q1 only supports reporting faults. Fault conditions are set in the corresponding status register and the host or power system manager can poll it. Any bits set in the status register remain set even if the fault condition is removed or corrected. The fault bits in the status register remain set until one of the following occur:

The device receives a CLEAR_FAULTS command.
A RESET signal is asserted by either issuing a SOFT_RESET or by asserting/deasserting the CE terminal.
Bias power is removed from the PMBus device.

Fault Handling describes fault thresholds and specific response behaviors.

8.5.3 PMBus Core Commands

These PMBus core commands are defined in the PMBus Specification. This section describes details that are unique to the TPS65400-Q1 implementation.

8.5.3.1 (00h) PAGE

The PAGE command provides the ability to configure, control, and monitor multiple outputs on a single TPS65400-Q1 using a single PMBus physical address. All subsequent commands that depend on PAGE are applied to the rail selected by the PAGE command.

Rails are numbered starting with one, while pages are numbered starting at 0. Table 8 shows the relationship between the PMBus PAGE value and the rail number.

Table 8. PAGE Data Byte Contents

BITS	NAME	READ / WRITE	DEFAULT VALUE	VALUE	OUTPUT RAIL	PAIRING	CURRENT SHARING RELATIONSHIP
7:0	PAGE	R/W	0xFF	0x00	SW1	SW1-SW2	Master
				0x01	SW2	SW1-SW2	Slave
				0x02	SW3	SW3-SW4	Master
				0x03	SW4	SW3-SW4	Slave
				0x04 to 0xFE	Invalid	—	—
				0xFF	All	—	—

On the TPS65400-Q1, current share is organized in pairs (PAGE = 0x00, 0x01 and PAGE = 0x02, 0x03). When current sharing mode is detected on a particular pair, the slave PAGE is invalid and the slave’s default settings follow that of its master PAGE. The only exception is that the slave switcher PWM will be a fixed 180° phase-shift from its master (see (D7h) FREQUENCY_PHASE). Additionally, the ISHARE bit will be asserted (see (D6h) IOUT_MODE).

(00h) PAGE of the register map describes the PAGE command in more detail.

NOTE

The PAGE parameter is not stored in the default store in data flash.

8.5.3.2 (01h) OPERATION

The OPERATION command in conjunction with input from the enable pins ENSWx is used to turn on or off (enable or disable) the currently selected switching regulator as determined by the current PAGE. Margins are not supported. Data byte contents are given in Table 9.

Table 9. Operation Data Byte Contents

PAGE SUPPORT	BITS [7:6]	BITS [5:4]	BITS [3:2]	BITS [1:0]	SEQUENCING	OUTPUT ON OR OFF	DELAY
0x00 to 0x03, 0xFF	00	XX	XX	XX	No	Immediate off	None
0x00 to 0x03	01	XX	XX	XX	No	Soft off	t_{OFF_DELAY}
0xFF	01	XX	XX	XX	Yes	Soft off	t_{OFF_DELAY}
0x00 to 0x03	10	00	XX	XX	No	On with soft-start (default)	t_{ON_DELAY}
0xFF	10	00	XX	XX	Yes	On with soft-start (default⁽¹⁾)	t_{ON_DELAY}

(1) This is also the default behavior upon reset with active ENABLE selected (see (D2h) PIN_CONFIG_00)

Input from the enable pin overrides the off state of the corresponding output. The pin function configuration command PIN_CONFIG_00 can accept or ignore enable pins as well as disable OPERATION sequencing command support (see (01h) OPERATION). If the OPERATION state is on, and PIN_CONFIG_00 is set to accept enable pins, action from enable pins would result in a delay specified by TON_TOFF_DELAY. Figure 31 shows how the on/off states are triggered.

Figure 31. On/Off Configuration (Per Output)

When a fault occurs, the output state will turn OFF and possibly attempt to turn ON repeatedly for persistent faults. Specific fault response behaviors are described in Fault Handling.

NOTE

TI recommends that if OPERATION is to be used exclusively, all outputs should be set to the same order and enable pins should be ignored (see (D5h) SEQUENCE_ORDER, and (D2h) PIN_CONFIG_00).

The OPERATION parameter is not stored in the default store in data flash.

8.5.3.3 (03h) CLEAR_FAULTS

The CLEAR_FAULTS command clears all faults for the selected output. If PAGE 0xFF is selected, all faults for all PAGE outputs are cleared.

NOTE

POWER_GOOD_N and OFF indicate the current state of the outputs and cannot be cleared.

8.5.3.4 (10h) WRITE_PROTECT

The WRITE_PROTECT command disables writes on the PMBus. It has one data byte, described in Table 10.

Table 10. WRITE_PROTECT Command Data Byte Contents

DATA BYTE VALUE	MEANING
1000 0000	Disable all writes except to the WRITE_PROTECT command
0100 0000 (default)	Disable all writes except to the WRITE_PROTECT, OPERATION, and PAGE commands
0010 0000	Disable all writes except to the WRITE_PROTECT, OPERATION, PAGE, and VREF_COMMAND commands
0000 0000	Enable writes to all commands

If an invalid command is received, a communications fault is set. WRITE_PROTECT does not protect against CLEAR_FAULTS. The user is able to CLEAR_FAULTS anytime regardless of the WRITE_PROTECT state.

This command has no PAGE support.

NOTE

The WRITE_PROTECT parameter is not stored in the default store in data flash.

8.5.3.5 (11h) STORE_DEFAULT_ALL

The STORE_DEFAULT_ALL command saves the PMBus parameters from operating memory into the default store in data flash (EEPROM). The TPS65400-Q1 uses the most recently written set of default store values at startup. The maximum time it takes for the data flash to be written is 70 ms.

This command has no PAGE support.

NOTE

The OPERATION, PAGE, and WRITE_PROTECT parameters are not stored in the default store in data flash.

CAUTION

When STORE_DEFAULT_ALL is issued, operating memory should not be written to during the save.

8.5.3.6 (19h) CAPABILITY

The CAPABILITY command is a read-only command.

This command has no PAGE support.

Table 11. CAPABILITY COMMAND Data Byte Contents

BIT	READ / WRITE	DEFAULT VALUE	MEANING
7	R	1	Packet error checking is supported
6:5	R	01	Maximum supported bus speed is 400 kHz
4	R	0	Device does not have a SMBALERT pin and does not support the SMBus alert response protocol
3:0	R	0000	Reserved

8.5.3.7 (78h) STATUS_BYTE

The STATUS_BYTE command is a read-only command. Write mask is not supported. The bits are listed in Table 12.

Table 12. STATUS_BYTE Data Byte Contents

PAGE SUPPORT	BIT	NAME	READ / WRITE	DEFAULT VALUE	MEANING
—	7	Not supported	R	0	—
Yes	6	OFF	R	—	Output is off
Yes	5	VOUT_OV	R	—	Output overvoltage fault
Yes	4	IOUT_OC	R	—	Output overcurrent fault
No	2	TEMPERATURE	R	—	Overtemperature fault
—	3	Not supported	R	0	—
No	1	CML	R	—	Invalid command code, data, or packet
Yes	0	NONE OF THE ABOVE	R	—	A fault or warning not listed in bits [7:1] has occurred

Overtemperature fault and CML is independent of PAGE. When there is PAGE support, the meaning of the bits applies only for the selected output PAGE. For PAGE = 0xFF, STATUS_BYTE is a logical OR of all PAGE = 0x00 to 0x03 STATUS_BYTE values.

An exception to NONE OF THE ABOVE is that the MFR bit in STATUS_WORD is ignored due to no PAGE support.

PAGE support is for outputs 0x00 to 0x03, 0x0FF.

8.5.3.8 (79h) STATUS_WORD

The STATUS_WORD command is a read-only command. Write mask is not supported. Only the parameters in Table 13 are supported.

Table 13. STATUS_WORD Data Word Contents (Upper Byte)

PAGE SUPPORT	BIT	NAME	READ / WRITE	DEFAULT VALUE	MEANING
Yes	7	VOUT	R	—	Output voltage fault set if any bit in STATUS_VOUT is asserted (for the same page)
—	6	Not supported	R	0	—
—	5	Not supported	R	0	—
No	4	MFR	R	—	Set if any bit in STATUS_MFR_SPECIFIC is asserted
Yes	3	POWER_GOOD_N	R	—	Output voltage is within PGOOD range, negated
—	2	Not supported	R	0	—
—	1	Not supported	R	0	—
—	0	Not supported	R	0	—

The lower byte of STATUS_WORD is STATUS_BYTE.

The MFR bit is independent of PAGE. When there is PAGE support, the meaning of the bits applies only for the selected output PAGE. For PAGE = 0xFF, STATUS_WORD is a logical OR of all PAGE = 0x00 to 0x03 STATUS_WORD values.

PAGE support is for outputs 0x00 to 0x03, 0x0FF.

8.5.3.9 (7Ah) STATUS_VOUT

The STATUS_VOUT command is a read-only command. Write mask is not supported. Only the parameters in Table 14 are supported.

Table 14. STATUS_VOUT Data Byte Contents

BIT	NAME	READ / WRITE	DEFAULT VALUE	MEANING
7	VOUT_OV	R	—	VOUT overvoltage fault
6	Not supported	R	0	—
5	Not supported	R	0	—
4	VOUT_UV	R	—	VOUT undervoltage fault
3	Not supported	R	0	—
2	Not supported	R	0	—
1	Not supported	R	0	—
0	Not supported	R	0	—

STATUS_VOUT shows the voltage output status for the PAGE selected output. For PAGE = 0xFF, STATUS_VOUT is a logical OR of all PAGE = 0x00-0x03 STATUS_ VOUT values. VOUT_OV in STATUS_VOUT is identical to VOUT_OV in STATUS_BYTE for the same PAGE.

PAGE support is for outputs 0x00 to 0x03, 0x0FF.

8.5.3.10 (80h) STATUS_MFR_SPECIFIC

The STATUS_MFR_SPECIFIC command is a read-only command. Write mask is not supported. Only the parameters in Table 15 are supported.

Table 15. STATUS_MFR_SPECIFIC Data Byte Contents

BIT	NAME	READ / WRITE	DEFAULT VALUE	MEANING
7	Not supported	R	0	—
6	Not supported	R	0	—
5	Not supported	R	0	—
4	Not supported	R	0	—
3	POWER_GOOD4_N	R	—	SW4 output voltage is within PGOOD range, negated
2	POWER_GOOD3_N	R	—	SW3 output voltage is within PGOOD range, negated
1	POWER_GOOD2_N	R	—	SW2 output voltage is within PGOOD range, negated
0	POWER_GOOD1_N	R	—	SW1 output voltage is within PGOOD range, negated

STATUS_MFR_SPECIFIC reports the individual output negated PGOODs. These bit values also can be retrieved from POWER_GOOD_N if an individual output is selected through PAGE.

This command has no PAGE support.

8.5.3.11 (98h) PMBUS_REVISION

The PMBUS_REVISION command is a read-only command.

Table 16. PMBUS_REVISION Data Byte Contents

BITS	NAME	READ / WRITE	DEFAULT VALUE	MEANING
7:4	Part I revision	R	0010	Supports version 1.2
3:0	Part II revision	R	0010	Supports version 1.2

This command has no PAGE support.

8.5.3.12 (ADh) IC_DEVICE_ID

The IC_DEVICE_ID command is a read-only block command and returns the ASCII characters of the part number TPS65400-Q1.

Table 17. IC_DEVICE_ID Data Block Contents

BYTE	NAME	READ / WRITE	DEFAULT VALUE	ASCII VALUE
7	IC_DEVICE_ID	R	0x30	0
6			0x33	3
5			0x34	4
4			0x36	6
3			0x32	2
2			0x4D	M
1			0x4C	L
0	Length byte	R	0x07	—

This command has no PAGE support.

8.5.3.13 (AEh) IC_DEVICE_REV

The IC_DEVICE_REV command is a read-only block command and returns the 2-byte device code of the part. The device code is identical to the 2-byte DEVICE_CODE. Refer to DEVICE_CODE for details (see (FCh) DEVICE_CODE).

Table 18. IC_DEVICE_REV Data Block Contents

BYTE	NAME	READ / WRITE	DEFAULT VALUE
2:1	DEVICE_CODE	R	See DEVICE_CODE
0	Length byte	R	0x02

This command has no PAGE support.

8.5.4 Manufacturer-Specific Commands

8.5.4.1 (D0h) USER_DATA_BYTE_00

The USER_DATA_BYTE_00 command contains 8 bits for reading and writing user-defined data. Upon issuing STORE_DEFAULT_ALL, contents of this command are saved to the default store in data flash.

Table 19. USER_DATA_BYTE_00 Data Byte Contents

BITS	NAME	READ / WRITE	DEFAULT VALUE
7:0	USER_DATA_BYTE_00	R/W	0x00

This command has no PAGE support.

8.5.4.2 (D1h) USER_DATA_BYTE_01

The USER_DATA_BYTE_01 command contains 7 bits, USER_DATA_BITS_01, for reading and writing user-defined data. Upon issuing STORE_DEFAULT_ALL, contents of this command are saved to the default store in data flash.

The most significant bit, STORED, is a read-only bit that indicates whether the user has written to the default store through STORE_DEFAULT_ALL. This indicator bit cannot be cleared.

Table 20. USER_DATA_BYTE_01 Data Byte Contents

BITS	NAME	READ / WRITE	DEFAULT VALUE
7	STORED	R	0
6:0	USER_DATA_BYTE_01	R/W	0000000

This command has no PAGE support.

8.5.4.3 (D2h) PIN_CONFIG_00

The PIN_CONFIG_00 command selects pin function and behavior for enable pins ENSWx and the global PGOOD pin.

ENABLE_PIN_CONFIG selects between active ENABLE, inactive ENABLE, or single ENABLE behavior for ENSWx pins.

When active ENABLE is selected, each pin in conjunction with OPERATION controls its respective switcher on/off. For details, see (01h) OPERATION and (DDh) TON_TOFF_DELAY.
When inactive ENABLE is selected, the state of all ENSWx pins is ignored.
When single ENABLE is selected, ENSW1 pin acts as a sequence start and sequence stop pin, with all other ENSWx pins ignored. This allows the device to emulate classic sequencing behavior. A start sequence begins when ENSW1 is asserted, and a stop sequence begins when ENSW1 is deasserted. If ENSW1 were to de-assert before a start sequence were complete, a stop-sequence would begin immediately.

PGOOD_PIN_CONFIG sets the function of the global PGOOD pin.

By default, the global PGOOD pin is configured to output a logical AND of each individual power supply’s PGOOD. If all supplies were to turn off, the global PGOOD pin would be de-asserted.
The global PGOOD pin can be selected to output the status of any individual power supply’s PGOOD, or any OR/AND combination thereof. If an individual supply’s PGOOD#_MASK bit is masked, its PGOOD status would be masked from the global PGOOD pin. If all PGOOD#_MASK pins were masked, the output of the global PGOOD pin would be at logic zero regardless of the PGOOD_LOGIC selected.
PGOOD#_MASK only applies to the output pin logic and does not affect STATUS_WORD or sequencing.

Table 21. PIN_CONFIG_00 Data Byte Contents

BITS	NAME	READ / WRITE	DEFAULT VALUE	BINARY VALUE	MEANING	PINS AFFECTED
7	—	R	0	—	—	—
6	PGOOD_PIN_CONFIG: PGOOD_LOGIC	R/W	0	0	AND of all unmasked PGOODs	Global PGOOD pin
6	PGOOD_PIN_CONFIG: PGOOD_LOGIC	R/W	0	1	OR of all unmasked PGOODs
5	PGOOD_PIN_CONFIG: PGOOD4_MASK	R/W	1	0	PGOOD4 is masked
5	PGOOD_PIN_CONFIG: PGOOD4_MASK	R/W	1	1	PGOOD4 is unmasked
4	PGOOD_PIN_CONFIG: PGOOD3_MASK	R/W	1	0	PGOOD3 is masked
4		R/W	1	1	PGOOD3 is unmasked
3	PGOOD_PIN_CONFIG: PGOOD2_MASK	R/W	1	0	PGOOD2 is masked
3	PGOOD_PIN_CONFIG: PGOOD2_MASK	R/W	1	1	PGOOD2 is unmasked
2	PGOOD_PIN_CONFIG: PGOOD1_MASK	R/W	1	0	PGOOD1 is masked
2	PGOOD_PIN_CONFIG: PGOOD1_MASK	R/W	1	1	PGOOD1 is unmasked
1:0	ENABLE_PIN_CONFIG	R/W	00	00	Active ENABLE Enable pins ENSWx control each switcher independently	ENSW# pins
				01	Inactive ENABLE All enable pins ENSWx are ignored
				1X	Single ENABLE ENSW1 starts and stops sequencing. All other enable pins are ignored.

Table 22 shows example configurations for PGOOD_PIN_CONFIG.

Table 22. PGOOD_PIN_CONFIG Example Configurations

PGOOD_PIN_CONFIG BINARY VALUE	GLOBAL PGOOD PIN
01111 (default)	PGOOD1 and PGOOD2 and PGOOD3 and PGOOD4
11111	PGOOD1 or PGOOD2 or PGOOD3 or PGOOD4
00101	PGOOD1 and PGOOD3
X0001	PGOOD1
X0010	PGOOD2
X0100	PGOOD3
X1000	PGOOD4

This command has no PAGE support.

CAUTION

Changing PIN_CONFIG_00 during normal operation has no effect. The configuration can only be modified by storing into EEPROM and then reloading the configuration upon reset.

8.5.4.4 (D3h) PIN_CONFIG_01

PIN_CONFIG_01 command selects pin function and behavior for the selected output’s SSx/PG pin.

SSPG_PIN_CONFIG sets the selected power supply’s SSx/PG pin to a soft-start time input pin or a power good output pin.

When selected as soft-start time input pin SSx, the internal soft-start ramp rate TON_TRANSITION_RATE is ignored. A 5-µA current source will be connected internally and an external capacitor can be used to set the soft-start delay.
When selected as a power good output pin PG (PGOOD), the pin outputs the status of the selected power supply’s power good.

Table 23. PIN_CONFIG_01 Data Byte Contents

BITS	NAME	READ / WRITE	DEFAULT VALUE	BINARY VALUE	MEANING	PINS AFFECTED
7:1	—	R	0000000	—	—	—
0	SSPG_PIN_CONFIG	R/W	0	0	SSx pin	SSx/PG pin
0	SSPG_PIN_CONFIG	R/W	0	1	PG pin	SSx/PG pin

PAGE support is for outputs 0x00 through 0x03.

CAUTION

Changing PIN_CONFIG_01 during normal operation will have no effect. The configuration can only be modified by storing into EEPROM and then reloading the configuration upon reset.

8.5.4.5 (D4h) SEQUENCE_CONFIG

The SEQUENCE_CONFIG command determines sequencing behavior.

START_PGOOD determines whether the next output in sequence looks at the previous output’s PGOOD before turning on. For turning on, the previous output’s PGOOD must be good. For the first in sequence, there is no PGOOD reference so START_PGOOD for those particular switchers are ignored. START_PGOOD applies to all switchers.

Table 24. SEQUENCE_CONFIG Data Byte Contents

BITS	NAME	READ / WRITE	DEFAULT VALUE	BINARY VALUE	MEANING
7:1	—	R	0000000	—	—
0	START_PGOOD	R/W	0	0	PGOOD is checked
0	START_PGOOD	R/W	0	1	PGOOD is ignored

This command has no PAGE support.

CAUTION

TI does not recommend changing SEQUENCE_CONFIG during start sequencing or stop sequencing.

8.5.4.6 (D5h) SEQUENCE_ORDER

The SEQUENCE_ORDER command determines the order in which each output starts and stops. If two or more supplies are assigned the same sequence number, they start/stop at the same time. If sequencing is not used, all sequence bits should be set to the same value. For PGOOD sequencing options, see (D4h) SEQUENCE_CONFIG.

Table 25. SEQUENCE_ORDER Data Byte Contents

BITS	NAME	READ / WRITE	DEFAULT VALUE	BINARY VALUE	VALUE	MEANING
7:4	—	R	0000	—	—	—
3:2	STOP_ORDER	R/W	00	00	1 (first to stop)	Stop sequence order number
				01	2
				10	3
				11	4 (last to stop)
1:0	START_ORDER	R/W	00	00	1 (first to start)	Start sequence order number
				01	2
				10	3
				11	4 (last to start)

CAUTION

TI does not recommend changing SEQUENCE_ORDER during start sequencing or stop sequencing.

PAGE support is for outputs 0x00 to 0x03.

8.5.4.7 (D6h) IOUT_MODE

The IOUT_MODE command configures the selected output to be:

Operating in CCM
Operating in Mixed CCM/DCM

There is a read-only bit, IOUT_SHARE, that indicates that the current selected output:

Shares its current
Does not share its current

On the TPS65400-Q1, current share is organized in pairs (PAGE = 0x00, 0x01 and PAGE = 0x02, 0x03). When current sharing mode is detected on a particular pair, the slave PAGE is invalid and the slave’s default settings follow that of its master PAGE. The only exception is that the slave switcher PWM is a fixed 180° phase-shift from its master (see (D7h) FREQUENCY_PHASE).

Table 26. IOUT_MODE Data Byte Contents

BITS	NAME	READ / WRITE	DEFAULT VALUE	BINARY VALUE	MEANING
7:2	—	R	000000	—	—
1	IOUT_SHARE	R	—	0	Current is not shared
1	IOUT_SHARE	R	—	1⁽¹⁾	Current is shared⁽¹⁾
0	CCM	R/W	1	0	Mixed CCM/DCM
0	CCM	R/W	1	1	CCM

(1) This bit is only observable from the master PAGEs (see (00h) PAGE).

PAGE support is for outputs 0x00 through 0x03.

CAUTION

Changing IOUT_MODE during normal operation has no effect. The configuration can only be modified by storing into EEPROM and then reloading the configuration upon reset.

8.5.4.8 (D7h) FREQUENCY_PHASE

The FREQUENCY_PHASE command sets the output switching frequency and phase of the selected output. The switching frequency is a quotient from the division of the master clock, F_OSC, by the selected divisor CLK_DIV. PHASE_DELAY determines the phase shift as a multiple of the internal PLL period, which is scaled at 4× less than the master clock period 1 / F_OSC.

Table 27. FREQUENCY_PHASE Data Byte Contents

BITS	NAME	READ / WRITE	DEFAULT VALUE	BINARY VALUE	VALUE	MEANING
7	—	R	0	—	—	—
6:2	PHASE_DELAY	R/W	See Table 28	00000	0	Switching delay time (phase)
				00001	1 / (4 × FOSC)
				..	..
				11110	30 / (4 × FOSC)
				11111	31 / (4 × FOSC)
1:0	CLK_DIV	R/W	00	00	FOSC / 1	Switching frequency
				01	FOSC / 2
				10	FOSC / 4
				11	FOSC / 8

Table 28. PHASE_DELAY Default Data Bit Values

PAGE	PHASE_DELAY BINARY VALUE	PHASE SHIFT (°)
0x00	00000	0
0x01	00010	180
0x02	00001	90
0x03	00011	270

The phase shift in degrees is calculated by Equation 5.

Equation 5. TPS65400-Q1 eq_12_phase_shift_LVSCQ9.gif

When current sharing mode is detected on a particular pair, the slave PAGE is invalid and the slave’s default settings follow that of its master PAGE. The only exception is that the slave switcher PWM is a fixed 180° phase-shift from its master. Additionally, the ISHARE bit is asserted (see (D6h) IOUT_MODE).

PAGE support is for outputs 0x00 through 0x03.

CAUTION

Changing the FREQUENCY_PHASE during normal operation has no effect. The configuration can only be modified by storing into EEPROM and then reloading the configuration upon reset.

8.5.4.9 (D8h) VREF_COMMAND

The VREF_COMMAND command sets the voltage reference (VREF) for the selected output. Values range from 0.6 to 1.87 V with a bit resolution of 10 mV per LSB.

Table 29. VREF_COMMAND Data Byte Contents

BITS	NAME	READ / WRITE	DEFAULT VALUE	BINARY VALUE	VALUE	MEANING
7	—	R	0	—	—	—
6:0	VREF_COMMAND	R/W	0010100	0000000	0.60 V	Reference voltage
				0000001	0.61 V
				…	…
				0010100	0.8 V
				…	…
				1111110	1.86 V
				1111111	1.87 V

The voltage reference can be changed while one or more voltage outputs are enabled. To reduce the effect of large transient steps, digital slew rate limiting is implemented. The larger the change in the voltage reference, the greater the delay that is incurred as the voltage steps toward the new reference. For details, see (DFh) VREF_TRANSITION_RATE.

Faults are blanked during transition. A 100-s fault blanking time results after a transition completes.

PAGE support is for outputs 0x00 through 0x03.

8.5.4.10 (D9h) IOUT_MAX

The IOUT_MAX command sets the current limit for the selected output.

Table 30. IOUT_MAX Data Byte Contents, PAGE = 0x00, 0x01

BITS	NAME	READ / WRITE	DEFAULT VALUE	BINARY VALUE	VALUE	MEANING
7:3	—	R	00000	—	—	—
2:0	IOUT_MAX	R/W	100	000	2 A	Current limit
				001	3 A
				010	4 A
				011	5 A
				1XX	6 A

Table 31. IOUT_MAX Data Byte Contents, PAGE = 0x02, 0x03

BITS	NAME	READ / WRITE	DEFAULT VALUE	BINARY VALUE	VALUE	MEANING
7:2	—	R	000000	—	—	—
1:0	IOUT_MAX	R/W	11	00	0.5 A	Current limit
				01	1 A
				10	2 A
				11	3 A

The limit set by the IOUT_MAX byte sets both the high-side and low-side current limit.

PAGE support is for outputs 0x00 through 0x03.

8.5.4.11 (DAh) USER_RAM_00

The USER_RAM_00 command is a reset notification status. Upon any RESET condition, the device clears this value to 0x00. This value can only be set to 0x01 by the PMBus master.

Table 32. USER_RAM_00 Data Byte Contents

BITS	NAME	READ / WRITE	DEFAULT VALUE
7:1	—	R	0000000
0	USER_RAM_00	R/W	0

This command has no PAGE support.

8.5.4.12 (DBh) SOFT_RESET

The SOFT_RESET command triggers a software reset of the device. It is equivalent to sending an assert-deasserting pulse to the CE pin. Consequently, all switchers turn off and all faults are cleared.

This command has no PAGE support.

8.5.4.13 (DCh) RESET_DELAY

The RESET_DELAY command sets the delay time before any switcher can begin its soft-start after CE is asserted. Thus, if the turn-on sequence or an individual switcher is enabled before this delay is over, no action occurs until the delay is completed. After this delay period is passed, enabling the turn-on sequence of an individual switcher would have an immediate effect subject to the t_{ON_DELAY} and soft-start time.

Table 33. RESET_DELAY Data Byte Contents⁽¹⁾

BITS	NAME	READ / WRITE	DEFAULT VALUE	BINARY VALUE	VALUE	MEANING
7:3	—	R	00000	—	—	—
2:0	RESET_DELAY	R/W	000	000	1 ms⁽²⁾	Reset delay time
				001	50 ms
				010	100 ms
				011	250 ms
				100	500 ms
				101	1000 ms
				110	1500 ms
				111	2000 ms

(1) All the delay times are subject to the delay between the rising edge of CE and the stabilizing delay time of the VDDD supply, which can be up to 1.1 ms, depending on the bypass capacitor sizing for these rails. The RESET_DELAY in the table is in addition to this power-up delay and has an accuracy of ±62.5 μs.

(2) When setting the RESET_DELAY to 1 ms, TI recommends that the t_{ON_DELAY} for the outputs starting up first be greater than 5 ms. Because, the COMP pin precharge starts at the same time as the RESET_DELAY. If RESET_DELAY is 1 ms, and t_{ON_DELAY} is 0 ms, then the COMP pin precharge may not stabilize before the switcher soft-start begins. The time needed to stabilize the COMP pin precharge depends on the RC compensation values connected to the COMP pin.

This command has no PAGE support.

8.5.4.14 (DDh) TON_TOFF_DELAY

The TON_TOFF_DELAY command sets the delay times after receiving an on or off command for the selected output to begin turning on or off.

TON_DELAY of this command are lexically equivalent to TON_DELAY. If TON_DELAY is set to 0 ms, the device would begin turning on immediately. If TOFF_DELAY is set to 0 ms, the device would begin turning off immediately.

Table 34. TON_TOFF_DELAY Data Byte Contents

BITS	NAME	READ / WRITE	DEFAULT VALUE	BINARY VALUE	VALUE	MEANING
7:6	—	R	00	—	—	—
5:3	TON_DELAY	R/W	010	000	0 ms	Delay time before starting
				001	1 ms
				010	5 ms
				011	25 ms
				100	100 ms
				101	500 ms
				110	1000 ms
				111	2000 ms
2:0	TOFF_DELAY	R/W	000	000	0 ms	Delay time before stopping
				001	1 ms
				010	5 ms
				011	25 ms
				100	100 ms
				101	500 ms
				110	1000 ms
				111	2000 ms

These delays are always in effect including when the outputs are internally or externally sequenced, or arbitrarily turned on or off. The only exceptions are:

The device receives an immediate OFF from the OPERATION command.
The device turns its output off internally (such as in a fault condition).

PAGE support is for outputs 0x00 through 0x03.

8.5.4.15 (DEh) TON_TRANSITION_RATE

The TON_TRANSITION_RATE command sets the soft-start ramp rate for the selected output. This command is ignored by default because soft-start is set externally through the SSx/PG pin. Only when the SSx/PG pin is configured as PG through PIN_CONFIG_01 will TON_TRANSITION_RATE determine the soft-start rate.

The soft-start ramp rate refers to the rate at which the reference voltage is increased. The time to complete the soft-start can be calculated from the target reference voltage as Equation 6.

Equation 6. TPS65400-Q1 eq_13_Tss_LVSCQ9.gif

For example, if VREF is set to 0.6 V and the default soft-start ramp rate of 0.5 V/ms is selected, then the soft-start time would be 1.2 ms. If VREF is set to 1 V and the soft-start ramp rate of 0.25 V/ms is selected, then the soft-start time would be 4 ms.

Table 35. TON_TRANSITION_RATE Data Byte Contents

BITS	NAME	READ / WRITE	DEFAULT VALUE	BINARY VALUE	VALUE	MEANING
7:2	—	R	000000	—	—	—
1:0	TON_RAMP_RATE	R/W	10	00	2 V/ms	Soft-start ramping rate
				01	1 V/ms
				10	0.5 V/ms
				11	0.25 V/ms

PAGE support is for outputs 0x00 through 0x03.

8.5.4.16 (DFh) VREF_TRANSITION_RATE

The VREF_TRANSITION_RATE command determines the stepping rate and stepping size when dynamically switching the reference voltage VREF of the selected output.

Table 36. VREF_TRANSITION_RATE Data Byte Contents

BITS	NAME	READ / WRITE	DEFAULT VALUE	BINARY VALUE	VALUE	MEANING
7	VREF_RAMP_ENABLE	R/W	1	0	—	Ramping disabled
7	VREF_RAMP_ENABLE	R/W	1	1	—	Ramping enabled
6	—	R	0	—	—	—
5:3	VREF_RAMP_TIMESTEP	R/W	011	000	1 µs	Delay time per ramping step
				001	2 µs
				010	3 µs
				011	4 µs
				100	6 µs
				101	8 µs
				110	12 µs
				111	16 µs
2:0	VREF_RAMP_BITSTEP	R/W	000	See Table 37	See Table 37	Ramp up and ramp down LSB increments / decrements

Table 37. VREF_RAMP_BITSTEP Data Bit Values

VREF_RAMP_BITSTEP BINARY VALUE	RAMP UP (LSB increments)	RAMP DOWN (LSB decrements)
000 (default)	1	1
001	2	1
010	4	2
011	6	3
100	8	4
101	10	5
110	12	6
111	16	8

VREF_RAMP_BITSTEP sets the amount of voltage reference bits to ramp up and ramp down per VREF_RAMP_TIMESTEP time. During ramping, if the target step is less than or equal to the VREF_RAMP_BITSTEP setting, ramping reduces to a fine voltage step of 1 LSB per VREF_RAMP_TIMESTEP time until the target voltage has been reached. For the actual voltage change per LSB, refer to (D8h) VREF_COMMAND.

PAGE support is for outputs 0x00 through 0x03.

8.5.4.17 (F0h) SLOPE_COMPENSATION

The SLOPE_COMPENSATION command modifies control loop compensation parameters to compensate for inductor ripple current harmonics from switching.

Table 38. SLOPE_COMPENSATION Data Byte Contents

BITS	NAME	READ / WRITE	DEFAULT VALUE	BINARY VALUE	VALUE	MEANING
7:2	—	R	000000	—	—	—
1:0	SLOPE_COMPENSATION	R/W	01	00	45 mV/µs	Slope compensation
				01	70 mV/µs
				10	100 mV/µs
				11	145 mV/µs

The default slope compensation will be adequate for most applications. The equivalent current slope compensation ramp on the inductor can be found by the following formula:

Equation 7. ΔI_L = –G_mps × SL_comp (A/S)

Where Gmps is the current sense gain of the peak current control to COMP voltage in Amps per Volt and SLcomp is the slope compensation voltage expressed in the table above.

Ideal slope compensation is achieved when:

Equation 8. TPS65400-Q1 eq_14_IL_LVSCQ9.gif

PAGE support is for outputs 0x00 through 0x03.

8.5.4.18 (F1h) ISENSE_GAIN

The ISENSE_GAIN command modifies the current sense G_mps of the feedback loop for the selected output. (F0h) SLOPE_COMPENSATION describes the equivalent current slope compensation ramp on the inductor.

Table 39. ISENSE_GAIN Data Byte Contents, PAGE = 0x00, 0x01

BITS	NAME	READ / WRITE	DEFAULT VALUE	BINARY VALUE	VALUE	MEANING
7:2	—	R	000000	—	—	—
1:0	ISENSE_GAIN	R/W	01	00	20 A/V	Current sense gain
				01	10 A/V
				10	5 A/V
				11	2.5 A/V

Table 40. ISENSE_GAIN Data Byte Contents, PAGE = 0x02, 0x03

BITS	NAME	READ / WRITE	DEFAULT VALUE	BINARY VALUE	VALUE	MEANING
7:2	—	R	000000	—	—	—
1:0	ISENSE_GAIN	R/W	01	00	10 A/V	Current sense gain
				01	5 A/V
				10	2.5 A/V
				11	1.25 A/V

PAGE support is for outputs 0x00 through 0x03.

8.5.4.19 (FCh) DEVICE_CODE

The DEVICE_CODE command returns a 2-byte read-only device code. For the TPS65400-Q1, this is 0x00FX, where 'X' is the revision/version number. This command has no PAGE support.

Table 41. DEVICE_CODE Data Word Contents

BITS	NAME	READ / WRITE	DEFAULT VALUE
15:4	DEVICE_CODE_ID	R	0x00F
3:0	DEVICE_CODE_REV	R	X

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発注情報

8 Detailed Description

8.1 Overview

8.2 Functional Block Diagrams

8.3 Feature Description

8.3.1 Startup Timing and Power Sequencing

8.3.1.1 Startup Timing

8.3.1.2 External Sequencing

8.3.1.3 Internal Sequencing

8.3.2 UVLO and Precision Enables

8.3.3 Soft-Start and Prebiased Startup

8.3.3.1 Analog Soft-Start (Default) and Digital Soft-Start

8.3.3.2 Soft-Start Capacitor Selection

8.3.4 PWM Switching Frequency Selection

8.3.5 Clock Synchronization

8.3.6 Phase Interleaving

Table 1. Programmable Options When Current Sharing Enabled

8.3.7 Fault Handling

8.3.8 OCP for SW1 to SW4

Table 2. Current Limit Options

8.3.9 Overcurrent Protection for SW1 to SW4 in Current Sharing Operation

8.3.10 Recovery on Power Loss

8.3.11 Feedback Compensation

Table 3. Compensation Calculation Table

8.3.12 Adjusting Output Voltage

8.3.13 Digital Interface – PMBus

8.3.14 Initial Configuration

8.4 Device Functional Modes

8.4.1 CCM Operation Mode

8.4.2 CCM/DCM Operation Mode

8.4.3 Current Sharing Mode

8.5 Register Maps

Table 4. Supported PMBus Commands

Table 5. Command Bit-Mapping

8.5.1 PMBus

8.5.1.1 Overview

8.5.1.2 PMBus Protocol

8.5.1.2.1 PMBus Protocol

8.5.1.2.2 Transactions (No PEC)

8.5.1.2.3 Addressing

Table 6. I2C Address Selection

8.5.1.2.4 Startup

8.5.1.2.5 Bus Speed

8.5.1.2.6 I2CALERT Terminal

Table 7. Timeout Specifications

8.5.1.2.7 CONTROL Terminal

8.5.1.2.8 Packet Error Checking

8.5.1.2.9 Group Commands

8.5.1.2.10 Unsupported Features

8.5.2 PMBus Register Descriptions

8.5.2.1 Overview

8.5.2.2 Memory Model

8.5.2.3 Data Formats

8.5.2.4 Fault Monitoring

8.5.3 PMBus Core Commands

8.5.3.1 (00h) PAGE

Table 8. PAGE Data Byte Contents

8.5.3.2 (01h) OPERATION

Table 9. Operation Data Byte Contents

8.5.3.3 (03h) CLEAR_FAULTS

8.5.3.4 (10h) WRITE_PROTECT

Table 10. WRITE_PROTECT Command Data Byte Contents

8.5.3.5 (11h) STORE_DEFAULT_ALL

8.5.3.6 (19h) CAPABILITY

Table 11. CAPABILITY COMMAND Data Byte Contents

8.5.3.7 (78h) STATUS_BYTE

Table 12. STATUS_BYTE Data Byte Contents

8.5.3.8 (79h) STATUS_WORD

Table 13. STATUS_WORD Data Word Contents (Upper Byte)

8.5.3.9 (7Ah) STATUS_VOUT

Table 14. STATUS_VOUT Data Byte Contents

8.5.3.10 (80h) STATUS_MFR_SPECIFIC

Table 15. STATUS_MFR_SPECIFIC Data Byte Contents

8.5.3.11 (98h) PMBUS_REVISION

Table 16. PMBUS_REVISION Data Byte Contents

8.5.3.12 (ADh) IC_DEVICE_ID

Table 17. IC_DEVICE_ID Data Block Contents

Table 6. I²C Address Selection

Table 33. RESET_DELAY Data Byte Contents⁽¹⁾