JAJSFK1 データシート

JAJSFK1E November 2014 – March 2022 TPS65400

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RGZ|48
- MPQF123F

サーマルパッド・メカニカル・データ

RGZ|48
- QFND014T

発注情報

7.5 Electrical Characteristics

V_IN = 12 V, Frequency = 500 kHz, T_J = –40°C to 125°C, typical values are at T_J = 25°C, unless otherwise indicated

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SWITCHER 1 AND SWITCHER 2
I_limit1, I_limit2	SW1, SW2 high-side current limit adjustment range		2		6	A
I_{limit-accuracy}	Accuracy to nominal current limit value	I_limit = 4 A, 5 A, 6 A	–25%		25%
R_dson HS	SW1, SW2 HS Rds(on)			66		mΩ
R_dson LS	SW1, SW2 LS Rds(on)			42		mΩ
SWITCHER 3 AND SWITCHER 4
I_limit3, I_limit4	SW3 and SW4 current limit		0.5		3	A
I_{limit accuracy}	Accuracy to nominal current limit value	I_limit = 1 A, 2 A, 3 A	–25%		25%
R_dson HS	SW3 and SW4 HS Rds(on)			120		mΩ
R_dson LS	SW3/4 LS Rds(on)			90		mΩ
FEEDBACK AND ERROR AMPLIFIERS FOR SW1 – SW4
VFB	Accuracy	V_REF = 1 V	–1%		1%
V_REFn	Error amplifier reference voltage	Default value		800		mV
V_{REF_STEP}	I²C programmable V_REF step size			10		mV
Gm	Error amplifier transconductance		95	133	165	µS
I_sink	Sink			12		µA
I_source	Source			12		µA
PWM SWITCHING CHARACTERISTICS
Phase_err12⁽¹⁾	Phase error between SW1 and SW2	F_sw = 1.1 MHz		5⁰
Phase_err34⁽¹⁾	Phase error between SW3 and SW4	F_sw = 1.1 MHz		5⁰
F_sw	Resistor-configurable PWM switching configuration		275		2200	kHz
F_sw-accuracy	PWM switching frequency accuracy	R_OSC = 165 kΩ (F_sw = 1.1 MHz)	–10%		10%
V_{rclock_sync}	Voltage reference for RCLOCK_SYNC			0.8		V
t_{ON_min}	Lower duty cycle limit			80	150	ns
t_{OFF_min}	Minimum off-time limit (constrains the maximum achievable duty cycle)			150		ns
CLOCK SYNC
V_H_SYNC	High signal threshold		2.6			V
V_L_SYNC	Low signal threshold				1	V
I_CLKOUT	Max current sink/source for CLK_OUT			2		mA
t_{min_}_SYNC	Minimum detectable time for sync pulse				150	ns
F_SYNC	Frequency synchronization range		275		2200	kHz
T_{SYNC_DELAY}	Delay between input pulse to RCLOCK_SYNC and rising edge of CLK_OUT and PWM output			20		ns
TIMING CHARACTERISTICS
t_restart	Delay for restart during repeated OCP condition			20		ms
INTERNAL REGULATORS AND UVLO
V_DDA	Internal subregulator output	V_in > 6.6 V		6.1		V
V_DDA	Internal subregulator output	4.5 V < V_in 6.6 V		V_in – 0.1		V
V_DDD	Output of internal subregulator			3.2		V
V_DDG	Output of internal regulator for gate drivers	V_in > 6.6 V		6.1		V
V_DDG	Output of internal regulator for gate drivers	4.5 V < V_in 6.6 V		V_in – 0.1		V
I_VIN	Quiescent non-switching, no load current	CE high, V_FB >> V_REF, (no switching)		8		mA
I_SD	Quiescent shutdown current	CE low		12	27	µA
V_{IN_UVLO}	Input voltage UVLO	Rising		4.25	4.48	V
V_{IN_UVLO}	Input voltage UVLO	Falling	3.4	3.75		V
PGOOD, ENSWx, RST_N, SSx, PG
R_L_PGOOD	Resistance of PGOOD outputs when low			500		Ω
V_OL_PGOOD	Logic output low voltage	I_OL = 100 µA			0.1	V
I_SS	Soft-start current		4.1	5.6	7.3	µA
V_EN	Enable logic high threshold (for ENSW1, ENSW2, ENSW3, ENSW4)	V_EN rising	1.12	1.20	1.28	V
V_{EN_L}	Enable logic low threshold (for ENSW1, EN_L ENSW2, ENSW3, ENSW4)	V_EN falling	0.97	1.07		V
V_{EN_HYS}	Enable hysteresis (for ENSW1, ENSW2, ENSW3, ENSW4)	V_EN falling		130		mV
I_EN	ENSWx pin pullup current	V_EN = 0		2		µA
I_CE	CE pin pullup current	V_CE = 0		2		µA
V_{IH_CE}	Logic input high for CE		1.3			V
V_{IL_CE}	Logic input low CE				0.4	V
V_{IH_RSTN}	Logic input high RST_N		1.3			V
V_{IL_RSTN}	Logic input low RST_N				0.4	V
I²C MODULE (SDA, SCL, I2CALERT, I2CADDR)
V_IL_I2C	Logic input low SCL, SDA				0.8	V
V_IH_I2C	Logic input high for SCL, SDA		2.1			V
R_L_I2C	ON resistance of I²C pins (SDA, SCL, I2CALERT) to GND	I2CALERT = 1		85		Ω
V_OL_I2C	Logic output low voltage for SCL, SDA, I2CALERT pins	I_OL = 350 µA			0.1	V
I_LEAK	Input leakage current	SDA, SCL = 3.3 V			1	µA
I_I2CADDR	Source current of I2CADDR pin	VDDD = 3.3 V, V_IN > 4.5 V		20		µA
t_TIMEOUT	Timeout detection on SDA or SCL low			30		ms
t_{TIMEOUT_PULSE}	Duration of timeout pulse on I2CALERT			200		µs
FAULTS
T_TSD⁽²⁾	Thermal shutdown threshold			160		⁰C
T_{TSD_restart}⁽²⁾	Thermal shutdown hysteresis			20		⁰C
V_{FB_OVP}	OVP threshold rising (fault latched, PGOOD asserted)	0.6V < V_REF < 1.87 V		111		% of V_REF
V_{FB_OVP}	OVP threshold falling (fault cleared, PGOOD deasserted)	0.6 V < V_REF < 1.87 V		104		% of V_REF
t_OVPSDOWN	Time after OVP before protection activation and PGOOD fall			55	95	µs
V_{FB UVP}	Undervoltage threshold (PGOOD deasserted)	0.6 V < V_REF < 1.87 V		92		% of V_REF
V_{FB UVP}	Undervoltage threshold (PGOOD asserted)	0.6 V < V_REF < 1.87 V		83		% of V_REF
t_UVPSDOWN	Time after UVP before PGOOD fall			55	95	µs

(1) Specified by design

(2) Specified by lab validation