JAJSH47 データシート

JAJSH47 March 2019 TPS65653-Q1

PRODUCT PREVIEW Information. Product in design phase of development. Subject to change or discontinuance without notice.

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8.5.1.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The TPS65653-Q1 pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The TPS65653-Q1 generates an acknowledge after each byte has been received.

There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down.

NOTE

If the V_(VANA) voltage is below VANA_UVLO threshold level during I²C communication the TPS65653-Q1 device does not drive SDA line. The ACK signal and data transfer to the master is disabled at that time.

After the START condition, the bus master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE, and a 1 indicates a READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register.

Figure 19. Write Cycle (w = write; SDA = 0). Example Device Address = 0x60

When READ function is to be accomplished, a WRITE function must precede the READ function as shown above.

Figure 20. Read Cycle (r = read; SDA = 1). Example Device Address = 0x60

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発注情報

8.5.1.3 Transferring Data