SLVSAI6A June   2011  – January 2016 TPS65735

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Terminal Configuration and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Pin Functions
  4. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Power-On Hours (POH)
    4. 4.4 Recommended Operating Conditions
    5. 4.5 Thermal Information
    6. 4.6 Electrical Characteristics
    7. 4.7 Quiescent Current
    8. 4.8 Typical Characteristics
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 System Operation
        1. 5.3.1.1 System Power Up
        2. 5.3.1.2 System Operation Using Push Button Switch
        3. 5.3.1.3 System Operation Using Slider Switch
      2. 5.3.2 Linear Charger Operation
        1. 5.3.2.1 Battery and TS Detection
        2. 5.3.2.2 Battery Charging
          1. 5.3.2.2.1 Pre-charge
          2. 5.3.2.2.2 Charge Termination
          3. 5.3.2.2.3 Recharge
          4. 5.3.2.2.4 Charge Timers
        3. 5.3.2.3 Charger Status (nCHG_STAT Pin)
      3. 5.3.3 LDO Operation
        1. 5.3.3.1 LDO Internal Current Limit
      4. 5.3.4 Boost Converter Operation
        1. 5.3.4.1 Boost Thermal Shutdown
        2. 5.3.4.2 Boost Load Disconnect
      5. 5.3.5 Full H-Bridge Analog Switches
        1. 5.3.5.1 H-Bridge Switch Control
      6. 5.3.6 Power Management Core Control
        1. 5.3.6.1 SLEEP / Power Control Pin Function
        2. 5.3.6.2 COMP Pin Functionality
        3. 5.3.6.3 SW_SEL Pin Functionality
        4. 5.3.6.4 SWITCH Pin
        5. 5.3.6.5 Slider Switch Behavior
        6. 5.3.6.6 Push-Button Switch Behavior
    4. 5.4 Device Functional Modes
      1. 5.4.1 SLEEP State
      2. 5.4.2 NORMAL Operating Mode
  6. 6 Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Active Shutter 3D Glasses
        1. 6.2.1.1 Design Requirements
        2. 6.2.1.2 Detailed Design Procedure
          1. 6.2.1.2.1 Reducing System Quiescent Current (IQ)
          2. 6.2.1.2.2 Boost Converter Application Information
            1. 6.2.1.2.2.1 Setting Boost Output Voltage
            2. 6.2.1.2.2.2 Boost Inductor Selection
            3. 6.2.1.2.2.3 Boost Capacitor Selection
          3. 6.2.1.2.3 Bypassing Default Push-Button SWITCH Functionality
        3. 6.2.1.3 Application Curves
  7. 7  Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Community Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Specifications

4.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Input voltage on all pins (except for VIN, BST_OUT, BST_SW, BST_FB, VLDO, LCLP, LCLN, LCRP, LCRN, AGND, DGND, and PGNDBST) with respect to AGND –0.3 7 V
VIN with respect to AGND –0.3 28 V
BST_OUT, BST_SW, LCLP, LCLN, LCRP, and LCRN with respect to PGNDBST –0.3 18 V
BST_FB with respect to PGNDBST, VLDO with respect to DGND –0.3 3.6 V
TA Operating free-air temperature 0 60 °C
TJ Junction temperature Electrical characteristics ensured 0 85 °C
Functionality ensured(3) 0 105
Tstg Storage temperature –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Device has a thermal shutdown feature implemented that shuts down at 105°C

4.2 ESD Ratings

VALUE UNIT
VESD Electrostatic discharge Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001(1) ±1000 V
Charged Device Model (CDM),
per JESD22-C101(2)		 ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4.3 Power-On Hours (POH)

See (1)(2)(3)(4)
OPERATING CONDITION NOMINAL CVDD VOLTAGE (V) JUNCTION TEMPERATURE (Tj) LIFETIME POH(5)
100% OPP 1.1 –40 to 105 °C 100 K
120% OPP 1.2 –40 to 105 °C 100 K
166% OPP 1.35 –40 to 105 °C 49 K
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms and conditions for TI semiconductor products.
(2) To avoid significant degradation, the device power-on hours (POH) must be limited to those specified in this table.
(3) Logic functions and parameter values are not assured out of the range specified in the recommended operating conditions.
(4) Notations in this table cannot be deemed a warranty or deemed to extend or modify the warranty under TI's standard terms and conditions for TI semiconductor products.
(5) POH represent device operation under the specified nominal conditions continuously for the duration of the calculated lifetime.

4.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
CHARGER / POWER PATH
VVIN Voltage at charger input pin 3.7 28(2) V
IVIN Input current at VIN pin 200 mA
CVIN Capacitor on VIN pin 0.1 2.2 10 µF
LVIN Inductance at VIN pin 0 2 µH
VSYS Voltage at SYS pin 2.5 6.4 V
ISYS(OUT) Output current at SYS pin 100 mA
CSYS Capacitor on SYS pin 0.1 4.7 10 µF
VBAT Voltage at BAT pin 2.5 6.4 V
CBAT Capacitor on BAT pin 4.7 10 µF
REXT(nCHG_STAT) Resistor connected to nCHG_STAT pin to limit current into pin 320 Ω
BOOST CONVERTER / H-BRIDGE SWITCHES
VIN(BST_SW) Input voltage for boost converter 2.5 6.5 V
VBST_OUT Output voltage for boost converter 8 16 V
CBST_OUT Boost output capacitor 3.3 4.7 10 µF
LBST_SW(1) Inductor connected between SYS and BST_SW pins 4.7 10(3) µH
LDO
CVLDO External decoupling cap on pin VLDO 1 10 µF
POWER MANAGEMENT CORE CONTROL (LOGIC LEVELS FOR GPIOs)
VIL(PMIC) GPIO low level (BST_EN, CHG_EN, SW_SEL, VLDO_SET and to switch H-Bridge inputs to a low, 0, level) 0.4 V
VIH(PMIC) GPIO high level (BST_EN, CHG_EN, SW_SEL, VLDO_SET and to switch H-Bridge inputs to a high, 1, level) 1.2 V
(1) See Section 5.3.4 for information on boost converter inductor selection.
(2) VIN pin has 28 V ESD protection
(3) Design optimized for boost operation with 10 µH inductor

4.5 Thermal Information

THERMAL METRIC(1) TPS65735 UNIT
RSN (WQFN)
32 PINS
RθJA Junction-to-ambient thermal resistance(2) 38.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance(3) 26.5 °C/W
RθJB Junction-to-board thermal resistance(4) 9.8 °C/W
ψJT Junction-to-top characterization parameter(5) 0.3 °C/W
ψJB Junction-to-board characterization parameter(6) 9.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance(7) 3.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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4.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BATTERY CHARGER POWER PATH
VUVLO(VIN) Undervoltage lockout at power path input, VIN pin VVIN: 0 V → 4 V 3.2 3.3 3.45 V
VHYS-UVLO(VIN) Hysteresis on UVLO at power path input, VIN pin VVIN: 4 V → 0 V 200 300 mV
VIN-DT Input power detection threshold Input power detected if: (VVIN > VBAT + VIN-DT);
VBAT = 3.6 V
VVIN: 3.5 V → 4 V		 40 140 mV
VHYS-INDT Hysteresis on VIN-DT VBAT = 3.6 V
VVIN: 4 V → 3.5 V		 20 mV
VOVP Input over-voltage protection threshold VVIN: 5 V → 7 V 6.4 6.6 6.8 V
VHYS-OVP Hysteresis on OVP VVIN: 11 V → 5 V 105 mV
VDO(VIN-SYS) VIN pin to SYS pin dropout voltage
VVIN – VSYS 		ISYS = 150 mA (including IBAT)
VVIN = 4.35 V
VBAT = 3.6 V		 350 mV
VDO(BAT-SYS) BAT pin to SYS pin dropout voltage
VBAT – VSYS 		ISYS = 100 mA
VVIN = 0 V
VBAT > 3 V		 150 mV
IVIN(MAX) Maximum power path input current at pin VIN VVIN = 5 V 200 mA
VSUP(ENT) Enter battery supplement mode VSYS ≤ (VBAT - 40 mV) V
VSUP(EXIT) Exit battery supplement mode VSYS ≥ (VBAT - 20 mV) V
VSUP(SC) Output short-circuit limit in supplement mode 250 mV
VO(SC) Output short-circuit detection threshold, power-on 0.9 V

BATTERY CHARGER
ICC Active supply current into VIN pin VVIN = 5 V
No load on SYS pin
VBAT > VBAT(REG) 		2 mA
IBAT(SC) Source current for BAT pin short-circuit detection 1 mA
VBAT(SC) BAT pin short-circuit detection threshold 1.6 1.8 2.0 V
VBAT(REG) Battery charger output voltage –1% 4.20 1% V
VLOWV Pre-charge to fast-charge transition threshold 2.9 3.0 3.1 V
ICHG Charger fast charge current range
ICHG = KISET / RISET 		VVIN = 5 V
VBAT(REG) > VBAT > VLOWV 		5 100 mA
KISET Battery fast charge current set factor
ICHG = KISET / RISET 		VVIN = 5 V
IVIN(MAX) > ICHG
ICHG = 100 mA
No load on SYS pin, thermal loop not active.		 –20% 450 20% AΩ
IPRECHG Pre-charge current 0.07 × ICHG 0.10 × ICHG 0.15 × ICHG mA
ITERM Charge current value for termination detection threshold ICHG = 100 mA 7 10 15 mA
VRCH Recharge detection threshold VBAT below nominal charger voltage, VBAT(REG) 55 100 170 mV
IBAT(DET) Sink current for battery detection 1 mA
tCHG Charge safety timer
(18000 seconds = 5 hours)		 18000 s
tPRECHG Pre-charge timer
(1800 seconds = 30 minutes)		 1800 s
VDPPM DPPM threshold VBAT + 100 mV V
ILEAK(nCHG) Leakage current for nCHG_STAT pin VnCHG_STAT = 4.2 V
CHG_EN = LOW (Charger disabled)		 100 nA
RDSON(nCHG) On resistance for nCHG_STAT MOSFET switch 20 60 Ω
IMAX(nCHG) Maximum input current to nCHG_STAT pin 50 mA

BATTERY CHARGER NTC MONITOR
ITSBIAS TS pin bias current 75 µA
VCOLD 0°C charge threshold for 10-kΩ NTC
(β = 3490)		 2100 mV
VHYS(COLD) Low temperature threshold hysteresis Battery charging and battery / NTC temperature increasing 300 mV
VHOT 50°C charge threshold for 10-kΩ NTC
(β = 3490)		 300 mV
VHYS(HOT) High temperature threshold hysteresis Battery charging and battery / NTC temperature decreasing 30 mV

BATTERY CHARGER THERMAL REGULATION
TJ(REG_LOWER) Charger lower thermal regulation limit 75 °C
TJ(REG_UPPER) Charger upper thermal regulation limit 95 °C
TJ(OFF) Charger thermal shutdown temperature 105 °C
TJ(OFF-HYS) Charger thermal shutdown hysteresis 20 °C

LDO
IMAX(LDO) Maximum LDO output current, VVLDO = 2.2 V VSYS = 4.2 V
VVIN = 0 V
VLDO_SET = 0 V		 30 mA
Maximum LDO output current, VVLDO = 3.0 V VSYS = 4.2 V
VVIN = 0 V
VLDO_SET = VSYS 		30 mA
ISC(LDO) Short circuit current limit 30 100 mA
VVLDO LDO output voltage VLDO_SET = LOW
(VLDO_SET pin connected to DGND)
3.7 V ≤ VVIN ≤ 6.5 V
ILOAD(LDO) = –10 mA		 2.13 2.2 2.27 V
VVLDO LDO output voltage VLDO_SET = HIGH
(VVLDO_SET = VSYS)
3.7 V ≤ VVIN ≤ 6.5 V
ILOAD(LDO) = –10 mA		 2.91 3.0 3.09 V
VDO(LDO) LDO Dropout voltage VVIN - VLDO when in dropout
ILOAD(LDO) = –10 mA		 200 mV
Line regulation 3.7 V ≤ VVIN ≤ 6.5 V
ILOAD(LDO) = –10 mA		 –1% 1%
Load regulation VVIN = 3.5 V
0.1 mA ≤ ILOAD(LDO) ≤ –10 mA		 –2% 2%
PSRR Power supply rejection ratio at 20 KHz, ILOAD(LDO) = 10 mA
VDO(LDO) = 0.5 V
CVLDO = 10 µF		 45 dB

BOOST CONVERTER
IQ(BST) Boost operating quiescent current Boost Enabled, BST_EN = High
IOUT(BST) = 0 mA
(boost is not switching)
VBAT = 3.6 V		 2 4.5 µA
RDSON(BST) Boost MOSFET switch on-resistance VIN(BST) = 2.5 V
ISW(MAIN) = 200 mA		 0.8 1.2 Ω
ILKG(BST_SW) Leakage into BST_SW pin
(includes leakage into analog h-bridge switches)		 BST_EN signal = LOW (Boost disabled)
VBST_SW = 4.2 V
No load on BST_OUT pin		 90 nA
ISWLIM(BST) Boost MOSFET switch current limit 100 150 200 mA
VDIODE(BST) Voltage across integrated boost diode during normal operation BST_EN signal = HIGH
VBST_SW = 16.0 V
IBST_OUT = –2 mA		 1.0 V
VREF(BST) Boost reference voltage on BST_FB pin 1.17 1.2 1.23 V
VREFHYS(BST) Boost reference voltage hysteresis on BST_FB pin 2% 2.5% 3.2%
TON(BST) Maximum on time detection threshold 5 6.5 8 µs
TOFF(BST) Minimum off time detection threshold 1.4 1.75 2.1 µs
TSHUT(BST) Boost thermal shutdown threshold 105 °C
TSHUT-HYS(BST) Boost thermal shutdown threshold hysteresis 20 °C

FULL H-BRIDGE ANALOG SWITCHES
IQ(HSW) Operating quiescent current for h-bridge switches 5 µA
RDSON(HSW) H-bridge switches on resistance 20 40 Ω
TDELAY(HSW-H) H-bridge switch propagation delay, input switched from low to high state. VHBxy = 0 V → VVLDO 100 ns
TDELAY(HSW-L) H-bridge switch propagation delay, input switched from high to low state. VHBxy = VVLDO → 0 V 100 ns
POWER MANAGEMENT CORE CONTROLLER
VIL(PMIC) Low logic level for logic signals on power management core
(BST_EN, CHG_EN, SLEEP, HBR1, HBR2, HBL1, HBL2)		 IO logic level decreasing:
VSYS → 0 V
IIN = 1 mA		 0.4 V
VIH(PMIC) High logic level for signals on power management core
(BST_EN, CHG_EN, SLEEP, HBR1, HBR2, HBL1, HBL2)		 IO logic level increasing:
0 V → VSYS
IIN = 1 mA		 1.2 V
VGOOD(LDO) Power fault detection threshold VVLDO decreasing 1.96 V
VGOOD_HYS(LDO) Power fault detection hysteresis VVLDO increasing 50 mV
VBATCOMP COMP pin voltage (scaled down battery voltage) VBAT = 4.2 V
VVLDO = 2.2 V		 1.85 V
VBAT = 2.5 V
VVLDO = 2.2 V		 1.10
VBAT = 4.2 V
VVLDO = 3.0 V		 1.90
VBAT = 3.3 V
VVLDO = 3.0 V		 1.50

4.7 Quiescent Current

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IQ(SLEEP) Power management core quiescent current in sleep mode at 25° C
VBAT = 3.6 V
VVIN = 0 V
No load on LDO
CHG_EN, BST_EN grounded
BST_FB = 300 mV
Power management core in sleep mode / device 'off'		 8.6 10.5 µA
IQ(ACTIVE) Power management core quiescent current in active mode at 25° C
VBAT = 3.6 V
VVIN = 0 V
Boost enabled but not switching, H-bridge in grounded state
No load on LDO
Power management core in active mode		 39 53.5 µA

4.8 Typical Characteristics

TPS65735 startup_lvu418.gif
VIN = 5 V 15-mA Load on LDO 1-mA Load on Boost
Figure 4-1 Startup
TPS65735 shutdown_lvu418.gif
VIN = 5 V 15-mA Load on LDO 1-mA Load on Boost
Figure 4-2 Shutdown