JAJSF73S June   2010  – August 2018 TPS65911

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison Table
  4. 4Pin Configuration and Functions
    1. 4.1 Pin Attributes
      1.      Pin Attributes
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: I/O Pullup and Pulldown
    6. 5.6  Electrical Characteristics: Digital I/O Voltage
    7. 5.7  Electrical Characteristics: Power Consumption
    8. 5.8  Electrical Characteristics: Power References and Thresholds
    9. 5.9  Electrical Characteristics: Thermal Monitoring and Shutdown
    10. 5.10 Electrical Characteristics: 32-kHz RTC Clock
    11. 5.11 Electrical Characteristics: Backup Battery Charger
    12. 5.12 Electrical Characteristics: VRTC LDO
    13. 5.13 Electrical Characteristics: VIO SMPS
    14. 5.14 Electrical Characteristics: VDD1 SMPS
    15. 5.15 Electrical Characteristics: VDD2 SMPS
    16. 5.16 Electrical Characteristics: VDDCtrl SMPS
    17. 5.17 Electrical Characteristics: LDO1 and LDO2
    18. 5.18 Electrical Characteristics: LDO3 and LDO4
    19. 5.19 Electrical Characteristics: LDO5
    20. 5.20 Electrical Characteristics: LDO6, LDO7, and LDO8
    21. 5.21 Timing and Switching Characteristics
      1. 5.21.1 I2C Timing and Switching
      2. 5.21.2 Switch-ON and Switch-OFF Sequences and Timing
      3. 5.21.3 Power Control Timing
        1. 5.21.3.1 Device State Control Through PWRON Signal
        2. 5.21.3.2 Device SLEEP State Control
        3. 5.21.3.3 Device Turnon and Turnoff With Rising and Falling Input Voltage
        4. 5.21.3.4 Power Supplies State Control Through EN1 and EN2 Signals
        5. 5.21.3.5 VDD1, VDD2 Voltage Control Through EN1 and EN2 Signals
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Power Reference
    4. 6.4  Power Resources
    5. 6.5  Embedded Power Controller (EPC)
      1. 6.5.1 State Machine
        1. 6.5.1.1 Device POWER ON Enable Conditions
        2. 6.5.1.2 Device POWER ON Disable Conditions
        3. 6.5.1.3 Device SLEEP Enable Conditions
        4. 6.5.1.4 Device Reset Scenarios
      2. 6.5.2 BOOT Configuration, Switch-ON, and Switch-OFF Sequences
      3. 6.5.3 Control Signals
        1. 6.5.3.1  SLEEP
        2. 6.5.3.2  PWRHOLD
        3. 6.5.3.3  BOOT1
        4. 6.5.3.4  NRESPWRON, NRESPWRON2
        5. 6.5.3.5  CLK32KOUT
        6. 6.5.3.6  PWRON
        7. 6.5.3.7  INT1
        8. 6.5.3.8  EN2 and EN1
        9. 6.5.3.9  GPIO0 to GPIO8
        10. 6.5.3.10 HDRST Input
        11. 6.5.3.11 PWRDN
        12. 6.5.3.12 Comparators: COMP1 and COMP2
        13. 6.5.3.13 Watchdog
        14. 6.5.3.14 Tracking LDO
    6. 6.6  PWM and LED Generators
    7. 6.7  Dynamic Voltage Frequency Scaling and Adaptive Voltage Scaling Operation
    8. 6.8  32-kHz RTC Clock
    9. 6.9  Real Time Clock (RTC)
      1. 6.9.1 Time Calendar Registers
      2. 6.9.2 General Registers
      3. 6.9.3 Compensation Registers
    10. 6.10 Backup Battery Management
    11. 6.11 Backup Registers
    12. 6.12 I2C Interface
      1. 6.12.1 Access Protocols
        1. 6.12.1.1 Single Byte Access
        2. 6.12.1.2 Multiple Byte Access to Several Adjacent Registers
    13. 6.13 Thermal Monitoring and Shutdown
    14. 6.14 Interrupts
    15. 6.15 Register Maps
      1. 6.15.1 Functional Registers
        1. 6.15.1.1 TPS65911_FUNC_REG Registers Mapping Summary
        2. 6.15.1.2 TPS65911_FUNC_REG Register Descriptions
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 External Component Recommendation
        2. 7.2.2.2 Controller Design Procedure
          1. 7.2.2.2.1 Inductor Selection
          2. 7.2.2.2.2 Selecting the RTRIP Resistor
          3. 7.2.2.2.3 Selecting the Output Capacitors
          4. 7.2.2.2.4 Selecting FETs
          5. 7.2.2.2.5 Bootstrap Capacitor
          6. 7.2.2.2.6 Selecting Input Capacitors
        3. 7.2.2.3 Converter Design Procedure
          1. 7.2.2.3.1 Selecting the Inductor
          2. 7.2.2.3.2 Selecting Output Capacitors
          3. 7.2.2.3.3 Selecting Input Capacitors
      3. 7.2.3 Application Curves
      4. 7.2.4 Layout Guidelines
        1. 7.2.4.1 PCB Layout
      5. 7.2.5 Layout Example
    3. 7.3 Power Supply Recommendations
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 デバイス・サポート
      1. 8.1.1 開発サポート
      2. 8.1.2 デバイスの項目表記
    2. 8.2 ドキュメントのサポート
      1. 8.2.1 関連資料
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 コミュニティ・リソース
      1. 8.4.1 Community Resources
    5. 8.5 商標
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 Glossary
  9. 9メカニカル、パッケージ、および注文情報
    1. 9.1 パッケージの説明

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.15 Electrical Characteristics: VDD2 SMPS

Over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage on VCC2 and VCC7 (VIN) VOUT ≤ 2.7 V 2.7 5.5 V
VOUT > 2.7 V VOUT 5.5
DC output voltage (VOUT) VGAIN_SEL = 00,
IOUT = 0 to IOUTmax 		Max programmable voltage, SEL[6:0] = 1001011 1.5 V
SEL[6:0] = 0110011 –3% 1.2 3%
Min programmable voltage, SEL[6:0] = 0000011 0.6
SEL[6:0] = 000000: power down 0
VGAIN_SEL = 10,
SEL = 0101011 = 43		 –3% 2.2 3%
VGAIN_SEL = 11, SEL = 0101011 = 43 –3% 3.3 3%
DC output maximum voltage maximum value 3.3 V
DC output voltage programmable step (VOUTSTEP) VGAIN_SEL = 00, 72 steps 12.5 mV
Rated output current IOUTmax VDD2 output voltage = 0.6 to 1.5 V 1500 mA
VDD2 output voltage = 2.2 V 1200
VDD2 output voltage = 3.2 V 1200
P-channel MOSFET VIN = VINmin 300 mΩ
On-resistance (RDS(ON)_PMOS) VIN = 3.8 V 250 400 mΩ
P-channel leakage current (ILK_PMOS) VIN = VINmax, SW2 = 0 V 2 µA
N-channel MOSFET VIN = VMIN 300 mΩ
On-resistance (RDS(ON)_NMOS) VIN = 3.8 V 250 400 mΩ
N-channel leakage current (ILK_NMOS) VIN = VINmax, SW2 = VINmax 2 µA
PMOS current limit (high-side) VIN = VINmin to VINmax, source current load 1800 mA
NMOS current limit (low-side) VIN = VINmin to VINmax, source current load 1800 mA
VIN = VINmin to VINmax, sink current load 1800
DC load regulation On mode, VIN = VINmin to VINmax at IOUT = 1500 mA
VDD2 output voltage = 0.6 to 1.5V		 20 mV
On mode, VIN = VINmin to VINmax at IOUT = 1200 mA
VDD2 output voltage = 2.2 to 3.3 V		 30
DC line regulation On mode, VIN = VINmin to VINmax at IOUT = 1500 mA
VDD2 output voltage = 0.6 to 1.5V		 20 mV
On mode, VIN = VINmin to VINmax at IOUT = 1200 mA
VDD2 output voltage = 2.2 to 3.3 V		 30
Transient load regulation VIN = 3.8 V, VOUT = 1.2 V
IOUT = 0 to 500 mA , Maximum slew = 100 mA/µs
IOUT = 700 mA to 1.2 A , Maximum slew = 100 mA/µs		 50 mV
Turnon time (ton) Off to on IOUT = 200 mA 350 µs
Output voltage transition rate From VOUT = 0.6 V to 1.5 V
and VOUT = 1.5 V to 0.6 V
IOUT = 500 mA		 TSTEP[2:0] = 001 12.5 mV/µs
TSTEP[2:0] = 011 (default) 7.5
TSTEP[2:0] = 111 2.5
Overshoot SMPS turned on 3%
Power-save mode ripple voltage PFM (pulse skip mode), IOUT = 1 mA 0.025 × VOUT VPP
Switching frequency 2.7 3 3.3 MHz
Duty cycle 100%
Minimum on time
P-Channel MOSFET		 35 ns
Discharge resistor for power-down sequence (RDIS) 30 50 Ω
VFB2 internal resistance 0.5 1 MΩ
Ground current (IQ) Off 1 µA
PWM mode, IOUT = 0 mA, VIN = 3.8 V, VDD2_PSKIP = 0 7500
PFM (pulse skipping) mode, no switching 78
Low-power (pulse skipping) mode, no switching ST[1:0] = 11 63
Conversion efficiency PWM mode, DCRL < 50 mΩ, VOUT = 1.2 V, VIN = 3.6 V IOUT = 10 mA 35%
IOUT = 100 mA 78%
IOUT = 400 mA 80%
IOUT = 800 mA 74%
IOUT = 1200 mA 66%
IOUT = 1500 mA 62%
PFM mode, DCRL < 50 mΩ, VOUT = 1.2 V, VIN = 3.6 V IOUT = 1 mA 59%
IOUT = 10 mA 70%
IOUT = 400 mA 80%
PWM mode, DCRL < 50 mΩ, VOUT = 3.3 V, VIN = 5 V IOUT = 10 mA 39%
IOUT = 100 mA 85%
IOUT = 400 mA 91%
IOUT = 800 mA 90%
IOUT = 1200 mA 86%
PFM mode, DCRL < 50 mΩ, VOUT = 3.3 V, VIN = 5 V IOUT = 1 mA 80%
IOUT = 10 mA 82%
IOUT = 400 mA 92%