JAJSF73S June   2010  – August 2018 TPS65911

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison Table
  4. 4Pin Configuration and Functions
    1. 4.1 Pin Attributes
      1.      Pin Attributes
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: I/O Pullup and Pulldown
    6. 5.6  Electrical Characteristics: Digital I/O Voltage
    7. 5.7  Electrical Characteristics: Power Consumption
    8. 5.8  Electrical Characteristics: Power References and Thresholds
    9. 5.9  Electrical Characteristics: Thermal Monitoring and Shutdown
    10. 5.10 Electrical Characteristics: 32-kHz RTC Clock
    11. 5.11 Electrical Characteristics: Backup Battery Charger
    12. 5.12 Electrical Characteristics: VRTC LDO
    13. 5.13 Electrical Characteristics: VIO SMPS
    14. 5.14 Electrical Characteristics: VDD1 SMPS
    15. 5.15 Electrical Characteristics: VDD2 SMPS
    16. 5.16 Electrical Characteristics: VDDCtrl SMPS
    17. 5.17 Electrical Characteristics: LDO1 and LDO2
    18. 5.18 Electrical Characteristics: LDO3 and LDO4
    19. 5.19 Electrical Characteristics: LDO5
    20. 5.20 Electrical Characteristics: LDO6, LDO7, and LDO8
    21. 5.21 Timing and Switching Characteristics
      1. 5.21.1 I2C Timing and Switching
      2. 5.21.2 Switch-ON and Switch-OFF Sequences and Timing
      3. 5.21.3 Power Control Timing
        1. 5.21.3.1 Device State Control Through PWRON Signal
        2. 5.21.3.2 Device SLEEP State Control
        3. 5.21.3.3 Device Turnon and Turnoff With Rising and Falling Input Voltage
        4. 5.21.3.4 Power Supplies State Control Through EN1 and EN2 Signals
        5. 5.21.3.5 VDD1, VDD2 Voltage Control Through EN1 and EN2 Signals
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Power Reference
    4. 6.4  Power Resources
    5. 6.5  Embedded Power Controller (EPC)
      1. 6.5.1 State Machine
        1. 6.5.1.1 Device POWER ON Enable Conditions
        2. 6.5.1.2 Device POWER ON Disable Conditions
        3. 6.5.1.3 Device SLEEP Enable Conditions
        4. 6.5.1.4 Device Reset Scenarios
      2. 6.5.2 BOOT Configuration, Switch-ON, and Switch-OFF Sequences
      3. 6.5.3 Control Signals
        1. 6.5.3.1  SLEEP
        2. 6.5.3.2  PWRHOLD
        3. 6.5.3.3  BOOT1
        4. 6.5.3.4  NRESPWRON, NRESPWRON2
        5. 6.5.3.5  CLK32KOUT
        6. 6.5.3.6  PWRON
        7. 6.5.3.7  INT1
        8. 6.5.3.8  EN2 and EN1
        9. 6.5.3.9  GPIO0 to GPIO8
        10. 6.5.3.10 HDRST Input
        11. 6.5.3.11 PWRDN
        12. 6.5.3.12 Comparators: COMP1 and COMP2
        13. 6.5.3.13 Watchdog
        14. 6.5.3.14 Tracking LDO
    6. 6.6  PWM and LED Generators
    7. 6.7  Dynamic Voltage Frequency Scaling and Adaptive Voltage Scaling Operation
    8. 6.8  32-kHz RTC Clock
    9. 6.9  Real Time Clock (RTC)
      1. 6.9.1 Time Calendar Registers
      2. 6.9.2 General Registers
      3. 6.9.3 Compensation Registers
    10. 6.10 Backup Battery Management
    11. 6.11 Backup Registers
    12. 6.12 I2C Interface
      1. 6.12.1 Access Protocols
        1. 6.12.1.1 Single Byte Access
        2. 6.12.1.2 Multiple Byte Access to Several Adjacent Registers
    13. 6.13 Thermal Monitoring and Shutdown
    14. 6.14 Interrupts
    15. 6.15 Register Maps
      1. 6.15.1 Functional Registers
        1. 6.15.1.1 TPS65911_FUNC_REG Registers Mapping Summary
        2. 6.15.1.2 TPS65911_FUNC_REG Register Descriptions
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 External Component Recommendation
        2. 7.2.2.2 Controller Design Procedure
          1. 7.2.2.2.1 Inductor Selection
          2. 7.2.2.2.2 Selecting the RTRIP Resistor
          3. 7.2.2.2.3 Selecting the Output Capacitors
          4. 7.2.2.2.4 Selecting FETs
          5. 7.2.2.2.5 Bootstrap Capacitor
          6. 7.2.2.2.6 Selecting Input Capacitors
        3. 7.2.2.3 Converter Design Procedure
          1. 7.2.2.3.1 Selecting the Inductor
          2. 7.2.2.3.2 Selecting Output Capacitors
          3. 7.2.2.3.3 Selecting Input Capacitors
      3. 7.2.3 Application Curves
      4. 7.2.4 Layout Guidelines
        1. 7.2.4.1 PCB Layout
      5. 7.2.5 Layout Example
    3. 7.3 Power Supply Recommendations
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 デバイス・サポート
      1. 8.1.1 開発サポート
      2. 8.1.2 デバイスの項目表記
    2. 8.2 ドキュメントのサポート
      1. 8.2.1 関連資料
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 コミュニティ・リソース
      1. 8.4.1 Community Resources
    5. 8.5 商標
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 Glossary
  9. 9メカニカル、パッケージ、および注文情報
    1. 9.1 パッケージの説明

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.18 Electrical Characteristics: LDO3 and LDO4

Over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage on VCC5 (VIN) VOUT (LDO3) = 1.8 V and VOUT (LDO4) = 1.8 V or 1.1 V or 1.0 V 2.7 5.5 V
VOUT (LDO3) = 2.6 V and VOUT (LDO4) = 2.5 V 3.0 5.5
VOUT (LDO3) = 2.8 V 3.2 5.5
LDO3
DC output voltage (VOUT) On and low-power mode, VOUT = 1.0 to 3.3 V,
VIN = VINmin to VINmax 		SEL[6:2] = 00010 1 V
SEL[6:2] = 00011 1.1
... –3% ... 3%
SEL[6:2] = 11000 3.2
SEL[6:2] = 11001 3.3
Rated output current (IOUTmax) On mode 200 mA
Low-power mode 1
Load current limitation (short-circuit protection) On mode, VOUT = VOUTmin – 100 mV 400 550 650 mA
Dropout voltage (VDO) On mode, VOUTtyp = 3.3 V, VDO = VIN – VOUT,
VIN = 3.6 V, IOUT = IOUTmax 		150 250 mV
DC load regulation On mode, IOUT = IOUTmax to 0 10 mV
DC line regulation On mode, VIN = VINmin to VINmax at IOUT = IOUTmax 4 mV
Transient load regulation On mode, VIN = 2.7 V, VOUTtyp = 1.8 V
IOUT = 0.1 × IOUTmax to 0.9 × IOUTmax in 5 µs and
IOUT = 0.9 × IOUTmax to 0.1 × IOUTmax in 5 µs		 15 22 mV
Transient line regulation On mode, VOUTtyp = 1.8V, IOUT = IOUTmax,
VIN = VINmin + 0.5 V to VINmin in 30 µs
and VIN = VINmin to VINmin + 0.5 V in 30 µs, IOUT = IOUTmax 		0.5 1 mV
Turnon time VOUT = (1 to 1.8 V), at IOUT = 0
measured from VOUT = 0.1 V up to 97% of VOUT 		30 150 µs
VOUT = (1.9 to 3.3 V), at IOUT = 0
measured from VOUT = 0.1 V up to 97% of VOUT 		50 200
Turnon inrush current 200 450 mA
Ripple rejection VIN = VINDC + 100 mVpp tone,
VINDC+ = 3.8 V,
IOUT = IOUTmax / 2		 ƒ = 217 Hz 70 dB
ƒ = 50 Hz 40
LDO3 internal resistance LDO off 500 kΩ
Ground current On mode, IOUT = 0 65 76 µA
On mode, IOUT = IOUTmax 2000
Low-power mode 14 22
Off mode 1
LDO4
DC output voltage (VOUT) On and low-power mode, VIN = VINmin to VINmax(1) SEL[7:2] = 000000 0.8
SEL[7:2] = 000001 0.85
SEL[7:2] = 000010 0.9
SEL[7:2] = 000011 0.95
SEL[7:2] = 000100 1 V
SEL[7:2] = 000101 1.05
... –3% ... 3%
SEL[7:2] = 110001 3.25
SEL[7:2] = 110010 3.3
Rated output current (IOUTmax) On mode 50 mA
Low-power mode 1
Load current limitation (short-circuit protection) On mode, VOUT = VOUTmin – 100 mV 200 400 500 mA
Dropout voltage (VDO) On mode, VOUTtyp = 2.5 V, VDO = VIN – VOUT
VIN = 3.6 V, IOUT = IOUTmax 		100 160 mV
DC load regulation On mode, IOUT = IOUTmax to 0 5 mV
DC line regulation On mode, VIN = VINmin to VINmax at IOUT = IOUTmax 4 mV
Transient load regulation On mode, VIN = 2.7 V, VOUTtyp = 1.8 V
IOUT = 0.1 × IOUTmax to 0.9 × IOUTmax in 5 µs
and IOUT = 0.9 × IOUTmax to 0.1 × IOUTmax in 5 µs		 6 10 mV
Transient line regulation On mode, VIN = VINmin + 0.5 V to VINmin in 30 µs
and VIN = VINmin to VINmin + 0.5 V in 30 µs, IOUT = IOUTmax / 2		 0.2 1 mV
Turnon time VOUT = (1 to 1.8 V), at IOUT = 0
measured from VOUT = 0.1 V up to 97% of VOUT 		30 150 µs
VOUT = (1.9 to 3.3 V), at IOUT = 0
measured from VOUT = 0.1 V up to 97% of VOUT 		50 200
Ripple rejection VIN = VINDC + 100 mVpp tone,
VINDC+= 3.8 V,
IOUT = IOUTmax / 2		 ƒ = 217 Hz 70 dB
ƒ = 50 kHz 40
LDO4 internal resistance LDO off 500 kΩ
Ground current On mode, IOUT = 0 55 65 µA
On mode, IOUT = IOUTmax 900
Low-power mode 14 17
Off mode 1
(1) Set DCDCCTRL_REG.TRACK=1 and disable VDD1 to achieve VOUT < 1 V.