JAJSF73S June   2010  – August 2018 TPS65911

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison Table
  4. 4Pin Configuration and Functions
    1. 4.1 Pin Attributes
      1.      Pin Attributes
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: I/O Pullup and Pulldown
    6. 5.6  Electrical Characteristics: Digital I/O Voltage
    7. 5.7  Electrical Characteristics: Power Consumption
    8. 5.8  Electrical Characteristics: Power References and Thresholds
    9. 5.9  Electrical Characteristics: Thermal Monitoring and Shutdown
    10. 5.10 Electrical Characteristics: 32-kHz RTC Clock
    11. 5.11 Electrical Characteristics: Backup Battery Charger
    12. 5.12 Electrical Characteristics: VRTC LDO
    13. 5.13 Electrical Characteristics: VIO SMPS
    14. 5.14 Electrical Characteristics: VDD1 SMPS
    15. 5.15 Electrical Characteristics: VDD2 SMPS
    16. 5.16 Electrical Characteristics: VDDCtrl SMPS
    17. 5.17 Electrical Characteristics: LDO1 and LDO2
    18. 5.18 Electrical Characteristics: LDO3 and LDO4
    19. 5.19 Electrical Characteristics: LDO5
    20. 5.20 Electrical Characteristics: LDO6, LDO7, and LDO8
    21. 5.21 Timing and Switching Characteristics
      1. 5.21.1 I2C Timing and Switching
      2. 5.21.2 Switch-ON and Switch-OFF Sequences and Timing
      3. 5.21.3 Power Control Timing
        1. 5.21.3.1 Device State Control Through PWRON Signal
        2. 5.21.3.2 Device SLEEP State Control
        3. 5.21.3.3 Device Turnon and Turnoff With Rising and Falling Input Voltage
        4. 5.21.3.4 Power Supplies State Control Through EN1 and EN2 Signals
        5. 5.21.3.5 VDD1, VDD2 Voltage Control Through EN1 and EN2 Signals
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Power Reference
    4. 6.4  Power Resources
    5. 6.5  Embedded Power Controller (EPC)
      1. 6.5.1 State Machine
        1. 6.5.1.1 Device POWER ON Enable Conditions
        2. 6.5.1.2 Device POWER ON Disable Conditions
        3. 6.5.1.3 Device SLEEP Enable Conditions
        4. 6.5.1.4 Device Reset Scenarios
      2. 6.5.2 BOOT Configuration, Switch-ON, and Switch-OFF Sequences
      3. 6.5.3 Control Signals
        1. 6.5.3.1  SLEEP
        2. 6.5.3.2  PWRHOLD
        3. 6.5.3.3  BOOT1
        4. 6.5.3.4  NRESPWRON, NRESPWRON2
        5. 6.5.3.5  CLK32KOUT
        6. 6.5.3.6  PWRON
        7. 6.5.3.7  INT1
        8. 6.5.3.8  EN2 and EN1
        9. 6.5.3.9  GPIO0 to GPIO8
        10. 6.5.3.10 HDRST Input
        11. 6.5.3.11 PWRDN
        12. 6.5.3.12 Comparators: COMP1 and COMP2
        13. 6.5.3.13 Watchdog
        14. 6.5.3.14 Tracking LDO
    6. 6.6  PWM and LED Generators
    7. 6.7  Dynamic Voltage Frequency Scaling and Adaptive Voltage Scaling Operation
    8. 6.8  32-kHz RTC Clock
    9. 6.9  Real Time Clock (RTC)
      1. 6.9.1 Time Calendar Registers
      2. 6.9.2 General Registers
      3. 6.9.3 Compensation Registers
    10. 6.10 Backup Battery Management
    11. 6.11 Backup Registers
    12. 6.12 I2C Interface
      1. 6.12.1 Access Protocols
        1. 6.12.1.1 Single Byte Access
        2. 6.12.1.2 Multiple Byte Access to Several Adjacent Registers
    13. 6.13 Thermal Monitoring and Shutdown
    14. 6.14 Interrupts
    15. 6.15 Register Maps
      1. 6.15.1 Functional Registers
        1. 6.15.1.1 TPS65911_FUNC_REG Registers Mapping Summary
        2. 6.15.1.2 TPS65911_FUNC_REG Register Descriptions
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 External Component Recommendation
        2. 7.2.2.2 Controller Design Procedure
          1. 7.2.2.2.1 Inductor Selection
          2. 7.2.2.2.2 Selecting the RTRIP Resistor
          3. 7.2.2.2.3 Selecting the Output Capacitors
          4. 7.2.2.2.4 Selecting FETs
          5. 7.2.2.2.5 Bootstrap Capacitor
          6. 7.2.2.2.6 Selecting Input Capacitors
        3. 7.2.2.3 Converter Design Procedure
          1. 7.2.2.3.1 Selecting the Inductor
          2. 7.2.2.3.2 Selecting Output Capacitors
          3. 7.2.2.3.3 Selecting Input Capacitors
      3. 7.2.3 Application Curves
      4. 7.2.4 Layout Guidelines
        1. 7.2.4.1 PCB Layout
      5. 7.2.5 Layout Example
    3. 7.3 Power Supply Recommendations
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 デバイス・サポート
      1. 8.1.1 開発サポート
      2. 8.1.2 デバイスの項目表記
    2. 8.2 ドキュメントのサポート
      1. 8.2.1 関連資料
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 コミュニティ・リソース
      1. 8.4.1 Community Resources
    5. 8.5 商標
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 Glossary
  9. 9メカニカル、パッケージ、および注文情報
    1. 9.1 パッケージの説明

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5.2 BOOT Configuration, Switch-ON, and Switch-OFF Sequences

The power sequence is the automated switch-on of the devices resources when an OFF-to-ACTIVE transition occurs. The power-on sequence has 15 sequential time slots to which resources (DC-DC converters, LDOs, 32-kHz clock, GPIO0, GPIO2, GPIO6, GPIO7) can be assigned. The time slot length can be selected to be 0.5 ms or 2 ms. If a resource is not assigned to any time slot, it will be in off mode after the power-on sequence and the voltage level can be changed through the register SEL bits before enabling the resource.

Power off disables all power resources at the same time by default. By setting the PWR_OFF_SEQ control bit to 1, power off will follow the power-up sequence in reverse order (the first resource to be powered on will be last to power off).

The values of VDD1, VDD2, and VDDCtrl set in the boot sequence can be selected from 16 steps. For the whole range, 100-mV steps are available: 0.6/0.7...1.4/1.5 V. From 0.8 to 1.4 V, additional values with
50-mV step resolution can be set: 0.85/1.05...1.35 V.

For LDO1, LDO2, and LDO4 all levels from 1.0 to 3.3 V are selectable in the boot sequence with 50-mV steps. For other LDOs, the level is selectable with 100-mV steps, from 1.0 to 3.3 V.

The device supports three boot configurations, which define the power sequence and several device control bits. The boot configuration is selectable by the device BOOT1 pin.

BOOT1 BOOT CONFIGURATION
Floating Test boot mode
0 Fixed boot mode
1 EEPROM boot mode

The BOOT1 input pad is disabled after the boot mode is read at power up, to save power.

Table 6-2 and Table 6-3 describe the power sequence and general control bits defined in the boot sequence, respectively.

Fixed boot mode is the same in all devices, while EEPROM boot mode is different in each device. For a description of EEPROM boot mode, refer to the user's guide for the selected device. For a list of user's guides, see Section 8.2.1 or the device product folder on ti.com.

Table 6-2 Boot Configuration: Power Sequence Control Bits

REGISTER BIT DESCRIPTION TPS65911
FIXED BOOT EEPROM BOOT
VDD1_OP_REG/
VDD1_SR_REG		 VDD1 voltage level selection for boot. Levels available: 1.2 V x
0.6/0.7/0.8/0.85/0.9/0.95/.../1.35/1.4/1.5 V
VDD1_REG VGAIN_SEL VDD1 gain selection, ×1 or ×2 ×1 x
EEPROM VDD1 time slot selection 3 x
DCDCCTRL_REG VDD1_PSKIP VDD1 pulse skip mode enable Enable skip x
VDD2_OP_REG/
VDD2_SR_REG		 VDD2 voltage level selection for boot. Levels available: 1.5 V x
0.6/0.7/0.8/0.85/0.9/0.95/.../1.35/1.4/1.5 V
VDD2_REG VGAIN_SEL VDD2 gain selection, ×1 or ×3 ×1 x
EEPROM VDD2 time slot selection 6 x
DCDCCTRL_REG VDD2_PSKIP VDD2 pulse skip mode enable Enable skip x
VIO_REG SEL[3:2] VIO voltage selection 1.8 V x
EEPROM VIO time slot selection 4 x
DCDCCTRL_REG VIO_PSKIP VIO pulse skip mode enable Enable skip x
VDDCtrl_OP_REG/
VDDCtrl_SR_REG		 VDDCtrl voltage level selection for boot. Levels available: Off x
0.6/0.7/0.8/0.85/0.9/0.95/../1.35/1.4 V
EEPROM VDDCtrl time slot selection Off x
LDO1_REG SEL[7:2] LDO1 voltage selection 1.05 V x
EEPROM LDO1 time slot Off x
LDO2_REG SEL[7:2] LDO2 voltage selection 1.2 V x
EEPROM LDO2 time slot 7 x
LDO3_REG SEL[6:2] LDO3 voltage selection LDO3 voltage: 1 V x
EEPROM LDO3 time slot Off x
LDO4_REG SEL[7:2] LDO4 voltage selection 1.2 V x
EEPROM LDO4 time slot 2 x
LDO5_REG SEL[6:2] LDO5 voltage selection LDO5 voltage: 1 V x
EEPROM LDO5 time slot Off x
LDO6_REG SEL[6:2] LDO6 voltage selection LDO6 voltage: 1 V x
EEPROM LDO6 time slot Off x
LDO7_REG SEL[6:2] LDO7 voltage selection 1.2 V x
EEPROM LDO7 time slot 5 x
LDO8_REG SEL[6:2] LDO8 voltage selection 1 V x
EEPROM LDO8 time slot 7 x
CLK32KOUT pin CLK32KOUT time slot 5 x
NRESPWRON, NRESPWRON2 pin NRESPWRON time slot 10 x
GPIO0 pin GPIO0 time slot 1 x
GPIO2 pin GPIO2 time slot Off x
GPIO6 pin GPIO6 time slot 6 x
GPIO7 pin GPIO7 time slot 5 x

Table 6-3 Boot Configuration: General Control Bits

REGISTER BIT DESCRIPTION TPS65911
FIXED BOOT EEPROM BOOT
VRTC_REG VRTC_OFFMASK 0: VRTC LDO will be in low-power mode during OFF state. 0 x
1: VRTC LDO will be in full-power mode during OFF state.
DEVCTRL_REG CK32K_CTRL 0: Clock source is crystal/external clock. Crystal x
1: Clock source is internal RC oscillator.
DEVCTRL_REG DEV_ON 0: No impact 0 x
1: Will keep device on, in ACTIVE or SLEEP state
DEVCTRL2_REG TSLOTD Boot sequence time slot duration: 2 ms x
0: 0.5 ms
1: 2 ms
DEVCTRL2_REG PWON_LP_OFF 0: Turn off device after PWRON long-press not allowed. 1 x
1: Turn off device after PWRON long-press.
DEVCTRL2_REG PWON_LP_RST 0: No impact 1 x
1: Reset digital core when device is off
DEVCTRL2_REG IT_POL 0: INT1 signal will be active-low. 0 x
1: INT1 signal will be active-high.
INT_MSK_REG VMBHI_IT_MSK 0: Device will automatically switch-on at NO SUPPLY-to-OFF or BACKUP-to-OFF transition (device will switch-on when supply is inserted) 1 x
1: Start-up reason required before switch-on (VMBHI event interrupt masked)
INT_MSK3_REG GPIO5_F_IT_MSK 0: GPIO5 falling-edge detection interrupt not masked 1 x
1: GPIO5 falling-edge detection interrupt masked
INT_MSK3_REG GPIO5_R_IT_MSK 0: GPIO5 rising-edge detection interrupt not masked 0 x
1: GPIO5 rising-edge detection interrupt masked
INT_MSK3_REG GPIO4_F_IT_MSK 0: GPIO4 falling-edge detection interrupt not masked 1 x
1: GPIO4 falling-edge detection interrupt masked
INT_MSK3_REG GPIO4_R_IT_MSK 0: GPIO4 rising-edge detection interrupt not masked 0 x
1: GPIO4 rising-edge detection interrupt masked
GPIO0_REG GPIO_ODEN 0: GPIO0 configured as push-pull output Push-pull x
1: GPIO0 configured as open-drain output
WATCHDOG_REG WATCHDOG_EN 0: Watchdog disabled 1 x
1: Watchdog enabled, periodic operation with 100 s
EEPROM VMBBUF_BYPASS 0: Enable input buffer for external resistive divider Disable buffer x
1: In single-cell system, disable buffer for low power
VMBCH_REG VMBCH_SEL[5:1] Select threshold for boot gating comparator COMP1, 2.5–3.5 V. 3.1 V x
EEPROM AUTODEV_ON 0: PWRHOLD pin is used as PWRHOLD feature. 1, PWRHOLD pin is GPI x
1: PWRHOLD pin is GPI. After power on, DEV_ON set high internally, no processor action required to keep supplies.
EEPROM PWRDN_POL 0: PWRDN signal will be active-low. Active-low x
1: PWRDN signal will be active-high.