JAJSF73S June   2010  – August 2018 TPS65911

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison Table
  4. 4Pin Configuration and Functions
    1. 4.1 Pin Attributes
      1.      Pin Attributes
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: I/O Pullup and Pulldown
    6. 5.6  Electrical Characteristics: Digital I/O Voltage
    7. 5.7  Electrical Characteristics: Power Consumption
    8. 5.8  Electrical Characteristics: Power References and Thresholds
    9. 5.9  Electrical Characteristics: Thermal Monitoring and Shutdown
    10. 5.10 Electrical Characteristics: 32-kHz RTC Clock
    11. 5.11 Electrical Characteristics: Backup Battery Charger
    12. 5.12 Electrical Characteristics: VRTC LDO
    13. 5.13 Electrical Characteristics: VIO SMPS
    14. 5.14 Electrical Characteristics: VDD1 SMPS
    15. 5.15 Electrical Characteristics: VDD2 SMPS
    16. 5.16 Electrical Characteristics: VDDCtrl SMPS
    17. 5.17 Electrical Characteristics: LDO1 and LDO2
    18. 5.18 Electrical Characteristics: LDO3 and LDO4
    19. 5.19 Electrical Characteristics: LDO5
    20. 5.20 Electrical Characteristics: LDO6, LDO7, and LDO8
    21. 5.21 Timing and Switching Characteristics
      1. 5.21.1 I2C Timing and Switching
      2. 5.21.2 Switch-ON and Switch-OFF Sequences and Timing
      3. 5.21.3 Power Control Timing
        1. 5.21.3.1 Device State Control Through PWRON Signal
        2. 5.21.3.2 Device SLEEP State Control
        3. 5.21.3.3 Device Turnon and Turnoff With Rising and Falling Input Voltage
        4. 5.21.3.4 Power Supplies State Control Through EN1 and EN2 Signals
        5. 5.21.3.5 VDD1, VDD2 Voltage Control Through EN1 and EN2 Signals
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Power Reference
    4. 6.4  Power Resources
    5. 6.5  Embedded Power Controller (EPC)
      1. 6.5.1 State Machine
        1. 6.5.1.1 Device POWER ON Enable Conditions
        2. 6.5.1.2 Device POWER ON Disable Conditions
        3. 6.5.1.3 Device SLEEP Enable Conditions
        4. 6.5.1.4 Device Reset Scenarios
      2. 6.5.2 BOOT Configuration, Switch-ON, and Switch-OFF Sequences
      3. 6.5.3 Control Signals
        1. 6.5.3.1  SLEEP
        2. 6.5.3.2  PWRHOLD
        3. 6.5.3.3  BOOT1
        4. 6.5.3.4  NRESPWRON, NRESPWRON2
        5. 6.5.3.5  CLK32KOUT
        6. 6.5.3.6  PWRON
        7. 6.5.3.7  INT1
        8. 6.5.3.8  EN2 and EN1
        9. 6.5.3.9  GPIO0 to GPIO8
        10. 6.5.3.10 HDRST Input
        11. 6.5.3.11 PWRDN
        12. 6.5.3.12 Comparators: COMP1 and COMP2
        13. 6.5.3.13 Watchdog
        14. 6.5.3.14 Tracking LDO
    6. 6.6  PWM and LED Generators
    7. 6.7  Dynamic Voltage Frequency Scaling and Adaptive Voltage Scaling Operation
    8. 6.8  32-kHz RTC Clock
    9. 6.9  Real Time Clock (RTC)
      1. 6.9.1 Time Calendar Registers
      2. 6.9.2 General Registers
      3. 6.9.3 Compensation Registers
    10. 6.10 Backup Battery Management
    11. 6.11 Backup Registers
    12. 6.12 I2C Interface
      1. 6.12.1 Access Protocols
        1. 6.12.1.1 Single Byte Access
        2. 6.12.1.2 Multiple Byte Access to Several Adjacent Registers
    13. 6.13 Thermal Monitoring and Shutdown
    14. 6.14 Interrupts
    15. 6.15 Register Maps
      1. 6.15.1 Functional Registers
        1. 6.15.1.1 TPS65911_FUNC_REG Registers Mapping Summary
        2. 6.15.1.2 TPS65911_FUNC_REG Register Descriptions
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 External Component Recommendation
        2. 7.2.2.2 Controller Design Procedure
          1. 7.2.2.2.1 Inductor Selection
          2. 7.2.2.2.2 Selecting the RTRIP Resistor
          3. 7.2.2.2.3 Selecting the Output Capacitors
          4. 7.2.2.2.4 Selecting FETs
          5. 7.2.2.2.5 Bootstrap Capacitor
          6. 7.2.2.2.6 Selecting Input Capacitors
        3. 7.2.2.3 Converter Design Procedure
          1. 7.2.2.3.1 Selecting the Inductor
          2. 7.2.2.3.2 Selecting Output Capacitors
          3. 7.2.2.3.3 Selecting Input Capacitors
      3. 7.2.3 Application Curves
      4. 7.2.4 Layout Guidelines
        1. 7.2.4.1 PCB Layout
      5. 7.2.5 Layout Example
    3. 7.3 Power Supply Recommendations
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 デバイス・サポート
      1. 8.1.1 開発サポート
      2. 8.1.2 デバイスの項目表記
    2. 8.2 ドキュメントのサポート
      1. 8.2.1 関連資料
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 コミュニティ・リソース
      1. 8.4.1 Community Resources
    5. 8.5 商標
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 Glossary
  9. 9メカニカル、パッケージ、および注文情報
    1. 9.1 パッケージの説明

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.15.1.2 TPS65911_FUNC_REG Register Descriptions

Table 6-7 SECONDS_REG

Address Offset 0x00
Instance Reset Domain: FULL RESET
Description RTC register for seconds
Type RW
7 6 5 4 3 2 1 0
Reserved SEC1 SEC0
Bits Field Name Description Type Reset
7 Reserved Reserved bit RO
R returns 0s 		0
6:4 SEC1 Second digit of seconds (range is 0 up to 5) RW 0x0
3:0 SEC0 First digit of seconds (range is 0 up to 9) RW 0x0

Table 6-8 MINUTES_REG

Address Offset 0x01
Instance Reset Domain: FULL RESET
Description RTC register for minutes
Type RW
7 6 5 4 3 2 1 0
Reserved MIN1 MIN0
Bits Field Name Description Type Reset
7 Reserved Reserved bit RO
R returns 0s 		0
6:4 MIN1 Second digit of minutes (range is 0 up to 5) RW 0x0
3:0 MIN0 First digit of minutes (range is 0 up to 9) RW 0x0

Table 6-9 HOURS_REG

Address Offset 0x02
Instance Reset Domain: FULL RESET
Description RTC register for hours
Type RW
7 6 5 4 3 2 1 0
PM_NAM Reserved HOUR1 HOUR0
Bits Field Name Description Type Reset
7 PM_NAM Only used in PM_AM mode (otherwise it is set to 0)
0 is AM
1 is PM 		RW 0
6 Reserved Reserved bit RO
R returns 0s 		0
5:4 HOUR1 Second digit of hours(range is 0 up to 2) RW 0x0
3:0 HOUR0 First digit of hours (range is 0 up to 9) RW 0x0

Table 6-10 DAYS_REG

Address Offset 0x03
Instance Reset Domain: FULL RESET
Description RTC register for days
Type RW
7 6 5 4 3 2 1 0
Reserved DAY1 DAY0
Bits Field Name Description Type Reset
7:6 Reserved Reserved bit RO
R returns 0s 		0x0
5:4 DAY1 Second digit of days (range is 0 up to 3) RW 0x0
3:0 DAY0 First digit of days (range is 0 up to 9) RW 0x1

Table 6-11 MONTHS_REG

Address Offset 0x04
Instance Reset Domain: FULL RESET
Description RTC register for months
Type RW
7 6 5 4 3 2 1 0
Reserved MONTH1 MONTH0
Bits Field Name Description Type Reset
7:5 Reserved Reserved bit RO
R returns 0s 		0x0
4 MONTH1 Second digit of months (range is 0 up to 1) RW 0
3:0 MONTH0 First digit of months (range is 0 up to 9) RW 0x1

Table 6-12 YEARS_REG

Address Offset 0x05
Instance Reset Domain: FULL RESET
Description RTC register for day of the week
Type RW
7 6 5 4 3 2 1 0
YEAR1 YEAR0
Bits Field Name Description Type Reset
7:4 YEAR1 Second digit of years (range is 0 up to 9) RW 0x0
3:0 YEAR0 First digit of years (range is 0 up to 9) RW 0x0

Table 6-13 WEEKS_REG

Address Offset 0x06
Instance Reset Domain: FULL RESET
Description RTC register for day of the week
Type RW
7 6 5 4 3 2 1 0
Reserved WEEK
Bits Field Name Description Type Reset
7:3 Reserved Reserved bit RO
R returns 0s 		0x00
2:0 WEEK First digit of day of the week (range is 0 up to 6) RW 0

Table 6-14 ALARM_SECONDS_REG

Address Offset 0x08
Instance Reset Domain: FULL RESET
Description RTC register for alarm programmation for seconds
Type RW
7 6 5 4 3 2 1 0
Reserved ALARM_SEC1 ALARM_SEC0
Bits Field Name Description Type Reset
7 Reserved Reserved bit RO
R returns 0s 		0
6:4 ALARM_SEC1 Second digit of alarm programmation for seconds (range is 0 up to 5) RW 0x0
3:0 ALARM_SEC0 First digit of alarm programmation for seconds (range is 0 up to 9) RW 0x0

Table 6-15 ALARM_MINUTES_REG

Address Offset 0x09
Instance Reset Domain: FULL RESET
Description RTC register for alarm programmation for minutes
Type RW
7 6 5 4 3 2 1 0
Reserved ALARM_MIN1 ALARM_MIN0
Bits Field Name Description Type Reset
7 Reserved Reserved bit RO
R returns 0s 		0
6:4 ALARM_MIN1 Second digit of alarm programmation for minutes (range is 0 up to 5) RW 0x0
3:0 ALARM_MIN0 First digit of alarm programmation for minutes (range is 0 up to 9) RW 0x0

Table 6-16 ALARM_HOURS_REG

Address Offset 0x0A
Instance Reset Domain: FULL RESET
Description RTC register for alarm programmation for hours
Type RW
7 6 5 4 3 2 1 0
ALARM_PM_NAM Reserved ALARM_HOUR1 ALARM_HOUR0
Bits Field Name Description Type Reset
7 ALARM_PM_
NAM		 Only used in PM_AM mode for alarm programmation (otherwise it is set to 0)
0 is AM
1 is PM 		RW 0
6 Reserved Reserved bit RO
R returns 0s		 0
5:4 ALARM_HOUR1 Second digit of alarm programmation for hours(range is 0 up to 2) RW 0x0
3:0 ALARM_HOUR0 First digit of alarm programmation for hours (range is 0 up to 9) RW 0x0

Table 6-17 ALARM_DAYS_REG

Address Offset 0x0B
Instance Reset Domain: FULL RESET
Description RTC register for alarm programmation for days
Type RW
7 6 5 4 3 2 1 0
Reserved ALARM_DAY1 ALARM_DAY0
Bits Field Name Description Type Reset
7:6 Reserved Reserved bit RO
R Special		 0x0
5:4 ALARM_DAY1 Second digit of alarm programmation for days (range is 0 up to 3) RW 0x0
3:0 ALARM_DAY0 First digit of alarm programmation for days (range is 0 up to 9) RW 0x1

Table 6-18 ALARM_MONTHS_REG

Address Offset 0x0C
Instance Reset Domain: FULL RESET
Description RTC register for alarm programmation for months
Type RW
7 6 5 4 3 2 1 0
Reserved ALARM_
MONTH1		 ALARM_MONTH0
Bits Field Name Description Type Reset
7:5 Reserved Reserved bit RO
R returns 0s 		0x0
4 ALARM_MONTH1 Second digit of alarm programmation for months (range is 0 up to 1) RW 0
3:0 ALARM_MONTH0 First digit of alarm programmation for months (range is 0 up to 9) RW 0x1

Table 6-19 ALARM_YEARS_REG

Address Offset 0x0D
Instance Reset Domain: FULL RESET
Description RTC register for alarm programmation for years
Type RW
7 6 5 4 3 2 1 0
ALARM_YEAR1 ALARM_YEAR0
Bits Field Name Description Type Reset
7:4 ALARM_YEAR1 Second digit of alarm programmation for years (range is 0 up to 9) RW 0x0
3:0 ALARM_YEAR0 First digit of alarm programmation for years (range is 0 up to 9) RW 0x0

Table 6-20 RTC_CTRL_REG

Address Offset 0x10
Instance Reset Domain: FULL RESET
Description RTC control register:
NOTES: A dummy read of this register is necessary before each I2C read in order to update the ROUND_30S bit value.
Type RW
7 6 5 4 3 2 1 0
RTC_V_OPT GET_TIME SET_32_
COUNTER		 TEST_MODE MODE_12_24 AUTO_COMP ROUND_30S STOP_RTC
Bits Field Name Description Type Reset
7 RTC_V_OPT RTC date/time register selection:
0: Read access directly to dynamic registers (SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG, MONTHS_REG, YEAR_REG, WEEKS_REG)
1: Read access to static shadowed registers: (see GET_TIME bit). 		RW 0
6 GET_TIME When writing a 1 into this register, the content of the dynamic registers (SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG, MONTHS_REG, YEAR_REG and WEEKS_REG) is transferred into static shadowed registers. Each update of the shadowed registers needs to be done by re-asserting GET_TIME bit to 1 (that is: reset it to 0 and then rewrite it to 1) RW 0
5 SET_32_COUNTER 0: No action
1: set the 32-kHz counter with COMP_REG value.
It must only be used when the RTC is frozen. 		RW 0
4 TEST_MODE 0: functional mode
1: test mode (Auto compensation is enable when the 32-kHz counter reaches at its end) 		RW 0
3 MODE_12_24 0: 24 hours mode
1: 12 hours mode (PM-AM mode)
It is possible to switch between the two modes at any time without disturbed the RTC, read or write are always performed with the current mode. 		RW 0
2 AUTO_COMP 0: No auto compensation
1: Auto compensation enabled 		RW 0
1 ROUND_30S 0: No update
1: When a one is written, the time is rounded to the nearest minute.
This bit is a toggle bit, the microcontroller can only write one and RTC clears it. If the microcontroller sets the ROUND_30S bit and then reads it, the microcontroller will read one until rounded to the nearest value.		 RW 0
0 STOP_RTC 0: RTC is frozen
1: RTC is running 		RW 0

Table 6-21 RTC_STATUS_REG

Address Offset 0x11
Instance Reset Domain: FULL RESET
Description RTC status register:
NOTES: A dummy read of this register is necessary before each I2C read in order to update the status register value.
Type RW
7 6 5 4 3 2 1 0
POWER_UP ALARM EVENT_1D EVENT_1H EVENT_1M EVENT_1S RUN Reserved
Bits Field Name Description Type Reset
7 POWER_UP Indicates that a reset occurred (bit cleared to 0 by writing 1).
POWER_UP is set by a reset, is cleared by writing one in this bit. 		RW 1
6 ALARM Indicates that an alarm interrupt has been generated (bit clear by writing 1).
The alarm interrupt keeps its low level, until the microcontroller write 1 in the ALARM bit of the RTC_STATUS_REG register.
The timer interrupt is a low-level pulse (15 µs duration). 		RW 0
5 EVENT_1D One day has occurred RO 0
4 EVENT_1H One hour has occurred RO 0
3 EVENT_1M One minute has occurred RO 0
2 EVENT_1S One second has occurred RO 0
1 RUN 0: RTC is frozen
1: RTC is running
This bit shows the real state of the RTC, indeed because of STOP_RTC signal was resynchronized on 32-kHz clock, the action of this bit is delayed. 		RO 0
0 Reserved Reserved bit RO
R returns 0s 		0

Table 6-22 RTC_INTERRUPTS_REG

Address Offset 0x12
Instance Reset Domain: FULL RESET
Description RTC interrupt control register
Type RW
7 6 5 4 3 2 1 0
Reserved IT_SLEEP_
MASK_EN		 IT_ALARM IT_TIMER EVERY
Bits Field Name Description Type Reset
7:5 Reserved Reserved bit RO
R returns 0s 		0x0
4 IT_SLEEP_MASK_EN 1: Mask periodic interrupt while the TPS65911 device is in SLEEP mode. Interrupt event is back up in a register and occurred as soon as the TPS65911 device is no more in SLEEP mode.
0: Normal mode, no interrupt masked 		RW 0
3 IT_ALARM Enable one interrupt when the alarm value is reached (TC ALARM registers) by the TC registers RW 0
2 IT_TIMER Enable periodic interrupt
0: interrupt disabled
1: interrupt enabled 		RW 0
1:0 EVERY Interrupt period
00: each second
01: each minute
10: each hour
11: each day 		RW 0x0

Table 6-23 RTC_COMP_LSB_REG

Address Offset 0x13
Instance Reset Domain: FULL RESET
Description RTC compensation register (LSB)
Notes: This register must be written in 2-complement.
This means that to add one 32-kHz oscillator period each hour, microcontroller needs to write FFFF into RTC_COMP_MSB_REG and RTC_COMP_LSB_REG.
To remove one 32-kHz oscillator period each hour, microcontroller needs to write 0001 into RTC_COMP_MSB_REG and RTC_COMP_LSB_REG.
The 7FFF value is forbidden.
Type RW
7 6 5 4 3 2 1 0
RTC_COMP_LSB
Bits Field Name Description Type Reset
7:0 RTC_COMP_LSB This register contains the number of 32-kHz periods to be added into the 32-kHz counter each hour [LSB] RW 0x00

Table 6-24 RTC_COMP_MSB_REG

Address Offset 0x14
Instance Reset Domain: FULL RESET
Description RTC compensation register (MSB)
Notes: See RTC_COMP_LSB_REG Notes.
Type RW
7 6 5 4 3 2 1 0
RTC_COMP_MSB
Bits Field Name Description Type Reset
7:0 RTC_COMP_MSB This register contains the number of 32-kHz periods to be added into the 32-kHz counter each hour [MSB] RW 0x00

Table 6-25 RTC_RES_PROG_REG

Address Offset 0x15
Instance Reset Domain: FULL RESET
Description RTC register containing oscillator resistance value
Type RW
7 6 5 4 3 2 1 0
Reserved SW_RES_PROG
Bits Field Name Description Type Reset
7:6 Reserved Reserved bit RO
R returns 0s 		0x0
5:0 SW_RES_PROG Value of the oscillator resistance RW 0x27

Table 6-26 RTC_RESET_STATUS_REG

Address Offset 0x16
Instance Reset Domain: FULL RESET
Description RTC register for reset status
Type RW
7 6 5 4 3 2 1 0
Reserved RESET_
STATUS
Bits Field Name Description Type Reset
7:1 Reserved Reserved bit RO
R returns 0s 		0x0
0 RESET_STATUS This bit can only be set to one and is cleared when a manual reset or a POR (VBAT < 2.1) occurs. If this bit is reset it means that the RTC has lost its configuration. RW 0

Table 6-27 BCK1_REG

Address Offset 0x17
Instance Reset Domain: FULL RESET
Description Backup register which can be used for storage by the application firmware when the external host is powered down. These registers will retain their content as long as the VRTC is active.
Type RW
7 6 5 4 3 2 1 0
BCKUP
Bits Field Name Description Type Reset
7:0 BCKUP Backup bit RW 0x00

Table 6-28 BCK2_REG

Address Offset 0x18
Instance Reset Domain: FULL RESET
Description Backup register which can be used for storage by the application firmware when the external host is powered down. These registers will retain their content as long as the VRTC is active.
Type RW
7 6 5 4 3 2 1 0
BCKUP
Bits Field Name Description Type Reset
7:0 BCKUP Backup bit RW 0x00

Table 6-29 BCK3_REG

Address Offset 0x19
Instance Reset Domain: FULL RESET
Description Backup register which can be used for storage by the application firmware when the external host is powered down. These registers will retain their content as long as the VRTC is active.
Type RW
7 6 5 4 3 2 1 0
BCKUP
Bits Field Name Description Type Reset
7:0 BCKUP Backup bit RW 0x00

Table 6-30 BCK4_REG

Address Offset 0x1A
Instance Reset Domain: FULL RESET
Description Backup register which can be used for storage by the application firmware when the external host is powered down. These registers will retain their content as long as the VRTC is active.
Type RW
7 6 5 4 3 2 1 0
BCKUP
Bits Field Name Description Type Reset
7:0 BCKUP Backup bit RW 0x00

Table 6-31 BCK5_REG

Address Offset 0x1B
Instance Reset Domain: FULL RESET
Description Backup register which can be used for storage by the application firmware when the external host is powered down. These registers will retain their content as long as the VRTC is active.
Type RW
7 6 5 4 3 2 1 0
BCKUP
Bits Field Name Description Type Reset
7:0 BCKUP Backup bit RW 0x00

Table 6-32 PUADEN_REG

Address Offset 0x1C
Instance Reset Domain: GENERAL RESET
Description Pullup/pulldown control register.
Type RW
7 6 5 4 3 2 1 0
Reserved I2CCTLP I2CSRP PWRONP SLEEPP PWRHOLDP HDRSTP NRESPWRON2P
Bits Field Name Description Type Reset
7 Reserved RO 0
6 I2CCTLP SDACTL and SCLCTL pullup control:
1: Pullup is enabled
0: Pullup is disabled 		RW 0
5 I2CSRP SDASR and SCLSR pullup control:
1: Pullup is enabled
0: Pullup is disabled 		RW 0
4 PWRONP PWRON pad pullup control:
1: Pullup is enabled
0: Pullup is disabled 		RW 1
3 SLEEPP SLEEP pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled 		RW 1
2 PWRHOLDP PWRHOLD pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled 		RW 1
1 HDRSTP HDRST pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled 		RW 1
0 NRESPWRON2P NRESPWRON2 pad control:
1: Pulldown is enabled
0: Pulldown is disabled 		RW 1

Table 6-33 REF_REG

Address Offset 0x1D
Instance Reset Domain: TURNOFF OFF RESET
Description Reference control register
Type RO
7 6 5 4 3 2 1 0
Reserved ST
Bits Field Name Description Type Reset
7:2 Reserved Reserved bit RO
R returns 0s 		0x00
1:0 ST Reference state:
ST[1:0] = 00: Off
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Reserved
ST[1:0] = 11: On low power (SLEEP)
(Write access available in test mode only) 		RO 0x1

Table 6-34 VRTC_REG

Address Offset 0x1E
Instance Reset Domain: GENERAL RESET
Description VRTC internal regulator control register
Type RW
7 6 5 4 3 2 1 0
Reserved VRTC_
OFFMASK		 Reserved ST
Bits Field Name Description Type Reset
7:4 Reserved Reserved bit RO
R returns 0s 		0x0
3 VRTC_OFFMASK VRTC internal regulator off mask signal:
when 1, the regulator keeps its full-load capability during device OFF state.
when 0, the regulator will go to low-power mode during device OFF state.
Note that VRTC is put in low-power mode when the device is on backup even if this bit is set to 1
(Default value: See boot configuration) 		RW 0
2 Reserved Reserved bit RO
R returns 0s 		0
1:0 ST Reference state:
ST[1:0] = 00: Reserved
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Reserved
ST[1:0] = 11: On low power (SLEEP)
(Write access available in test mode only) 		RO 0x1

Table 6-35 VIO_REG

Address Offset 0x20
Instance Reset Domain: TURNOFF OFF RESET
Description VIO control register
Type RW
7 6 5 4 3 2 1 0
ILMAX Reserved SEL ST
Bits Field Name Description Type Reset
7:6 ILMAX Select maximum load current:
when 00: 0.6 A
when 01: 1.0 A
when 10: 1.3 A
when 11: 1.3 A 		RW 0x0
5:4 Reserved Reserved bit RO
R returns 0s 		0x0
3:2 SEL Output voltage selection (EEPROM bits):
SEL[1:0] = 00: 1.5 V
SEL[1:0] = 01: 1.8 V
SEL[1:0] = 10: 2.5 V
SEL[1:0] = 11: 3.3 V
(Default value: See boot configuration)		 RW 0x0
1:0 ST Supply state (EEPROM bits):
ST[1:0] = 00: Off
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP) 		RW 0x0

Table 6-36 VDD1_REG

Address Offset 0x21
Instance Reset Domain: TURNOFF OFF RESET
Description VDD1 control register
Type RW
7 6 5 4 3 2 1 0
VGAIN_SEL ILMAX TSTEP ST
Bits Field Name Description Type Reset
7:6 VGAIN_SEL Select output voltage multiplication factor: G (EEPROM bits):
when 00: ×1
when 01: ×1
when 10: ×2
when 11: ×3
(Default value: See boot configuration)		 RW 0x0
5 ILMAX Select maximum load current:
when 0: 1.0 A
when 1: > 1.5 A 		RW 0
4:2 TSTEP Time step: when changing the output voltage, the new value is reached through successive 12.5-mV voltage steps (if not bypassed). The equivalent programmable slew rate of the output voltage is then:
TSTEP[2:0] = 000: step duration is 0, step function is bypassed
TSTEP[2:0] = 001: 12.5 mV/µs (sampling 3 MHz)
TSTEP[2:0] = 010: 9.4 mV/µs (sampling 3 MHz × 3/4)
TSTEP[2:0] = 011: 7.5 mV/µs (sampling 3 MHz × 3/5) (default)
TSTEP[2:0] = 100: 6.25 mV/µs(sampling 3 MHz/2)
TSTEP[2:0] = 101: 4.7 mV/µs(sampling 3 MHz/3)
TSTEP[2:0] = 110: 3.12 mV/µs(sampling 3 MHz/4)
TSTEP[2:0] = 111: 2.5 mV/µs(sampling 3 MHz/5) 		RW 0x3
1:0 ST Supply state (EEPROM bits):
ST[1:0] = 00: Off
ST[1:0] = 01: On, high-power mode
ST[1:0] = 10: Off
ST[1:0] = 11: On, low-power mode 		RW 0x0

Table 6-37 VDD1_OP_REG

Address Offset 0x22
Instance Reset Domain: TURNOFF OFF RESET
Description VDD1 voltage selection register.
This register can be accessed by both control and voltage scaling I2C interfaces depending on SR_CTL_I2C_SEL register bit value.
Type RW
7 6 5 4 3 2 1 0
CMD SEL
Bits Field Name Description Type Reset
7 CMD when 0: VDD1_OP_REG voltage is applied
when 1: VDD1_SR_REG voltage is applied 		RW 0
6:0 SEL Output voltage (4 EEPROM bits) selection with GAIN_SEL = 00 (G = 1, 12.5 mV per LSB):
SEL[6:0] = 1001011 to 1111111: 1.5 V
...
SEL[6:0] = 0111111: 1.35 V
...
SEL[6:0] = 0110011: 1.2 V
...
SEL[6:0] = 0000001 to 0000011: 0.6 V
SEL[6:0] = 0000000: Off (0.0 V)
Note: from SEL[6:0] = 3 to 75 (dec)
Vout = (SEL[6:0] × 12.5 mV + 0.5625 V) × G
(Default value: See boot configuration)
Note: Vout maximum value is 3.3 V		 RW 0x00

Table 6-38 VDD1_SR_REG

Address Offset 0x23
Instance Reset Domain: TURNOFF OFF RESET
Description VDD1 voltage selection register.
This register can be accessed by both control and voltage scaling dedicated I2C interfaces depending on SR_CTL_I2C_SEL register bit value.
Type RW
7 6 5 4 3 2 1 0
Reserved SEL
Bits Field Name Description Type Reset
7 Reserved Reserved bit RO
R returns 0s 		0
6:0 SEL Output voltage selection with GAIN_SEL = 00 (G = 1, 12.5 mV per LSB):
SEL[6:0] = 1001011 to 1111111: 1.5 V
...
SEL[6:0] = 0111111: 1.35 V
...
SEL[6:0] = 0110011: 1.2 V
...
SEL[6:0] = 0000001 to 0000011: 0.6 V
SEL[6:0] = 0000000: Off (0.0 V)
Note: from SEL[6:0] = 3 to 75 (dec)
Vout = (SEL[6:0] × 12.5 mV + 0.5625 V) × G
(Default value: See boot configuration)
Note: Vout maximum value is 3.3 V		 RW 0x00

Table 6-39 VDD2_REG

Address Offset 0x24
Instance Reset Domain: TURNOFF OFF RESET
Description VDD2 control register
Type RW
7 6 5 4 3 2 1 0
VGAIN_SEL ILMAX TSTEP ST
Bits Field Name Description Type Reset
7:6 VGAIN_SEL Select output voltage multiplication factor (×1, ×3 included in EEPROM bits): G
when 00: ×1
when 01: ×1
when 10: ×2
when 11: ×3 		RW 0x0
5 ILMAX Select maximum load current:
when 0: 1.0 A
when 1: > 1.5 A 		RW 0
4:2 TSTEP Time step: when changing the output voltage, the new value is reached through successive 12.5-mV voltage steps (if not bypassed). The equivalent programmable slew rate of the output voltage is then:
TSTEP[2:0] = 000: step duration is 0, step function is bypassed
TSTEP[2:0] = 001: 12.5 mV/µs (sampling 3 MHz)
TSTEP[2:0] = 010: 9.4 mV/µs (sampling 3 MHz × 3/4)
TSTEP[2:0] = 011: 7.5 mV/µs (sampling 3 MHz × 3/5) (default)
TSTEP[2:0] = 100: 6.25 mV/µs(sampling 3 MHz/2)
TSTEP[2:0] = 101: 4.7 mV/µs(sampling 3 MHz/3)
TSTEP[2:0] = 110: 3.12 mV/µs(sampling 3 MHz/4)
TSTEP[2:0] = 111: 2.5 mV/µs(sampling 3 MHz/5) 		RW 0x1
1:0 ST Supply state (EEPROM bits):
ST[1:0] = 00: Off
ST[1:0] = 01: On, high-power mode
ST[1:0] = 10: Off
ST[1:0] = 11: On, low-power mode 		RW 0x0

Table 6-40 VDD2_OP_REG

Address Offset 0x25
Instance Reset Domain: TURNOFF OFF RESET
Description VDD2 voltage selection register.
This register can be accessed by both control and voltage scaling dedicated I2C interfaces depending on SR_CTL_I2C_SEL register bit value.
Type RW
7 6 5 4 3 2 1 0
CMD SEL
Bits Field Name Description Type Reset
7 CMD Command:
when 0: VDD2_OP_REG voltage is applied
when 1: VDD2_SR_REG voltage is applied 		RW 0
6:0 SEL Output voltage (4 EEPROM bits) selection with GAIN_SEL = 00 (G = 1, 12.5 mV per LSB):
SEL[6:0] = 1001011 to 1111111: 1.5 V
...
SEL[6:0] = 0111111: 1.35 V
...
SEL[6:0] = 0110011: 1.2 V
...
SEL[6:0] = 0000001 to 0000011: 0.6 V
SEL[6:0] = 0000000: Off (0.0 V)
Note: from SEL[6:0] = 3 to 75 (dec)
Vout = (SEL[6:0] × 12.5 mV + 0.5625 V) × G
Note: Vout maximum value is 3.3 V		 RW 0x00

Table 6-41 VDD2_SR_REG

Address Offset 0x26
Instance Reset Domain: TURNOFF OFF RESET
Description VDD2 voltage selection register.
This register can be accessed by both control and voltage scaling dedicated I2C interfaces depending on SR_CTL_I2C_SEL register bit value.
Type RW
7 6 5 4 3 2 1 0
Reserved SEL
Bits Field Name Description Type Reset
7 Reserved Reserved bit RO
R returns 0s 		0
6:0 SEL Output voltage (EEPROM bits) selection with GAIN_SEL = 00 (G = 1, 12.5 mV per LSB):
SEL[6:0] = 1001011 to 1111111: 1.5 V
...
SEL[6:0] = 0111111: 1.35 V
...
SEL[6:0] = 0110011: 1.2 V
...
SEL[6:0] = 0000001 to 0000011: 0.6 V
SEL[6:0] = 0000000: Off (0.0 V)
Note: from SEL[6:0] = 3 to 75 (dec)
Vout = (SEL[6:0] × 12.5 mV + 0.5625 V) × G
Note: Vout maximum value is 3.3 V		 RW 0x00

Table 6-42 VDDCRTL_REG

Address Offset 0x27
Instance Reset Domain: TURNOFF OFF RESET
Description VDDCtrl, external FET controller
Type RW
7 6 5 4 3 2 1 0
Reserved ST
Bits Field Name Description Type Reset
7:2 Reserved Reserved bit RO
R returns 0s 		0x00
1:0 ST Supply state (EEPROM dependent):
ST[1:0] = 00: Off
ST[1:0] = 01: On
ST[1:0] = 10: Off
ST[1:0] = 11: On 		RW 0x0

Table 6-43 VDDCRTL_OP_REG

Address Offset 0x28
Instance Reset Domain: TURN OFF RESET
Description VDDCtrl voltage selection register.
This register can be accessed by both control and voltage scaling dedicated I2C interfaces depending on SR_CTL_I2C_SEL register bit value.
Type RW
7 6 5 4 3 2 1 0
CMD SEL
Bits Field Name Description Type Reset
7 CMD Command:
when 0: VDDctrl_OP_REG voltage is applied
when 1: VDDctrl_SR_REG voltage is applied		 RW 0
6:0 SEL Output voltage (4 EEPROM bits) selection:
SEL[6:0] = 1000011 to 1111111: 1.4 V
...
SEL[6:0] = 0110011: 1.2 V
...
SEL[6:0] = 0010011: 0.8 V
...
SEL[6:0] = 0000001: 0000011 0.6 V
SEL[6:0] = 0000000: Off (0.0 V)
Note: from SEL[6:0] = 3 to 64 (dec)
Vout = (SEL[6:0] × 12.5 mV + 0.5625 V)
(Default value: See boot configuration)		 RW 0x00

Table 6-44 VDDCRTL_SR_REG

Address Offset 0x29
Instance Reset Domain: TURN OFF RESET
Description VDDCtrl voltage selection register.
This register can be accessed by both control and voltage scaling dedicated I2C interfaces depending on SR_CTL_I2C_SEL register bit value.
Type RW
7 6 5 4 3 2 1 0
Reserved SEL
Bits Field Name Description Type Reset
7 Reserved RO 0
6:0 SEL Output voltage (4 EEPROM bits) selection:
SEL[6:0] = 1000011 to 1111111: 1.4 V
...
SEL[6:0] = 0110011: 1.2 V
...
SEL[6:0] = 0010011: 0.8 V
...
SEL[6:0] = 0000001: 0000011: 0.6 V
SEL[6:0] = 0000000: Off (0.0 V)
Note: from SEL[6:0] = 3 to 64 (dec)
Vout = (SEL[6:0] × 12.5 mV + 0.5625 V)
(Default value: See boot configuration)		 RW 0x03

Table 6-45 LDO1_REG

Address Offset 0x30
Instance Reset Domain: TURNOFF OFF RESET
Description LDO1 regulator control register
Type RW
7 6 5 4 3 2 1 0
SEL ST
Bits Field Name Description Type Reset
7:2 SEL Supply voltage (EEPROM bits):
SEL[7:2] = 000000 to 000011: 1 V
SEL[7:2] = 000100: 1 V
SEL[7:2] = 000101: 1.05 V
...
SEL[7:2] = 110001: 3.25 V
SEL[7:2] = 110010: 3.3 V
(Default value: See boot configuration)		 RW 0x0
1:0 ST Supply state (EEPROM bits):
ST[1:0] = 00: Off
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP) 		RW 0x0

Table 6-46 LDO2_REG

Address Offset 0x31
Instance Reset Domain: TURNOFF OFF RESET
Description LDO2 regulator control register
Type RW
7 6 5 4 3 2 1 0
SEL ST
Bits Field Name Description Type Reset
7:2 SEL Supply voltage (EEPROM bits):
SEL[7:2] = 000000 to 000011: 1 V
SEL[7:2] = 000100: 1 V
SEL[7:2] = 000101: 1.05 V
...
SEL[7:2] = 110001: 3.25 V
SEL[7:2] = 110010: 3.3 V
(Default value: See boot configuration)		 RW 0x0
1:0 ST Supply state (EEPROM bits):
ST[1:0] = 00: Off
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP) 		RW 0x0

Table 6-47 LDO5_REG

Address Offset 0x32
Instance Reset Domain: TUROFF RESET
Description LDO5 regulator control register
Type RW
7 6 5 4 3 2 1 0
Reserved SEL ST
Bits Field Name Description Type Reset
7 Reserved RO
R returns 0s 		0
6:2 SEL Supply voltage (EEPROM bits):
SEL[6:2] = 00000 to 00010: 1 V
SEL[6:2] = 00011: 1.1 V
...
SEL[6:2] = 11000: 3.2 V
SEL[6:2] = 11001: 3.3 V
(Default value: See boot configuration)		 RW 0x00
1:0 ST Supply state (EEPROM bits):
ST[1:0] = 00: Off
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP) 		RW 0x0

Table 6-48 LDO8_REG

Address Offset 0x33
Instance Reset Domain: TURNOFF OFF RESET
Description LDO8 regulator control register
Type RW
7 6 5 4 3 2 1 0
Reserved SEL ST
Bits Field Name Description Type Reset
7 Reserved RO
R returns 0s 		0
6:2 SEL Supply voltage (EEPROM bits):
SEL[6:2] = 00000 to 00010: 1 V
SEL[6:2] = 00011: 1.1 V
...
SEL[6:2] = 11000: 3.2 V
SEL[6:2] = 11001: 3.3 V
(Default value: See boot configuration)		 RW 0x00
1:0 ST Supply state (EEPROM bits):
ST[1:0] = 00: Off
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP) 		RW 0x0

Table 6-49 LDO7_REG

Address Offset 0x34
Instance Reset Domain: TURNOFF OFF RESET
Description LDO7 regulator control register
Type RW
7 6 5 4 3 2 1 0
Reserved SEL ST
Bits Field Name Description Type Reset
7 Reserved RO
R returns 0s 		0
6:2 SEL Supply voltage (EEPROM bits):
SEL[6:2] = 00000 to 00010: 1 V
SEL[6:2] = 00011: 1.1 V
...
SEL[6:2] = 11000: 3.2 V
SEL[6:2] = 11001: 3.3 V
(Default value: See boot configuration)		 RW 0x00
1:0 ST Supply state (EEPROM bits):
ST[1:0] = 00: Off
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP) 		RW 0x0

Table 6-50 LDO6_REG

Address Offset 0x35
Instance Reset Domain: TURNOFF OFF RESET
Description LDO6 regulator control register
Type RW
7 6 5 4 3 2 1 0
Reserved SEL ST
Bits Field Name Description Type Reset
7 Reserved RO
R returns 0s 		0
6:2 SEL Supply voltage (EEPROM bits):
SEL[6:2] = 00000 to 00010: 1 V
SEL[6:2] = 00011: 1.1 V
...
SEL[6:2] = 11000: 3.2 V
SEL[6:2] = 11001: 3.3 V
(Default value: See boot configuration)		 RW 0x00
1:0 ST Supply state (EEPROM bits):
ST[1:0] = 00: Off
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP) 		RW 0x0

Table 6-51 LDO4_REG

Address Offset 0x36
Instance Reset Domain: TURNOFF OFF RESET
Description LDO4 regulator control register
Type RW
7 6 5 4 3 2 1 0
SEL ST
Bits Field Name Description Type Reset
7:2 SEL Supply voltage (EEPROM bits):
SEL[7:2] = 000000: 0.8 V
SEL[7:2] = 000001: 0.85 V
SEL[7:2] = 000010: 0.9 V
SEL[7:2] = 000011: 0.95 V
SEL[7:2] = 000100: 1 V
SEL[7:2] = 000101: 1.05 V
...
SEL[7:2] = 110001: 3.25 V
SEL[7:2] = 110010: 3.3 V
Applicable voltage selection
TRACK LDO 0: 1 V to 3.3 V
TRACK LDO 1: 0.8 V to 1.5 V
(Default value: See boot configuration)		 RW 0x00
1:0 ST Supply state (EEPROM bits):
ST[1:0] = 00: Off
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP) 		RW 0x0

Table 6-52 LDO3_REG

Address Offset 0x37
Instance Reset Domain: TURNOFF OFF RESET
Description LDO3 regulator control register
Type RW
7 6 5 4 3 2 1 0
Reserved SEL ST
Bits Field Name Description Type Reset
7 Reserved RO
R returns 0s 		0
6:2 SEL Supply voltage (EEPROM bits):
SEL[6:2] = 00000: 1 V
SEL[6:2] = 00001: 1 V
SEL[6:2] = 00010: 1 V
SEL[6:2] = 00011: 1.1 V
...
SEL[6:2] = 11000: 3.2 V
SEL[6:2] = 11001: 3.3 V
(Default value: See boot configuration)		 RW 0x00
1:0 ST Supply state (EEPROM bits):
ST[1:0] = 00: Off
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP) 		RW 0x0

Table 6-53 Therm_REG

Address Offset 0x38
Instance Reset Domain:
bits[5:2]: GENERAL RESET
bit[0]: TURNOFF OFF RESET
Description Thermal control register
Type RW
7 6 5 4 3 2 1 0
Reserved THERM_HD THERM_TS THERM_HDSEL Reserved THERM_
STATE
Bits Field Name Description Type Reset
7:6 Reserved Reserved bit RO
R returns 0s 		0x0
5 THERM_HD Hot die detector output:
when 0: the hot die threshold is not reached
when 1: the hot die threshold is reached 		RO 0
4 THERM_TS Thermal shutdown detector output:
when 0: the thermal shutdown threshold is not reached
when 1: the thermal shutdown threshold is reached 		RO 0
3:2 THERM_HDSEL Temperature selection for hot die detector:
when 00: Low temperature threshold
…
when 11: High temperature threshold 		RW 0x3
1 Reserved RO
R returns 0s 		0
0 THERM_STATE Thermal shutdown module enable signal:
when 0: thermal shutdown module is disable
when 1: thermal shutdown module is enable 		RW 1

Table 6-54 BBCH_REG

Address Offset 0x39
Instance Reset Domain: GENERAL RESET
Description Backup battery charger control register
Type RW
7 6 5 4 3 2 1 0
Reserved BBSEL BBCHEN
Bits Field Name Description Type Reset
7:3 Reserved Reserved bit RO
R returns 0s 		0x00
2:1 BBSEL Back up battery charge voltage selection:
BBSEL[1:0] = 00: 3.0 V
BBSEL[1:0] = 01: 2.52 V
BBSEL[1:0] = 10: 3.15 V
BBSEL[1:0] = 11: VBAT 		RW 0x0
0 BBCHEN Back up battery charge enable RW 0

Table 6-55 DCDCCTRL_REG

Address Offset 0x3E
Instance RESET DOMAIN:
bits [7:3]: TURNOFF OFF RESET
bits [2:0]: GENERAL RESET
Description DCDC control register
Type RW
7 6 5 4 3 2 1 0
Reserved TRACK VDD2_PSKIP VDD1_PSKIP VIO_PSKIP DCDCCKEXT DCDCCKSYNC
Bits Field Name Description Type Reset
7 Reserved Reserved bit RO
R returns 0s 		0
6 TRACK 0 = Normal LDO operation without tracking
1 = Tracking mode: LDO4 output follows VDD1 setting when VDD1 active. See Section 6.5.3.14 for more information.		 RW 0
5 VDD2_PSKIP VDD2 pulse skip mode enable (EEPROM bit)
Default value: See boot configuration		 RW 1
4 VDD1_PSKIP VDD1 pulse skip mode enable (EEPROM bit)
Default value: See boot configuration		 RW 1
3 VIO_PSKIP VIO pulse skip mode enable (EEPROM bit)
Default value: See boot configuration		 RW 1
2 DCDCCKEXT This signal control the muxing of the GPIO2 pad:
When 0: this pad is a GPIO
When 1: this pad is used as input for an external clock used for the synchronisation of the DCDCs 		RW 0
1:0 DCDCCKSYNC DCDC clock configuration:
DCDCCKSYNC[1:0] = 00: no synchronization of DCDC clocks
DCDCCKSYNC[1:0] = 01: DCDC synchronous clock with phase shift
DCDCCKSYNC[1:0] = 10: no synchronization of DCDC clocks
DCDCCKSYNC[1:0] = 11: DCDC synchronous clock 		RW 0x1

Table 6-56 DEVCTRL_REG

Address Offset 0x3F
Instance Reset Domain: GENERAL RESET
Bit 0,1, and 3: TURN OFF RESET
Description Device control register
Type RW
7 6 5 4 3 2 1 0
PWR_OFF_
SEQ		 RTC_PWDN CK32K_CTRL SR_CTL_I2C_SEL DEV_OFF_
RST		 DEV_ON DEV_SLP DEV_OFF
Bits Field Name Description Type Reset
7 PWR_OFF_SEQ When 1, power-off will be sequential, reverse of power-on sequence (first resource to power on will be the last to power off).
When 0, all resources disabled at the same time		 RW 0
6 RTC_PWDN When 1, disable the RTC digital domain (clock gating and reset of RTC registers and logic).
This register bit is not reset in BACKUP state.		 RW 0
5 CK32K_CTRL Internal 32-kHz clock source control bit (EEPROM bit):
when 0, the internal 32-kHz clock source is the crystal oscillator or an external 32-kHz clock in case the crystal oscillator is used in bypass mode
when 1, the internal 32-kHz clock source is the RC oscillator. 		RW 0
4 SR_CTL_I2C_SEL Voltage scaling registers access control bit:
when 0: access to registers by voltage scaling I2C
when 1: access to registers by control I2C. The voltage scaling registers are: VDD1_OP_REG, VDD1_SR_REG, VDD2_OP_REG, VDD2_SR_REG, VDDCtrl_OP_REG, and VDDCtrl_SR_REG. 		RW 1
3 DEV_OFF_RST Write 1 will start an ACTIVE-to-OFF or SLEEP-to-OFF device state transition (switch-off event) and activate reset of the digital core.
This bit is cleared in OFF state.		 RW 0
2 DEV_ON Write 1 will keep the device on (ACTIVE or SLEEP device state) (if DEV_OFF = 0 and DEV_OFF_RST = 0).
EEPROM bit
(Default value: See boot configuration)		 RW 0
1 DEV_SLP Write 1 allows SLEEP device state (if DEV_OFF = 0 and DEV_OFF_RST = 0).
Write 0 will start an SLEEP-to-ACTIVE device state transition (wake-up event) (if DEV_OFF = 0 and DEV_OFF_RST = 0). This bit is cleared in OFF state. 		RW 0
0 DEV_OFF Write 1 will start an ACTIVE-to-OFF or SLEEP-to-OFF device state transition (switch-off event). This bit is cleared in OFF state. RW 0

Table 6-57 DEVCTRL2_REG

Address Offset 0x40
Instance Reset Domain: GENERAL RESET
TSLOT_LENGTH: TURN OFF RESET
Description Device control register
Type RW
7 6 5 4 3 2 1 0
Reserved DCDC_SLEEP_LVL TSLOT_LENGTH SLEEPSIG_
POL		 PWON_LP_
OFF		 PWON_LP_
RST		 IT_POL
Bits Field Name Description Type Reset
7 Reserved RO
R returns 0s 		0
6 DCDC_SLEEP_LVL When 1, DCDC output level in SLEEP mode is VDDx_SR_REG, to be other than 0 V.
When 0, no effect		 RW 0
5:4 TSLOT_LENGTH Time slot duration programming (EEPROM bit):
When 00: 0 µs
When 01: 200 µs
When 10: 500 µs
When 11: 2 ms
(Default value: See boot configuration)		 RW 0x3
3 SLEEPSIG_POL When 1, SLEEP signal active-high
When 0, SLEEP signal active-low 		RW 0
2 PWON_LP_OFF When 1, allows device turnoff after a PWON Long Press (signal low) (EEPROM bits).
(Default value: See boot configuration)		 RW 1
1 PWON_LP_RST When 1, allows digital core reset when the device is OFF (EEPROM bit).
(Default value: See boot configuration)		 RW 0
0 IT_POL INT1 interrupt pad polarity control signal (EEPROM bit):
When 0, active low
When 1, active high
(Default value: See boot configuration)		 RW 0

Table 6-58 SLEEP_KEEP_LDO_ON_REG

Address Offset 0x41
Instance Reset Domain: GENERAL RESET
Description When corresponding control bit = 0 in EN1_ LDO_ASS register (default setting): Configuration Register keeping the full load capability of LDO regulator (ACTIVE mode) during the SLEEP state of the device.
When control bit = 1, LDO regulator full load capability (ACTIVE mode) is maintained during device SLEEP state.
When control bit = 0, the LDO regulator is set or stay in low-power mode during device SLEEP state(but then supply state can be overwritten programming ST[1:0]). Control bit value has no effect if the LDO regulator is off.
When corresponding control bit = 1 in EN1_ LDO_ASS register: Configuration Register setting the LDO regulator state driven by SCLSR_EN1 signal low level (when SCLSR_EN1 is high the regulator is on, full power):
- the regulator is set off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register (default)
- the regulator is set in low-power mode if its corresponding control bit = 1 in SLEEP_KEEP_LDO_ON register
Type RW
7 6 5 4 3 2 1 0
LDO3_
KEEPON		 LDO4_
KEEPON		 LDO7_KEEPON LDO8_
KEEPON		 LDO5_KEEPON LDO2_
KEEPON		 LDO1_
KEEPON		 LDO6_
KEEPON
Bits Field Name Description Type Reset
7 LDO3_KEEPON Setting supply state during device SLEEP state or when SCLSR_EN1 is low RW 0
6 LDO4_KEEPON Setting supply state during device SLEEP state or when SCLSR_EN1 is low RW 0
5 LDO7_KEEPON Setting supply state during device SLEEP state or when SCLSR_EN1 is low RW 0
4 LDO8_KEEPON Setting supply state during device SLEEP state or when SCLSR_EN1 is low RW 0
3 LDO5_KEEPON Setting supply state during device SLEEP state or when SCLSR_EN1 is low RW 0
2 LDO2_KEEPON Setting supply state during device SLEEP state or when SCLSR_EN1 is low RW 0
1 LDO1_KEEPON Setting supply state during device SLEEP state or when SCLSR_EN1 is low RW 0
0 LDO6_KEEPON Setting supply state during device SLEEP state or when SCLSR_EN1 is low RW 0

Table 6-59 SLEEP_KEEP_RES_ON_REG

Address Offset 0x42
Instance
Description Configuration Register keeping, during the SLEEP state of the device (but then supply state can be overwritten programming ST[1:0]):
- the full load capability of LDO regulator (ACTIVE mode),
- The PWM mode of DCDC converter
- 32-kHz clock output
- Register access though I2C interface (keeping the internal high speed clock on)
- Die Thermal monitoring on
Control bit value has no effect if the resource is off.
Type RW
7 6 5 4 3 2 1 0
THERM_
KEEPON		 CLKOUT32K_
KEEPON		 VRTC_
KEEPON		 I2CHS_
KEEPON		 Reserved VDD2_
KEEPON		 VDD1_
KEEPON		 VIO_
KEEPON
Bits Field Name Description Type Reset
7 THERM_KEEPON When 1, thermal monitoring is maintained during device SLEEP state.
When 0, thermal monitoring is turned off during device SLEEP state. 		RW 0
6 CLKOUT32K_KEEPON When 1, CLK32KOUT output is maintained during device SLEEP state.
When 0, CLK32KOUT output is set low during device SLEEP state. 		RW 0
5 VRTC_KEEPON When 1, LDO regulator full load capability (ACTIVE mode) is maintained during device SLEEP state.
When 0, the LDO regulator is set or stays in low-power mode during device SLEEP state. 		RW 0
4 I2CHS_KEEPON When 1, high speed internal clock is maintained during device SLEEP state.
When 0, high speed internal clock is turned off during device SLEEP state. 		RW 0
3 Reserved RO 0
2 VDD2_KEEPON When 1, VDD2 SMPS PWM mode is maintained during device SLEEP state. No effect if VDD2 working mode is PFM.
When 0, VDD2 SMPS PFM mode is set during device SLEEP state. 		RW 0
1 VDD1_KEEPON When 1, VDD1 SMPS PWM mode is maintained during device SLEEP state. No effect if VDD1 working mode is PFM.
When 0, VDD1 SMPS PFM mode is set during device SLEEP state. 		RW 0
0 VIO_KEEPON When 1, VIO SMPS PWM mode is maintained during device SLEEP state. No effect if VIO working mode is PFM.
When 0, VIO SMPS PFM mode is set during device SLEEP state. 		RW 0

Table 6-60 SLEEP_SET_LDO_OFF_REG

Address Offset 0x43
Instance Reset Domain: GENERAL RESET
Description Configuration Register turning-off LDO regulator during the SLEEP state of the device.
Corresponding *_KEEP_ON control bit in SLEEP_KEEP_RES_ON register should be 0 to make this *_SET_OFF control bit effective
Type RW
7 6 5 4 3 2 1 0
LDO3_SETOFF LDO4_SETOFF LDO7_SETOFF LDO8_SETOFF LDO5_SETOFF LDO2_SETOFF LDO1_SETOFF LDO6_SETOFF
Bits Field Name Description Type Reset
7 LDO3_SETOFF When 1, LDO regulator is turned off during device SLEEP state.
When 0, No effect		 RW 0
6 LDO4_SETOFF When 1, LDO regulator is turned off during device SLEEP state.
When 0, No effect		 RW 0
5 LDO7_SETOFF When 1, LDO regulator is turned off during device SLEEP state.
When 0, No effect		 RW 0
4 LDO8_SETOFF When 1, LDO regulator is turned off during device SLEEP state.
When 0, No effect		 RW 0
3 LDO5_SETOFF When 1, LDO regulator is turned off during device SLEEP state.
When 0, No effect		 RW 0
2 LDO2_SETOFF When 1, LDO regulator is turned off during device SLEEP state.
When 0, No effect		 RW 0
1 LDO1_SETOFF When 1, LDO regulator is turned off during device SLEEP state.
When 0, No effect		 RW 0
0 LDO6_SETOFF When 1, LDO regulator is turned off during device SLEEP state.
When 0, No effect		 RW 0

Table 6-61 SLEEP_SET_RES_OFF_REG

Address Offset 0x44
Instance Reset Domain: GENERAL RESET
Description Configuration Register turning-off SMPS regulator during the SLEEP state of the device.
Corresponding *_KEEP_ON control bit in SLEEP_KEEP_RES_ON2 register should be 0 to make this *_SET_OFF control bit effective. Supplies voltage expected after their wake-up (SLEEP-to-ACTIVE state transition) can also be programmed.
Type RW
7 6 5 4 3 2 1 0
DEFAULT_
VOLT		 Reserved SPARE_
SETOFF		 VDDCTRL_
SETOFF		 VDD2_
SETOFF		 VDD1_
SETOFF		 VIO_
SETOFF
Bits Field Name Description Type Reset
7 DEFAULT_VOLT When 1, default voltages (register value after switch-on) will be applied to all resources during SLEEP-to-ACTIVE transition.
When 0, voltages programmed before the ACTIVE-to-SLEEP state transition will be used to turned-on supplies during SLEEP-to-ACTIVE state transition.		 RW 0
6:5 Reserved RO
R returns 0s 		0x0
4 SPARE_SETOFF Spare bit RW 0
3 VDDCTRL_SETOFF When 1, SMPS is turned off during device SLEEP state.
When 0, No effect.		 RW 0
2 VDD2_SETOFF When 1, SMPS is turned off during device SLEEP state.
When 0, No effect.		 RW 0
1 VDD1_SETOFF When 1, SMPS is turned off during device SLEEP state.
When 0, No effect.		 RW 0
0 VIO_SETOFF When 1, SMPS is turned off during device SLEEP state.
When 0, No effect.		 RW 0

Table 6-62 EN1_LDO_ASS_REG

Address Offset 0x45
Instance Reset Domain: TURNOFF RESET
Description Configuration Register setting the LDO regulators, driven by the multiplexed SCLSR_EN1 signal.
When control bit = 1, LDO regulator state is driven by the SCLSR_EN1 control signal and is also defined though SLEEP_KEEP_LDO_ON register setting:
When SCLSR_EN1 is high the regulator is on,
When SCLSR_EN1 is low:
- the regulator is off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register
- the regulator is working in low-power mode if its corresponding control bit = 1 in
SLEEP_KEEP_LDO_ON register
When control bit = 0 no effect: LDO regulator state is driven though registers programming and the device state
Any control bit of this register set to 1 will disable the I2C SR Interface functionality
Type RW
7 6 5 4 3 2 1 0
LDO3_EN1 LDO4_EN1 LDO7_EN1 LDO8_EN1 LDO5_EN1 LDO2_EN1 LDO1_EN1 LDO6_EN1
Bits Field Name Description Type Reset
7 LDO3_EN1 Setting supply state control though SCLSR_EN1 signal RW 0
6 LDO4_EN1 Setting supply state control though SCLSR_EN1 signal RW 0
5 LDO7_EN1 Setting supply state control though SCLSR_EN1 signal RW 0
4 LDO8_EN1 Setting supply state control though SCLSR_EN1 signal RW 0
3 LDO5_EN1 Setting supply state control though SCLSR_EN1 signal RW 0
2 LDO2_EN1 Setting supply state control though SCLSR_EN1 signal RW 0
1 LDO1_EN1 Setting supply state control though SCLSR_EN1 signal RW 0
0 LDO6_EN1 Setting supply state control though SCLSR_EN1 signal RW 0

Table 6-63 EN1_SMPS_ASS_REG

Address Offset 0x46
Instance Reset Domain: TURNOFF RESET
Description Configuration Register setting the SMPS Supplies driven by the multiplexed SCLSR_EN1 signal.
When control bit = 1, SMPS Supply state and voltage is driven by the SCLSR_EN1 control signal and is also defined though SLEEP_KEEP_RES_ON register setting.
When control bit = 0 no effect: SMPS Supply state is driven though registers programming and the device state.
Any control bit of this register set to 1 will disable the I2C SR Interface functionality
Type RW
7 6 5 4 3 2 1 0
Reserved SPARE_EN1 VDDCTRL_
EN1		 VDD2_EN1 VDD1_EN1 VIO_EN1
Bits Field Name Description Type Reset
7:5 Reserved RO
R returns 0s		 0x0
4 SPARE_EN1 Spare bit RW 0
3 VDDCTRL_EN1 When control bit = 1:
When EN1 is high the supply voltage is programmed though VDDCtrl_OP_REG register, and it can also be programmed off.
When EN1 is low the supply voltage is programmed though VDDCtrl_SR_REG register, and it can also be programmed off.
When control bit = 0: No effect: Supply state is driven though registers programming and the device state		 RW 0
2 VDD2_EN1 When control bit = 1:
When SCLSR_EN1 is high the supply voltage is programmed though VDD2_OP_REG register, and it can also be programmed off.
When SCLSR_EN1 is low the supply voltage is programmed though VDD2_SR_REG register, and it can also be programmed off.
When SCLSR_EN1 is low and SLEEP_KEEP_RES_ON = 1 the SMPS is working in low-power mode, if not tuned off through VDD2_SR_REG register.
When control bit = 0 No effect: Supply state is driven though registers programming and the device state		 RW 0
1 VDD1_EN1 When 1:
When SCLSR_EN1 is high the supply voltage is programmed though VDD1_OP_REG register, and it can also be programmed off.
When SCLSR_EN1 is low the supply voltage is programmed though VDD1_SR_REG register, and it can also be programmed off.
When SCLSR_EN1 is low and SLEEP_KEEP_RES_ON = 1 the SMPS is working in low-power mode, if not tuned off though VDD1_SR_REG register.
When control bit = 0 no effect: supply state is driven though registers programming and the device state		 RW 0
0 VIO_EN1 When control bit = 1, supply state is driven by the SCLSR_EN1 control signal and is also defined though SLEEP_KEEP_RES_ON register setting:
When SCLSR_EN1 is high the supply is on,
When SCLSR_EN1 is low:
- the supply is off (default) or the SMPS is working in low-power mode if its corresponding control bit = 1 in SLEEP_KEEP_RES_ON register
When control bit = 0 No effect: SMPS state is driven though registers programming and the device state		 RW 0

Table 6-64 EN2_LDO_ASS_REG

Address Offset 0x47
Instance Reset Domain: TURNOFF RESET
Description Configuration Register setting the LDO regulators, driven by the multiplexed SDASR_EN2 signal.
When control bit = 1, LDO regulator state is driven by the SDASR_EN2 control signal and is also defined though SLEEP_KEEP_LDO_ON register setting:
When SDASR_EN2 is high the regulator is on,
When SCLSR_EN2 is low:
- the regulator is off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register
- the regulator is working in low-power mode if its corresponding control bit = 1 in SLEEP_KEEP_LDO_ON register
When control bit = 0 no effect: LDO regulator state is driven though registers programming and the device state
Any control bit of this register set to 1 will disable the I2C SR Interface functionality
Type RW
7 6 5 4 3 2 1 0
LDO3_EN2 LDO4_EN2 LDO7_EN2 LDO8_EN2 LDO5_EN2 LDO2_EN2 LDO1_EN2 LDO6_EN2
Bits Field Name Description Type Reset
7 LDO3_EN2 Setting supply state control though SDASR_EN2 signal RW 0
6 LDO4_EN2 Setting supply state control though SDASR_EN2 signal RW 0
5 LDO7_EN2 Setting supply state control though SDASR_EN2 signal RW 0
4 LDO8_EN2 Setting supply state control though SDASR_EN2 signal RW 0
3 LDO5_EN2 Setting supply state control though SDASR_EN2 signal RW 0
2 LDO2_EN2 Setting supply state control though SDASR_EN2 signal RW 0
1 LDO1_EN2 Setting supply state control though SDASR_EN2 signal RW 0
0 LDO6_EN2 Setting supply state control though SDASR_EN2 signal RW 0

Table 6-65 EN2_SMPS_ASS_REG

Address Offset 0x48
Instance Reset Domain: TURNOFF RESET
Description Configuration Register setting the SMPS Supplies driven by the multiplexed SDASR_EN2 signal.
When control bit = 1, SMPS Supply state and voltage is driven by the SDASR_EN2 control signal and is also defined though SLEEP_KEEP_RES_ON register setting.
When control bit = 0 no effect: SMPS Supply state is driven though registers programming and the device state
Any control bit of this register set to 1 will disable the I2C SR Interface functionality
Type RW
7 6 5 4 3 2 1 0
Reserved SPARE_EN2 VDDCTRL_
EN2		 VDD2_EN2 VDD1_EN2 VIO_EN2
Bits Field Name Description Type Reset
7:5 Reserved RO
R returns 0s 		0x0
4 SPARE_EN2 Spare bit RW 0
3 VDDCTRL_EN2 When control bit = 1:
When EN2 is high the supply voltage is programmed though VDDCtrl_OP_REG register, and it can also be programmed off..
When EN2 is low the supply voltage is programmed though VDDCtrl_SR_REG register, and it can also be programmed off.
When EN2 is low and VDDCtrl_KEEPON = 1 the SMPS is working in low-power mode, if not tuned off though VDDCtrl_SR_REG register.
When control bit = 0 no effect: Supply state is driven though registers programming and the device state		 RW 0
2 VDD2_EN2 When control bit = 1:
When SDASR_EN2 is high the supply voltage is programmed though VDD2_OP_REG register, and it can also be programmed off.
When SDASR_EN2 is low the supply voltage is programmed though VDD2_SR_REG register, and it can also be programmed off.
When SDASR_EN2 is low and SLEEP_KEEP_RES_ON = 1 the SMPS is working in low-power mode, if not tuned off though VDD2_SR_REG register.
When control bit = 0 no effect: Supply state is driven though registers programming and the device state		 RW 0
1 VDD1_EN2 When control bit = 1:
When SDASR_EN2 is high the supply voltage is programmed though VDD1_OP_REG register, and it can also be programmed off.
When SDASR_EN2 is low the supply voltage is programmed though VDD1_SR_REG register, and it can also be programmed off.
When SDASR_EN2 is low and SLEEP_KEEP_RES_ON = 1 the SMPS is working in low-power mode, if not tuned off though VDD1_SR_REG register.
When control bit = 0 no effect: supply state is driven though registers programming and the device state		 RW 0
0 VIO_EN2 When control bit = 1,
supply state is driven by the SCLSR_EN2 control signal and is also defined though SLEEP_KEEP_RES_ON register setting:
When SDASR _EN2 is high the supply is on,
When SDASR _EN2 is low :
- the supply is off (default) or the SMPS is working in low-power mode if its corresponding control bit = 1 in SLEEP_KEEP_RES_ON register
When control bit = 0 no effect: SMPS state is driven though registers programming and the device state		 RW 0

Table 6-66 INT_STS_REG

Address Offset 0x50
Instance Reset Domain: FULL RESET
Description Interrupt status register:
The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is cleared by writing 1.
Type RW
7 6 5 4 3 2 1 0
RTC_PERIOD_IT RTC_ALARM_
IT		 HOTDIE_IT PWRHOLD_R_
IT		 PWRON_LP_IT PWRON_IT VMBHI_IT PWRHOLD_F_
IT
Bits Field Name Description Type Reset
7 RTC_PERIOD_IT RTC period event interrupt status. RW
W1 to Clr 		0
6 RTC_ALARM_IT RTC alarm event interrupt status. RW
W1 to Clr 		0
5 HOTDIE_IT Hot-die event interrupt status. RW
W1 to Clr 		0
4 PWRHOLD_R_IT Rising PWRHOLD event interrupt status. RW
W1 to Clr 		0
3 PWRON_LP_IT PWRON Long Press event interrupt status. RW
W1 to Clr 		0
2 PWRON_IT PWRON event interrupt status. RW
W1 to Clr 		0
1 VMBHI_IT VBAT > VMHI event interrupt status RW
W1 to Clr 		0
0 PWRHOLD_F_IT Falling PWRHOLD event interrupt status. RW
W1 to Clr 		0

Table 6-67 INT_MSK_REG

Address Offset 0x51
Instance Reset Domain: GENERAL RESET
Description Interrupt mask register:
When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT interrupt status bit is updated.
When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is updated.
Type RW
7 6 5 4 3 2 1 0
RTC_PERIOD_
IT_MSK		 RTC_ALARM_
IT_MSK		 HOTDIE_
IT_MSK		 PWRHOLD_R_
IT_MSK		 PWRON_LP_
IT_MSK		 PWRON_
IT_MSK		 VMBHI_
IT_MSK		 PWRHOLD_F_
IT_MSK
Bits Field Name Description Type Reset
7 RTC_PERIOD_IT_MSK RTC period event interrupt mask. RW 1
6 RTC_ALARM_IT_MSK RTC alarm event interrupt mask. RW 1
5 HOTDIE_IT_MSK Hot die event interrupt mask. RW 1
4 PWRHOLD_R_IT_MSK PWRHOLD rising-edge event interrupt mask. RW 1
3 PWRON_LP_IT_MSK PWRON Long Press event interrupt mask. RW 1
2 PWRON_IT_MSK PWRON event interrupt mask. RW 1
1 VMBHI_IT_MSK VBAT > VMBHI interrupt event mask bit
When 0, interrupt not masked. Device automatically switches on at NO SUPPLY-to-OFF BACKUP-to-OFF transition
When 1, interrupt is masked. Device does not switch on until a start reason is received.
(EEPROM bit. Default value: See boot configuration)		 RW 1
0 PWRHOLD_F_IT_MSK PWRHOLD falling-edge event interrupt mask. RW 1

Table 6-68 INT_STS2_REG

Address Offset 0x52
Instance Reset Domain: FULL RESET
Description Interrupt status register:
The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is cleared by writing 1.
Type RW
7 6 5 4 3 2 1 0
GPIO3_F_IT GPIO3_R_IT GPIO2_F_IT GPIO2_R_IT GPIO1_F_IT GPIO1_R_IT GPIO0_F_IT GPIO0_R_IT
Bits Field Name Description Type Reset
7 GPIO3_F_IT GPIO3 falling-edge detection interrupt status RW
W1 to Clr 		0
6 GPIO3_R_IT GPIO3 rising-edge detection interrupt status RW
W1 to Clr 		0
5 GPIO2_F_IT GPIO2 falling-edge detection interrupt status RW
W1 to Clr 		0
4 GPIO2_R_IT GPIO2 rising-edge detection interrupt status RW
W1 to Clr 		0
3 GPIO1_F_IT GPIO1 falling-edge detection interrupt status RW
W1 to Clr 		0
2 GPIO1_R_IT GPIO1 rising-edge detection interrupt status RW
W1 to Clr 		0
1 GPIO0_F_IT GPIO0 falling-edge detection interrupt status RW
W1 to Clr 		0
0 GPIO0_R_IT GPIO0 rising-edge detection interrupt status RW
W1 to Clr 		0

Table 6-69 INT_MSK2_REG

Address Offset 0x53
Instance Reset Domain: GENERAL RESET
Description Interrupt mask register:
When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT interrupt status bit is updated.
When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is updated.
Type RW
7 6 5 4 3 2 1 0
GPIO3_F_
IT_MSK		 GPIO3_R_
IT_MSK		 GPIO2_F_
IT_MSK		 GPIO2_R_
IT_MSK		 GPIO1_F_
IT_MSK		 GPIO1_R_
IT_MSK		 GPIO0_F_
IT_MSK		 GPIO0_R_
IT_MSK
Bits Field Name Description Type Reset
7 GPIO3_F_IT_MSK GPIO3 falling-edge detection interrupt mask. RW 1
6 GPIO3_R_IT_MSK GPIO3 rising-edge detection interrupt mask. RW 1
5 GPIO2_F_IT_MSK GPIO2 falling-edge detection interrupt mask. RW 1
4 GPIO2_R_IT_MSK GPIO2 rising-edge detection interrupt mask. RW 1
3 GPIO1_F_IT_MSK GPIO1 falling-edge detection interrupt mask. RW 1
2 GPIO1_R_IT_MSK GPIO1 rising-edge detection interrupt mask. RW 1
1 GPIO0_F_IT_MSK GPIO0 falling-edge detection interrupt mask. RW 1
0 GPIO0_R_IT _MSK GPIO0 rising-edge detection interrupt mask. RW 1

Table 6-70 INT_STS3_REG

Address Offset 0x54
Instance Reset Domain: FULL RESET
Description Interrupt status register:
The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is cleared by writing 1.
Type RW
7 6 5 4 3 2 1 0
PWRDN_IT VMBCH2_L_IT VMBCH2_H_IT WTCHDG_IT GPIO5_F_IT GPIO5_R_IT GPIO4_F_IT GPIO4_R_IT
Bits Field Name Description Type Reset
7 PWRDN_IT PWRDN reset input high detected RW
W1 to Clr 		0
6 VMBCH2_L_IT Comparator2 input below threshold detection interrupt status RW
W1 to Clr 		0
5 VMBCH2_H_IT Comparator2 input above threshold detection interrupt status RW
W1 to Clr 		0
4 WTCHDG_IT Watchdog interrupt status RW
W1 to Clr 		0
3 GPIO5_F_IT GPIO5 falling-edge detection interrupt status RW
W1 to Clr 		0
2 GPIO5_R_IT GPIO5 rising-edge detection interrupt status RW
W1 to Clr 		0
1 GPIO4_F_IT GPIO4 falling-edge detection interrupt status RW
W1 to Clr 		0
0 GPIO4_R_IT GPIO4 rising-edge detection interrupt status RW
W1 to Clr 		0

Table 6-71 INT_MSK3_REG

Address Offset 0x55
Instance Reset Domain: GENERAL RESET
Description Interrupt mask register:
When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT interrupt status bit is updated.
When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is updated.
Type RW
7 6 5 4 3 2 1 0
PWRDN_
IT_MSK 		VMBCH2_L_
IT_MSK		 VMBCH2_H_
IT_MSK		 WTCHDG_
IT_MSK		 GPIO5_F_
IT_MSK		 GPIO5_R_
IT_MSK		 GPIO4_F_
IT_MSK		 GPIO4_R_
IT_MSK
Bits Field Name Description Type Reset
7 PWRDN_IT_MSK PWRDN interrupt mask RW 1
6 VMBCH2_L_IT_MSK Comparator2 input below threshold detection interrupt mask RW 1
5 VMBCH2_H_IT_MSK Comparator2 input above threshold detection interrupt mask RW 1
4 WTCHDG_IT_MSK Watchdog interrupt mask. RW 1
3 GPIO5_F_IT_MSK GPIO5 falling-edge detection interrupt mask. RW 1
2 GPIO5_R_IT_MSK GPIO5 rising-edge detection interrupt mask. RW 1
1 GPIO4_F_IT_MSK GPIO4 falling-edge detection interrupt mask. RW 1
0 GPIO4_R_IT_MSK GPIO4 rising-edge detection interrupt mask. RW 1

Table 6-72 GPIO0_REG

Address Offset 0x60
Instance Reset Domain: GENERAL RESET
Description GPIO0 configuration register
Type RW
7 6 5 4 3 2 1 0
GPIO_SLEEP Reserved GPIO_ODEN GPIO_DEB GPIO_PDEN GPIO_CFG GPIO_STS GPIO_SET
Bits Field Name Description Type Reset
7 GPIO_SLEEP(1) 1: as GPO, force low
0: No impact, keep as in active mode		 RW 0
6 Reserved Reserved bit RO
R returns 0s 		0
5 GPIO_ODEN Selection of output mode, EEPROM bit
0: Push-pull output
1: Open-drain output
(Default value: See boot configuration)
GPIO assigned to power-up sequence, this bit will be set to 1 by a TURNOFF reset		 RW 0
4 GPIO_DEB GPIO input debouncing time configuration:
When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate
When 1, the debouncing is 150 ms using a 50 ms clock rate 		RW 0
3 GPIO_PDEN GPIO pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled 		RW 0
2 GPIO_CFG Configuration of the GPIO pad direction:
When 0, the pad is configured as an input
When 1, the pad is configured as an output
(Default value: See boot configuration)		 RW 0
1 GPIO_STS Status of the GPIO pad RO 1
0 GPIO_SET Value set on the GPIO output when configured in output mode
GPIO assigned to power-up sequence, this bit will be in TURNOFF reset		 RW 0
(1) The GPIO_SLEEP bit is a bit available only for GPIO_0/2/6/7.This bit will be take into account and be effective only if the GPIO_0/2/6/7 is associated to a TIME_SLOT. It means that this bit is useful only if the GPIO is part of the POWER UP SEQUENCE. Note that in this case the associated GPIO will be set as GPO. GPIO_SLEEP bit is a bit related to the PMU sleep mode only, No action in ACTIVE mode. It is used to define SLEEP mode state for GPIO 0/2/6/7.

Table 6-73 GPIO1_REG

Address Offset 0x61
Instance Reset Domain: GENERAL RESET
Description GPIO1 configuration register
Type RW
7 6 5 4 3 2 1 0
Reserved GPIO_SEL GPIO_DEB GPIO_PDEN GPIO_CFG GPIO_STS GPIO_SET
Bits Field Name Description Type Reset
7:6 Reserved RO
R returns 0s 		0x0
5 GPIO_SEL Select signal to be available at GPIO when configured as output:
0: GPIO_SET
1: LED1 out		 RW 0
4 GPIO_DEB GPIO input debouncing time configuration:
When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate
When 1, the debouncing is 150 ms using a 50 ms clock rate 		RW 0
3 GPIO_PDEN GPIO pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled 		RW 1
2 GPIO_CFG Configuration of the GPIO pad direction:
When 0, the pad is configured as an input
When 1, the pad is configured as an output 		RW 0
1 GPIO_STS Status of the GPIO pad RO 1
0 GPIO_SET Value set on the GPIO output when configured in output mode RW 0

Table 6-74 GPIO2_REG

Address Offset 0x62
Instance Reset Domain: GENERAL RESET
Description GPIO2 configuration register
Type RW
7 6 5 4 3 2 1 0
GPIO_SLEEP Reserved GPIO_DEB GPIO_PDEN GPIO_CFG GPIO_STS GPIO_SET
Bits Field Name Description Type Reset
7 GPIO_SLEEP 1: as GPO, force low
0: no impact, keep as in active mode		 RW 0
6:5 Reserved RO
R returns 0s 		0x0
4 GPIO_DEB GPIO input debouncing time configuration:
When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate
When 1, the debouncing is 150 ms using a 50 ms clock rate 		RW 0
3 GPIO_PDEN GPIO pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled
GPIO assigned to power-up sequence, this bit will be set to 0 by a TURNOFF reset		 RW 1
2 GPIO_CFG Configuration of the GPIO pad direction:
When 0, the pad is configured as an input
When 1, the pad is configured as an output
(Default value: See boot configuration)
GPIO assigned to power-up sequence, this bit will be set to 1 by a TURNOFF reset 		RW 0
1 GPIO_STS Status of the GPIO pad RO 1
0 GPIO_SET Value set on the GPIO output when configured in output mode
GPIO assigned to power-up sequence, this bit will be in TURNOFF reset		 RW 0

Table 6-75 GPIO3_REG

Address Offset 0x63
Instance Reset Domain: GENERAL RESET
Description GPIO3 configuration register
Type RW
7 6 5 4 3 2 1 0
Reserved GPIO_SEL GPIO_DEB GPIO_PDEN GPIO_CFG GPIO_STS GPIO_SET
Bits Field Name Description Type Reset
7 Reserved RO
R returns 0s 		0
6:5 GPIO_SEL Select signal to be available at GPIO when configured as output:
00: GPIO_SET
01: LED2 out
10: PWM out 		RW 0x0
4 GPIO_DEB GPIO input debouncing time configuration:
When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate
When 1, the debouncing is 150 ms using a 50 ms clock rate 		RW 0
3 GPIO_PDEN GPIO pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled 		RW 1
2 GPIO_CFG Configuration of the GPIO pad direction:
When 0, the pad is configured as an input
When 1, the pad is configured as an output 		RW 0
1 GPIO_STS Status of the GPIO pad RO 1
0 GPIO_SET Value set on the GPIO output when configured in output mode RW 0

Table 6-76 GPIO4_REG

Address Offset 0x64
Instance Reset Domain: GENERAL RESET
Description GPIO4 configuration register
Type RW
7 6 5 4 3 2 1 0
Reserved GPIO_DEB GPIO_PDEN GPIO_CFG GPIO_STS GPIO_SET
Bits Field Name Description Type Reset
7:5 Reserved RO
R returns 0s 		0x0
4 GPIO_DEB GPIO input debouncing time configuration:
When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate
When 1, the debouncing is 150 ms using a 50 ms clock rate 		RW 0
3 GPIO_PDEN GPIO pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled 		RW 1
2 GPIO_CFG Configuration of the GPIO pad direction:
When 0, the pad is configured as an input
When 1, the pad is configured as an output 		RW 0
1 GPIO_STS Status of the GPIO pad RO 1
0 GPIO_SET Value set on the GPIO output when configured in output mode RW 0

Table 6-77 GPIO5_REG

Address Offset 0x65
Instance Reset Domain: GENERAL RESET
Description GPIO5 configuration register
Type RW
7 6 5 4 3 2 1 0
Reserved GPIO_DEB GPIO_PDEN GPIO_CFG GPIO_STS GPIO_SET
Bits Field Name Description Type Reset
7:5 Reserved RO
R returns 0s 		0x0
4 GPIO_DEB GPIO input debouncing time configuration:
When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate
When 1, the debouncing is 150 ms using a 50 ms clock rate 		RW 0
3 GPIO_PDEN GPIO pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled 		RW 1
2 GPIO_CFG Configuration of the GPIO pad direction:
When 0, the pad is configured as an input
When 1, the pad is configured as an output 		RW 0
1 GPIO_STS Status of the GPIO pad RO 1
0 GPIO_SET Value set on the GPIO output when configured in output mode RW 0

Table 6-78 GPIO6_REG

Address Offset 0x66
Instance Reset Domain: GENERAL RESET
Description GPIO6 configuration register
Type RW
7 6 5 4 3 2 1 0
GPIO_SLEEP Reserved GPIO_DEB GPIO_PDEN GPIO_CFG GPIO_STS GPIO_SET
Bits Field Name Description Type Reset
7 GPIO_SLEEP 1: as GPO, force low
0: no impact, keep as in active mode		 RW 0
6:5 Reserved RO
R returns 0s 		0x0
4 GPIO_DEB GPIO input debouncing time configuration:
When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate
When 1, the debouncing is 150 ms using a 50 ms clock rate 		RW 0
3 GPIO_PDEN GPIO pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled
GPIO assigned to power-up sequence, this bit will be set to 0 by a TURNOFF reset		 RW 1
2 GPIO_CFG Configuration of the GPIO pad direction:
When 0, the pad is configured as an input
When 1, the pad is configured as an output
(Default value: See boot configuration)
GPIO assigned to power-up sequence, this bit will be set to 1 by a TURNOFF reset 		RW 0
1 GPIO_STS Status of the GPIO pad RO 1
0 GPIO_SET Value set on the GPIO output when configured in output mode
GPIO assigned to power-up sequence, this bit will be in TURNOFF reset		 RW 0

Table 6-79 GPIO7_REG

Address Offset 0x67
Instance Reset Domain: GENERAL RESET
Description GPIO7 configuration register
Type RW
7 6 5 4 3 2 1 0
GPIO_SLEEP Reserved GPIO_DEB GPIO_PDEN GPIO_CFG GPIO_STS GPIO_SET
Bits Field Name Description Type Reset
7 GPIO_SLEEP 1: as GPO, force low
0: no impact, keep as in active mode		 RW 0
6:5 Reserved RO
R returns 0s 		0x0
4 GPIO_DEB GPIO input debouncing time configuration:
When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate
When 1, the debouncing is 150 ms using a 50 ms clock rate 		RW 0
3 GPIO_PDEN GPIO pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled
GPIO assigned to power-up sequence, this bit will be set to 0 by a TURNOFF reset		 RW 1
2 GPIO_CFG Configuration of the GPIO pad direction:
When 0, the pad is configured as an input
When 1, the pad is configured as an output
(Default value: See boot configuration)
GPIO assigned to power-up sequence, this bit will be set to 1 by a TURNOFF reset 		RW 0
1 GPIO_STS Status of the GPIO pad RO 1
0 GPIO_SET Value set on the GPIO output when configured in output mode
GPIO assigned to power-up sequence, this bit will be in TURNOFF reset		 RW 0

Table 6-80 GPIO8_REG

Address Offset 0x68
Instance Reset Domain: GENERAL RESET
Description GPIO8 configuration register
Type RW
7 6 5 4 3 2 1 0
Reserved GPIO_SEL GPIO_DEB GPIO_PDEN GPIO_CFG GPIO_STS GPIO_SET
Bits Field Name Description Type Reset
7:6 Reserved RO
R returns 0s 		0x0
5 GPIO_SEL Select signal to be available at GPIO when configured as output:
0: GPIO_SET
1: PWM out		 RW 0
4 GPIO_DEB GPIO input debouncing time configuration:
When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate
When 1, the debouncing is 150 ms using a 50 ms clock rate 		RW 0
3 GPIO_PDEN GPIO pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled 		RW 1
2 GPIO_CFG Configuration of the GPIO pad direction:
When 0, the pad is configured as an input
When 1, the pad is configured as an output 		RW 0
1 GPIO_STS Status of the GPIO pad RO 1
0 GPIO_SET Value set on the GPIO output when configured in output mode RW 0

Table 6-81 WATCHDOG_REG

Address Offset 0x69
Instance Reset Domain: GENERAL RESET
Description Watchdog
Type RW
7 6 5 4 3 2 1 0
Reserved WTCHDG_
MODE		 WTCHDG_TIME
Bits Field Name Description Type Reset
7:4 Reserved RO
R returns 0s 		0x0
3 WTCHDG_MODE 0: Periodic operation:
A periodical interrupt is generated based on WTCHDG_TIME setting. IC will generate WTCHDOG shutdown if interrupt is not cleared during the period.
1: Interrupt mode:
IC will generate WTCHDOG shutdown if an interrupt is pending (no cleared) more than WTCHDG_TIME s.		 RW 0
2:0 WTCHDG_TIME 000: Watchdog disabled
001: 5 seconds
010: 10 seconds
011: 20 Seconds
100: 40 seconds
101: 60 seconds
110: 80 seconds
111: 100 seconds (EEPROM bit)
(Default value: See boot configuration) 		RW 0x0

Table 6-82 VMBCH_REG

Address Offset 0x6A
Instance Reset Domain: GENERAL RESET
Description Comparator control register
Type RW
7 6 5 4 3 2 1 0
Reserved VMBCH_SEL Reserved
Bits Field Name Description Type Reset
7:6 Reserved RO
R returns 0s 		0x0
5:1 VMBCH_SEL Battery voltage comparator threshold (EEPROM)
11000 to 11111: 3.5 V
10111: 3.45 V
...
01110: 3 V (default)
...
00101: 2.55 V
00001 to 00100: 2.5 V
00000: Bypass
(Default value: See boot configuration) 		RW 0x00
0 Reserved RO
R returns 0s 		0

Table 6-83 VMBCH2_REG

Address Offset 0x6B
Instance Reset Domain: GENERAL RESET
Description Comparator for detecting battery discharge below threshold level
Type RW
7 6 5 4 3 2 1 0
Reserved VMBDCH2_SEL VMBDCH2_
DEB
Bits Field Name Description Type Reset
7:6 Reserved RO
R returns 0s 		0x0
5:1 VMBDCH2_SEL Battery voltage comparator threshold
11000 to 11111: 3.5 V
10111: 3.45 V
...
00101: 2.55 V
00001 to 00100: 2.5 V
00000: Bypass 		RW 0x00
0 VMBDCH2_DEB Comp2 input debouncing time configuration:
When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate
When 1, the debouncing is 150 ms using a 50 ms clock rate 		RW 0

Table 6-84 LED_CTRL1_REG

Address Offset 0x6C
Instance Reset Domain: GENERAL RESET
Description LED ON/OFF control register.
Type RW
7 6 5 4 3 2 1 0
Reserved LED2_PERIOD LED1_PERIOD
Bits Field Name Description Type Reset
7:6 Reserved RO
R returns 0s 		0x0
5:3 LED2_PERIOD Period of LED2 signal:
000: LED2 OFF
001: 0.125 s
010: 0.25 s
...
110: 4 s
111: 8 s 		RW 0x0
2:0 LED1_PERIOD Period of LED1 signal:
000: LED1 OFF
001: 0.125 s
010: 0.25 s
...
10: 2 s
110: 4 s
111: 8 s 		RW 0x0

Table 6-85 LED_CTRL2_REG1

Address Offset 0x6D
Instance Reset Domain: GENERAL RESET
Description LED ON/OFF control register.
Type RW
7 6 5 4 3 2 1 0
Reserved LED2_SEQ LED1_SEQ LED2_ON_TIME LED1_ON_TIME
Bits Field Name Description Type Reset
7:6 Reserved RO
R returns 0s 		0x0
5 LED2_SEQ When 1, LED2 will repeat 2 pulse sequence: ON (ON_TIME) - OFF (ON TIME) - ON (ON TIME) - OFF remainder of the period
When 0, LED2 will generate 1 pulse: ON (ON_TIME) - OFF (ON TIME)) 		RW 0
4 LED1_SEQ When 1, LED1 will repeat 2 pulse sequence: ON (ON_TIME) - OFF (ON TIME) - ON (ON TIME) - OFF remainder of the period.
When 0, LED1 will generate 1 pulse: ON (ON_TIME) - OFF (ON TIME)) 		RW 0
3:2 LED2_ON_TIME LED2 ON time:
00: 62.5 ms
01: 125 ms
10: 250 ms
11: 500 ms 		RW 0x0
1:0 LED1_ON_TIME LED1 ON time:
00: 62.5 ms
01: 125 ms
10: 250 ms
11: 500 ms 		RW 0x0

Table 6-86 PWM_CTRL1_REG

Address Offset 0x6E
Instance Reset Domain: GENERAL RESET
Description PWM frequency
Type RW
7 6 5 4 3 2 1 0
Reserved PWM_FREQ
Bits Field Name Description Type Reset
7:2 Reserved Reserved bit RO
R returns 0s 		0x00
1:0 PWM_FREQ Frequency of PWM:
00: 500 Hz
01: 250 Hz
10: 125 Hz
11: 62.5 Hz 		RW 0x0

Table 6-87 PWM_CTRL2_REG

Address Offset 0x6F
Instance Reset Domain: GENERAL RESET
Description PWM duty cycle.
Type RW
7 6 5 4 3 2 1 0
FREQ_DUTY_CYCLE
Bits Field Name Description Type Reset
7:0 FREQ_DUTY_CYCLE Duty cycle of PWM:
00000000: 0/256
...
11111111: 255/256 		RW 0x00

Table 6-88 SPARE_REG

Address Offset 0x70
Instance Reset Domain: FULL RESET
Description Spare functional register
Type RW
7 6 5 4 3 2 1 0
SPARE
Bits Field Name Description Type Reset
7:0 SPARE Spare bits RW 0x00

Table 6-89 VERNUM_REG

Address Offset 0x80
Instance Reset Domain: FULL RESET
Description Silicon version number
Type RW
7 6 5 4 3 2 1 0
READ_BOOT Reserved VERNUM
Bits Field Name Description Type Reset
7 READ_BOOT To enable the read of the BOOT mode if you want to go to JTAG mode, this be must set to 1. RW 0
6:4 Reserved Reserved bit RO
R returns 0s		 0x0
3:0 VERNUM Value depending on silicon version number 0000 - Revision 1.0 RO 0x0