JAJSF73S June   2010  – August 2018 TPS65911

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison Table
  4. 4Pin Configuration and Functions
    1. 4.1 Pin Attributes
      1.      Pin Attributes
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: I/O Pullup and Pulldown
    6. 5.6  Electrical Characteristics: Digital I/O Voltage
    7. 5.7  Electrical Characteristics: Power Consumption
    8. 5.8  Electrical Characteristics: Power References and Thresholds
    9. 5.9  Electrical Characteristics: Thermal Monitoring and Shutdown
    10. 5.10 Electrical Characteristics: 32-kHz RTC Clock
    11. 5.11 Electrical Characteristics: Backup Battery Charger
    12. 5.12 Electrical Characteristics: VRTC LDO
    13. 5.13 Electrical Characteristics: VIO SMPS
    14. 5.14 Electrical Characteristics: VDD1 SMPS
    15. 5.15 Electrical Characteristics: VDD2 SMPS
    16. 5.16 Electrical Characteristics: VDDCtrl SMPS
    17. 5.17 Electrical Characteristics: LDO1 and LDO2
    18. 5.18 Electrical Characteristics: LDO3 and LDO4
    19. 5.19 Electrical Characteristics: LDO5
    20. 5.20 Electrical Characteristics: LDO6, LDO7, and LDO8
    21. 5.21 Timing and Switching Characteristics
      1. 5.21.1 I2C Timing and Switching
      2. 5.21.2 Switch-ON and Switch-OFF Sequences and Timing
      3. 5.21.3 Power Control Timing
        1. 5.21.3.1 Device State Control Through PWRON Signal
        2. 5.21.3.2 Device SLEEP State Control
        3. 5.21.3.3 Device Turnon and Turnoff With Rising and Falling Input Voltage
        4. 5.21.3.4 Power Supplies State Control Through EN1 and EN2 Signals
        5. 5.21.3.5 VDD1, VDD2 Voltage Control Through EN1 and EN2 Signals
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Power Reference
    4. 6.4  Power Resources
    5. 6.5  Embedded Power Controller (EPC)
      1. 6.5.1 State Machine
        1. 6.5.1.1 Device POWER ON Enable Conditions
        2. 6.5.1.2 Device POWER ON Disable Conditions
        3. 6.5.1.3 Device SLEEP Enable Conditions
        4. 6.5.1.4 Device Reset Scenarios
      2. 6.5.2 BOOT Configuration, Switch-ON, and Switch-OFF Sequences
      3. 6.5.3 Control Signals
        1. 6.5.3.1  SLEEP
        2. 6.5.3.2  PWRHOLD
        3. 6.5.3.3  BOOT1
        4. 6.5.3.4  NRESPWRON, NRESPWRON2
        5. 6.5.3.5  CLK32KOUT
        6. 6.5.3.6  PWRON
        7. 6.5.3.7  INT1
        8. 6.5.3.8  EN2 and EN1
        9. 6.5.3.9  GPIO0 to GPIO8
        10. 6.5.3.10 HDRST Input
        11. 6.5.3.11 PWRDN
        12. 6.5.3.12 Comparators: COMP1 and COMP2
        13. 6.5.3.13 Watchdog
        14. 6.5.3.14 Tracking LDO
    6. 6.6  PWM and LED Generators
    7. 6.7  Dynamic Voltage Frequency Scaling and Adaptive Voltage Scaling Operation
    8. 6.8  32-kHz RTC Clock
    9. 6.9  Real Time Clock (RTC)
      1. 6.9.1 Time Calendar Registers
      2. 6.9.2 General Registers
      3. 6.9.3 Compensation Registers
    10. 6.10 Backup Battery Management
    11. 6.11 Backup Registers
    12. 6.12 I2C Interface
      1. 6.12.1 Access Protocols
        1. 6.12.1.1 Single Byte Access
        2. 6.12.1.2 Multiple Byte Access to Several Adjacent Registers
    13. 6.13 Thermal Monitoring and Shutdown
    14. 6.14 Interrupts
    15. 6.15 Register Maps
      1. 6.15.1 Functional Registers
        1. 6.15.1.1 TPS65911_FUNC_REG Registers Mapping Summary
        2. 6.15.1.2 TPS65911_FUNC_REG Register Descriptions
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 External Component Recommendation
        2. 7.2.2.2 Controller Design Procedure
          1. 7.2.2.2.1 Inductor Selection
          2. 7.2.2.2.2 Selecting the RTRIP Resistor
          3. 7.2.2.2.3 Selecting the Output Capacitors
          4. 7.2.2.2.4 Selecting FETs
          5. 7.2.2.2.5 Bootstrap Capacitor
          6. 7.2.2.2.6 Selecting Input Capacitors
        3. 7.2.2.3 Converter Design Procedure
          1. 7.2.2.3.1 Selecting the Inductor
          2. 7.2.2.3.2 Selecting Output Capacitors
          3. 7.2.2.3.3 Selecting Input Capacitors
      3. 7.2.3 Application Curves
      4. 7.2.4 Layout Guidelines
        1. 7.2.4.1 PCB Layout
      5. 7.2.5 Layout Example
    3. 7.3 Power Supply Recommendations
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 デバイス・サポート
      1. 8.1.1 開発サポート
      2. 8.1.2 デバイスの項目表記
    2. 8.2 ドキュメントのサポート
      1. 8.2.1 関連資料
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 コミュニティ・リソース
      1. 8.4.1 Community Resources
    5. 8.5 商標
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 Glossary
  9. 9メカニカル、パッケージ、および注文情報
    1. 9.1 パッケージの説明

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4.1 Pin Attributes

Pin Attributes

PIN I/O TYPE SUPPLIES DESCRIPTION PULLUP
PULLDOWN
NAME NO.
AGND D6, E5, E6,
F5, G4, H5,
H6, J3, J4,
J6, K3		 I/O Power AGND Analog ground No
AGND2 M8, N8 I/O Power AGND Analog ground No
BOOT1 J5 I Digital VRTC, DGND Power-up sequence selection No
CLK32KOUT F4 O Digital VDDIO, DGND 32-kHz clock output PD disable in ACTIVE or SLEEP state
DGND A1, B1, B2 I/O Power DGND Digital ground No
DRVH A3 O Analog VBST, GNDC VDDCtrl, High-side FET driver output
DRVL A6 O Analog V5IN, GNDC VDDCtrl, FET driver output
EN D5 I Analog VCC7, GNDC Internal functional pin, leave floating
EN1 M7 I/O Digital VDDIO, DGND Enable for supplies or
voltage scaling dedicated I2C clock		 External PU
EN2 M6 I/O Digital VDDIO, DGND Enable for supplies or
voltage scaling dedicated I2C data		 External PU
GNDC A7, A8 I/O Power GNDC VDDCtrl, Controller ground
GNDIO J7, J8 I/O Power VCCIO, GNDIO VIO DCDC Power ground No
GND1 C1, C2, D3 I/O Power VCC1, GND1 VDD1 DCDC Power ground No
GND2 J1, J2 I/O Power VCC2, GND2 VDD2 DCDC Power ground No
GPIO0 L5 I/O Digital VCC7, DGND GPIO, push-pull or OD as output OD: External PU
GPIO1 F6 I/O, OD Digital VRTC, DGND GPIO or LED1 output OD: External PU
GPIO2 L2 I/O, OD Digital VRTC, DGND GPIO or DCDC clock synchronization OD: External PU
GPIO3 B7 I/O, OD Digital VRTC, DGND GPIO or LED2 output OD: External PU
GPIO4 H7 I/O, OD Digital VRTC, DGND GPIO OD: External PU
GPIO5 G6 I/O, OD Digital VRTC, DGND GPIO OD: external PU
GPIO6 G3 I/O; OD Digital VRTC, DGND GPIO OD: External PU
GPIO7 L4 I/O, OD Digital VRTC, DGND GPIO OD: External PU
GPIO8 K5 I/O, OD Digital VRTC, DGND GPIO OD: External PU
HDRST L6 I Digital VRTC, DGND Cold reset PD
INT1 L3 O Digital VDDIO, DGND Interrupt flag No
LDO1 N6 O Power VCC6, REFGND LDO Regulator output No
LDO2 N4 O Power VCC6, REFGND LDO Regulator output No
LDO3 E7 O Power VCC5, REFGND LDO Regulator output PD 5 µA
LDO4 C8 O Power VCC5, REFGND LDO Regulator output PD 5 µA
LDO5 K1 O Power VCC4, REFGND LDO Regulator output PD 5 µA
LDO6 M2 O Power VCC3, REFGND LDO Regulator output PD 5 µA
LDO7 M3 O Power VCC3, REFGND LDO Regulator output PD 5 µA
LDO8 M1 O Power VCC3, REFGND LDO Regulator output PD 5 µA
NRESPWRON H4 O Digital VDDIO, DGND Power off reset PD active during device OFF state
NRESPWRON2 C7 O, OD Digital VRTC, DGND Second NRESPWRON output PD active during device OFF state. External pullup in ACTIVE state.
OSC32KIN F8 I Analog VRTC, REFGND 32-kHz crystal oscillator No
OSC32KOUT F7 I Analog VRTC, REFGND 32-kHz crystal oscillator No
PGOOD C4 O, OD Analog VCC7, GNDC VDDCtrl, internal signal, leave floating (controller trimming only)
PWRDN N2 I Analog VRTC, DGND Reset input (for example, thermal reset)
PWRHOLD N1 I Digital VRTC, DGND Switch-on, switch off control signal or GPI Programmable PD
(default active)
PWRON E4 I Digital VCC7, DGND External switch-on control (ON button) Programmable PU
(default active)
REFGND G7 I/O Analog REFGND Reference ground No
SCL_SCK M4 I/O Digital VDDIO, DGND I2C bidirectional clock signal or serial peripheral interface clock input (multiplexed) External PU
SDA_SDI M5 I/O Digital VDDIO, DGND I2C bidirectional data signal or serial peripheral interface data input (multiplexed) External PU
SLEEP F1 I Digital VDDIO, DGND ACTIVE-SLEEP state transition control signal Programmable PD
(default active)
SW A4 I Analog VBST, GNDC VDDCtrl, Switch node
SWIO K7, K8 O Power VCCIO, GNDIO VIO DCDC switched output No
SW1 D1, D2, E2 O Power VCC1, GND1 VDD1 DCDC switched output No
SW2 H1, H2 O Power VCC2, GND2 VDD2 DCDC switched output No
TESTV B8 O Analog VCC7, AGND Analog test output (DFT) No
TRAN C6 I Analog VCC7, GNDC Internal functional pin, leave floating (controller trimming only)
TRIP B3 I Analog V5IN, GNDC VDDCtrl, OCL detection threshold pin
VBACKUP D7 I Power VBACKUP, AGND Backup battery input No
VBST A2 I Analog VBST, GNDC VDDCtrl, supply for high-side FET driver
VCCIO L7, L8 I Power VCCIO, GNDIO VIO DCDC power Input No
VCCS E8 I/O Analog VCC7, DGND Input for two comparators
VCC1 E1, F2, F3 I Power VCC1, GND1 VDD1 DCDC power Input No
VCC2 G1, G2 I Power VCC2, GND2 VDD2 DCDC power Input No
VCC3 N3 I Power VCC3, AGND2 LDO6, LDO7, LDO8 power Input No
VCC4 L1 I Power VCC4, AGND2 LDO5 power Input No
VCC5 D8 I Power VCC5, AGND LDO3, LDO4 power Input No
VCC6 N5 I Power VCC6, AGND2 LDO1, LDO2 power Input No
VCC7 B6 I Power VCC7, REFGND VRTC power input and analog references supply No
VDDIO N7 I Power VDDIO, DGND Digital Ios supply No
VFB C5 I Analog VOUT, GNDC VDDCtrl, slew rate control capacitance
VFBIO H8 I Analog VCC7, DGND VIO feedback voltage PD 5 µA
VFB1 D4 I Analog VCC7, DGND VDD1 feedback voltage PD 5 µA
VFB2 K2 I Analog VCC7, DGND VDD2 DCDC feedback voltage PD 5 µA
VOUT B4 I Analog VOUT, GNDC VDDCtrl, Feedback input
VREF G8 O Analog VCC7, REFGND Band-gap voltage No
VRTC B5 O Power VCC7, REFGND LDO Regulator output PD 5 µA
V5IN A5 I Power V5IN, GNDC VDDCtrl, 5-V input