SWCS071C August   2012  – August 2017

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Default Settings
  4. 4 Pin Configuration and Functions
    1. 4.1 Pin Functions
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Characteristics
    5. 5.5  Electrical Characteristics - DCDC1, DCDC2, and DCDC3
    6. 5.6  Electrical Characteristics - DCDC4
    7. 5.7  Electrical Characteristics - LDOs
    8. 5.8  Electrical Characteristics - Digital Inputs, Digital Outputs
    9. 5.9  Electrical Characteristics - VMON Voltage Monitor, VDDIO, Undervoltage Lockout (UVLO), and LDOAO
    10. 5.10 Electrical Characteristics - Load Switch
    11. 5.11 Electrical Characteristics - LED Drivers
    12. 5.12 Electrical Characteristics - Thermal Monitoring and Shutdown
    13. 5.13 Electrical Characteristics - 32-kHz RC Clock
    14. 5.14 SPI Interface Timing Requirements
    15. 5.15 I2C Interface Timing Requirements
    16. 5.16 Typical Characteristics
  6. 6 Parameter Measurement Information
    1. 6.1 I2C Timing Diagrams
    2. 6.2 SPI Timing Diagram
  7. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Linear Regulators
      1. 7.3.1 Low Quiescent Current Mode (Eco-mode™)
      2. 7.3.2 Output Discharge
      3. 7.3.3 Thermal Shutdown
      4. 7.3.4 LDO Enable
      5. 7.3.5 LDO Voltage Range
      6. 7.3.6 LDO Power Good Comparator
    4. 7.4  Step-Down Converters
      1. 7.4.1 PWM/PFM Mode
      2. 7.4.2 Low Quiescent Current Mode
      3. 7.4.3 Output Voltage Monitoring
      4. 7.4.4 Output Discharge
      5. 7.4.5 Thermal Shutdown
      6. 7.4.6 Step-Down Converter ENABLE
      7. 7.4.7 Step-Down converter SOFT START
    5. 7.5  GPIOs
    6. 7.6  Power State Machine
    7. 7.7  Transition Conditions
    8. 7.8  Implementation of Internal Power-Up and Power-Down Sequencing
    9. 7.9  EN1, EN2, EN3, EN4, Resources Control
    10. 7.10 SLEEP State Control
    11. 7.11 Registers SET_OFF, KEEP_ON and DEF_VOLT Used in SLEEP State; CONFIG2 = 1
    12. 7.12 Registers SET_OFF, KEEP_ON and DEF_VOLT Used for Resources Assigned to an External Enable Pin; CONFIG2 = 1
    13. 7.13 Registers SET_OFF, KEEP_ON and DEF_VOLT for Resources Assigned to Pins PWR_REQ, CLK_REQ1 and CLK_REQ2; CONFIG2 = 0
    14. 7.14 Voltage Scaling Interface Control Using _OP and _AVS Registers with I2C or SPI Interface
    15. 7.15 Voltage Scaling Using the VCON Decoder on Pins VCON_PWM and VCON_CLK
    16. 7.16 Configuration Pins CONFIG1, CONFIG2 and DEF_SPI_I2C-GPIO
    17. 7.17 VDDIO Voltage for Push-Pull Output Stages
    18. 7.18 Digital Signal Summary
    19. 7.19 TPS659121 On/Off Operation With E450, E500
      1. 7.19.1 TPS659121 Power Up From Battery or 5-V USB Supply; CONFIG1=LOW
      2. 7.19.2 TPS659121 Power Up From 3.3-V Host Supply; CONFIG1=LOW
    20. 7.20 TPS659122 On/Off Operation for CONFIG1=HIGH
      1. 7.20.1 TPS659122 Power Up With CONFIG1=HIGH
      2. 7.20.2 TPS659121, TPS659122 Power-Off Sequence With CONFIG1=HIGH
    21. 7.21 TPS659122 On/Off Operation for CONFIG1=LOW
      1. 7.21.1 TPS659122 Power Up With CONFIG1=LOW
      2. 7.21.2 TPS659122 Power-Off Sequence With CONFIG1=LOW
    22. 7.22 Interfaces
    23. 7.23 Serial Peripheral Interface
    24. 7.24 I2C Interface
      1. 7.24.1 I2C Implementation
      2. 7.24.2 F/S-Mode Protocol
      3. 7.24.3 H/S-Mode Protocol
    25. 7.25 Thermal Monitoring and Shutdown
    26. 7.26 Load Switch
    27. 7.27 LED Driver
    28. 7.28 Memory
      1. 7.28.1 Register Format
      2. 7.28.2 Register Descriptions
        1. 7.28.2.1 DCDC Registers
          1. 7.28.2.1.1  DCDC1_CTRL (00h)
          2. 7.28.2.1.2  DCDC2_CTRL (01h)
          3. 7.28.2.1.3  DCDC3_CTRL (02h)
          4. 7.28.2.1.4  DCDC4_CTRL (03h)
          5. 7.28.2.1.5  DCDC1_OP (04h)
          6. 7.28.2.1.6  DCDC1_AVS (05h)
          7. 7.28.2.1.7  DCDC1_LIMIT (06h)
          8. 7.28.2.1.8  DCDC2_OP (07h)
          9. 7.28.2.1.9  DCDC2_AVS (08h)
          10. 7.28.2.1.10 DCDC2_LIMIT (09h)
          11. 7.28.2.1.11 DCDC3_OP (0Ah)
          12. 7.28.2.1.12 DCDC3_AVS (0Bh)
          13. 7.28.2.1.13 DCDC3_LIMIT (0Ch)
          14. 7.28.2.1.14 DCDC4_OP (0Dh)
          15. 7.28.2.1.15 DCDC4_AVS (0Eh)
          16. 7.28.2.1.16 DCDC4_LIMIT (0Fh)
          17. 7.28.2.1.17 VDCDCx Range Settings
          18. 7.28.2.1.18 DCDCx Voltage Settings
        2. 7.28.2.2 LDO Registers
          1. 7.28.2.2.1  LDO1_OP (10h)
          2. 7.28.2.2.2  LDO1_AVS (11h)
          3. 7.28.2.2.3  LDO1_LIMIT (12h)
          4. 7.28.2.2.4  LDO2_OP (13h)
          5. 7.28.2.2.5  LDO2_AVS (14h)
          6. 7.28.2.2.6  LDO2_LIMIT (15h)
          7. 7.28.2.2.7  LDO3_OP (16h)
          8. 7.28.2.2.8  LDO3_AVS (17h)
          9. 7.28.2.2.9  LDO3_LIMIT (18h)
          10. 7.28.2.2.10 LDO4_OP (19h)
          11. 7.28.2.2.11 LDO4_AVS (1Ah)
          12. 7.28.2.2.12 LDO4_LIMIT (1Bh)
          13. 7.28.2.2.13 LDO5 (1Ch)
          14. 7.28.2.2.14 LDO6 (1Dh)
          15. 7.28.2.2.15 LDO7 (1Eh)
          16. 7.28.2.2.16 LDO8 (1Fh)
          17. 7.28.2.2.17 LDO9 (20h)
          18. 7.28.2.2.18 LDO10 (21h)
        3. 7.28.2.3 LDO Voltage Settings
        4. 7.28.2.4 DEVCTRL Registers
          1. 7.28.2.4.1  THRM_REG (22h)
          2. 7.28.2.4.2  CLK32KOUT (23h)
          3. 7.28.2.4.3  DEVCTRL (24h)
          4. 7.28.2.4.4  DEVCTRL2 (25h)
          5. 7.28.2.4.5  I2C_SPI_CFG (26h)
          6. 7.28.2.4.6  KEEP_ON1 (27h)
          7. 7.28.2.4.7  KEEP_ON2 (28h)
          8. 7.28.2.4.8  SET_OFF1 (29h)
          9. 7.28.2.4.9  SET_OFF2 (2Ah)
          10. 7.28.2.4.10 DEF_VOLT (2Bh)
          11. 7.28.2.4.11 LDO Sleep Mode Behavior
          12. 7.28.2.4.12 DEF_VOLT_MAPPING (2Ch)
          13. 7.28.2.4.13 DISCHARGE1 (2Dh)
          14. 7.28.2.4.14 DISCHARGE2 (2Eh)
          15. 7.28.2.4.15 EN1_SET1 (2Fh)
          16. 7.28.2.4.16 EN1_SET2 (30h)
          17. 7.28.2.4.17 EN2_SET1 (31h)
          18. 7.28.2.4.18 EN2_SET2 (32h)
          19. 7.28.2.4.19 EN3_SET1 (33h)
          20. 7.28.2.4.20 EN3_SET2 (34h)
          21. 7.28.2.4.21 EN4_SET1 (35h)
          22. 7.28.2.4.22 EN4_SET2 (36h)
          23. 7.28.2.4.23 PGOOD (37h)
          24. 7.28.2.4.24 PGOOD2 (38h)
          25. 7.28.2.4.25 INT_STS (39h)
          26. 7.28.2.4.26 INT_MSK (3Ah)
          27. 7.28.2.4.27 INT_STS2 (3Bh)
          28. 7.28.2.4.28 INT_MSK2 (3Ch)
          29. 7.28.2.4.29 INT_STS3 (3Dh)
          30. 7.28.2.4.30 INT_MSK3 (3Eh)
          31. 7.28.2.4.31 INT_STS4 (3Fh)
          32. 7.28.2.4.32 INT_MSK4 (40h)
          33. 7.28.2.4.33 GPIO1 (41h)
          34. 7.28.2.4.34 GPIO2 (42h)
          35. 7.28.2.4.35 GPIO3 (43h)
          36. 7.28.2.4.36 GPIO4 (44h)
          37. 7.28.2.4.37 GPIO5 (45h)
          38. 7.28.2.4.38 VMON (46h)
          39. 7.28.2.4.39 LEDA_CTRL1 (47h)
          40. 7.28.2.4.40 LEDA_CTRL2 (48h)
          41. 7.28.2.4.41 LEDA_CTRL3 (49h)
          42. 7.28.2.4.42 LEDA_CTRL4 (4Ah)
          43. 7.28.2.4.43 LEDA_CTRL5 (4Bh)
          44. 7.28.2.4.44 LEDA_CTRL6 (4Ch)
          45. 7.28.2.4.45 LEDA_CTRL7 (4Dh)
          46. 7.28.2.4.46 LEDA_CTRL8 (4Eh)
          47. 7.28.2.4.47 LEDB_CTRL1 (4Fh)
          48. 7.28.2.4.48 LEDB_CTRL2 (50h)
          49. 7.28.2.4.49 LEDB_CTRL3 (51h)
          50. 7.28.2.4.50 LEDB_CTRL4 (52h)
          51. 7.28.2.4.51 LEDB_CTRL5 (53h)
          52. 7.28.2.4.52 LEDB_CTRL6 (54h)
          53. 7.28.2.4.53 LEDB_CTRL7 (55h)
          54. 7.28.2.4.54 LEDB_CTRL8 (56h)
          55. 7.28.2.4.55 LEDC_CTRL1 (57h)
          56. 7.28.2.4.56 LEDC_CTRL2 (58h)
          57. 7.28.2.4.57 LEDC_CTRL3 (59h)
          58. 7.28.2.4.58 LED_CTRL4 (5Ah)
          59. 7.28.2.4.59 LEDC_CTRL5 (5Bh)
          60. 7.28.2.4.60 LEDC_CTRL6 (5Ch)
          61. 7.28.2.4.61 LEDC_CTRL7 (5Dh)
          62. 7.28.2.4.62 LEDC_CTRL8 (5Eh)
          63. 7.28.2.4.63 LED_RAMP_UP_TIME (5Fh)
          64. 7.28.2.4.64 LED_RAMP_DOWN_TIME (60h)
          65. 7.28.2.4.65 LED_SEQ_EN (61h)
          66. 7.28.2.4.66 LEDx DC Current
          67. 7.28.2.4.67 LOADSWITCH (62h)
          68. 7.28.2.4.68 SPARE (63h)
          69. 7.28.2.4.69 VERNUM (64h)
  8. 8 Applications, Implementation, and Layout
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 DC-DC Converters
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Output Filter Design (Inductor and Output Capacitor)
            1. 8.2.1.2.1.1 Inductor Selection
            2. 8.2.1.2.1.2 Output Capacitor Selection
            3. 8.2.1.2.1.3 Input Capacitor Selection / Input Voltage
            4. 8.2.1.2.1.4 Output Capacitor Table
            5. 8.2.1.2.1.5 Voltage Change on DCDC1 to DCDC4
        3. 8.2.1.3 Application Curves
        4. 8.2.1.4 Layout
          1. 8.2.1.4.1 Layout Guidelines
          2. 8.2.1.4.2 Layout Example
    3. 8.3 Power Supply Recommendations
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Community Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Applications, Implementation, and Layout

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS65912 device is an integrated power-management integrated circuit (PMIC) that comes in an 81- pin, 0.4-mm pitch, DSBGA package. This device was designed for personal electronic, industrial, and communication applications and is dedicated to designs powered from a 5-V input supply that require multiple power rails. The device provides four step-down converters along with an interface to control ten external LDO regulators. The device can support a variety of different processors and applications. The step-down converters can also support dynamic voltage scaling through a dedicated I2C interface to provide optimum power savings. In addition to the power resources, the device contains an embedded power controller (EPC) to manage the power sequencing requirements of systems. The power sequencing is programmable through OTP. The device also contains five configurable GPIOs, a real-time clock module, and three LED outputs. The following sections provide the typical application use-case with the recommended external components and layout guidelines.

8.2 Typical Application

8.2.1 DC-DC Converters

TPS659121 TPS659122 ICERA_application_USB.gif Figure 8-1 5-V USB Host Connections for E450 and E500 Platforms

8.2.1.1 Design Requirements

For a typical application shown in Figure 8-1, Table 8-1 lists the key design parameters of the power resources.

Table 8-1 Design Parameters

DESIGN PARAMETER VALUE
Supply voltage 2.7 V to 5.5 V
Switching frequency Up to 3.5 MHz
DCDC1 voltage 1.1 V
DCDC1 current Up to 2.5 A
DCDC2 voltage 2.0 V
DCDC2 current Up to 0.75 A
DCDC3 voltage 3.2 V
DCDC3 current Up to 1.6 A
DCDC4 voltage 3.6 V
DCDC4 current Up to 2.5 A
LDO1 voltage 850 mV or 900 mV
LDO1 current Up to 100 mA
LDO2 voltage 850 mV or 900 mV
LDO2 current Up to 100 mA
LDO3 voltage 1.2 V
LDO3 current Up to 100 mA
LDO4 voltage 1.7 V or 1.8 V
LDO4 current Up to 250 mA
LDO5 voltage 2.7 V
LDO5 current Up to 250 mA
LDO6 voltage 1.8 V or 3.0 V
LDO6 current Up to 100 mA
LDO7 voltage 3.0 V
LDO7 current Up to 200 mA
LDO8 voltage 3.1 V
LDO8 current Up to 100 mA
LDO9 voltage 3.0 V
LDO9 current Up to 300 mA
LDO10 voltage 1.8 V
LDO10 current Up to 300 mA

8.2.1.2 Detailed Design Procedure

Table 8-2 lists the recommended external components.

Table 8-2 Recommended External Components

REFERENCE COMPONENTS COMPONENT(1) MANUFACTURER PART NUMBER VALUE EIA SIZE CODE(4) SIZE (mm) MASS PRODUCTION(2)
INPUT POWER SUPPLIES EXTERNAL COMPONENTS
CVCC, CVIN_DCDC_ANA, LDOAO Power input capacitors Murata GRM188R71A225KE15 2.2 µF, 10V 0603 1.6 × 0.8 × 0.8 Available(3)
CVDDIO I/O input capacitor Murata GRM188R60J475KE19 4.7 µF, 6.3V 0603 1.6 × 0.8 × 0.8 Available(3)
RGB LED EXTERNAL COMPONENTS
LEDA Yellow LED Lite On LTST-C190YKT 20mA, 2.1 V 0603 1.6 × 0.8 × 0.8 Available (3)
LEDB Green LED Lite On LTST-C190GKT 20mA, 2.1 V 0603 1.6 × 0.8 × 0.8 Available (3)
LEDC Red LED Lite On LTST-C190CKT 20mA, 2.1 V 0603 1.6 × 0.8 × 0.8 Available (3)
DCDC EXTERNAL COMPONENTS
CIN1, CIN2, CIN3, CIN4 Input capacitor Murata GRM188R60J106ME47 10 µF, 6.3V 0603 1.6 × 0.8 × 0.8 Available (3)
CoutDCDC1, CoutDCDC4 Output capacitor Murata GCM32ER70J476KE19 (Two capacitors per rail) 10 µF, 6.3V 0603 1.6 × 0.8 × 0.8 Available (3)
CoutDCDC2, CoutDCDC3 Output capacitor Murata GRM188R60J106ME47 10 µF, 6.3V 0603 1.6 × 0.8 × 0.8 Available (3)
L1, L2, L3, L4 Inductor Toko 1239AS-H-1R0N=P2 1 µH 2 × 2.5 Available(3)
LDO EXTERNAL COMPONENTS
CinLDO1210, CinLDO3, CinLDO67, CinLDO8, CinLDO9 Input capacitor Murata GRM188R71A225KE15 2.2 µF, 10V 0603 1.6 × 0.8 × 0.8 Available(3)
CinLDO4, CinLDO5 Input capacitor Murata GRM188R60J475KE19 4.7 µF, 6.3V 0603 1.6 × 0.8 × 0.8 Available(3)
CoutLDO3, CoutLDO1, CoutLDO2, CoutLDO6, CoutLDO7, CoutLDO8, CoutLDO9, CoutLDO10 Output capacitor Murata GRM188R71A225KE15 2.2 µF, 10V 0603 1.6 × 0.8 × 0.8 Available(3)
CoutLDO4, CoutLDO5 Output capacitor Murata GRM188R60J475KE19 4.7 µF, 6.3V 0603 1.6 × 0.8 × 0.8 Available(3)
(1) Component minimum and maximum tolerance values are specified in the electrical parameters section of each IP.
(2) This column refers to the criteria.
(3) Component used on the validation boards.
(4) The PACK column describes the external component package type.

8.2.1.2.1 Output Filter Design (Inductor and Output Capacitor)

8.2.1.2.1.1 Inductor Selection

The step-down converters are designed to operate with small external components such as 1-μH output inductors. The values given under the recommended operating conditions include tolerances and saturation effects and must not be violated for stable operation. The selected inductor must be rated for its DC resistance and saturation current. The DC resistance of the inductance will influence directly the efficiency of the converter. Therefore an inductor with lowest DC resistance should be selected for highest efficiency.

Equation 1 can be used to calculate the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 1. This is recommended because during heavy load transient the inductor current will rise above the calculated value.

Equation 1. TPS659121 TPS659122 eq4_dil_lvs950.gif

where

  • ΔIL = Peak-to-peak inductor ripple current
  • L = Inductor value
  • f = Switching frequency
Equation 2. TPS659121 TPS659122 eq5_ilmax_lvs950.gif

where

  • ILmax = Maximum inductor current

The highest inductor current will occur at maximum Vin.

Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents versus a comparable shielded inductor.

A more conservative approach is to select the inductor current rating just for the maximum switch current of the corresponding converter. It must be considered, that the core material from inductor to inductor differs and will have an impact on the efficiency especially at high switching frequencies.

Refer to Table 8-3 and the typical applications for possible inductors.

Table 8-3 Tested Inductors

INDUCTOR TYPE NOMINAL INDUCTANCE SUPPLIER
DFE252012 1 μH Toko
DFE322510 1 μH Toko
DFE322512 1 μH Toko
VLS201612ET-1R0 1 μH TDK
SPM3012T-1R0 1 μH TDK

8.2.1.2.1.2 Output Capacitor Selection

The control scheme of the DC-DC converters allow the use of small ceramic capacitors with a typical value as given in the recommended operating conditions, without having large output voltage under and overshoots during heavy load transients. Ceramic capacitors having low ESR values result in lowest output voltage ripple and are therefore recommended.

If ceramic output capacitors are used, the capacitor RMS ripple current rating will always meet the application requirements. Just for completeness the RMS ripple current is calculated as shown in Equation 3.

Equation 3. TPS659121 TPS659122 eq6_lrms_lvs950.gif

At nominal load current, the inductive converters operate in PWM mode and the overall output-voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor. See Equation 4.

Equation 4. TPS659121 TPS659122 eq7_dvout_lvs950.gif

Where the highest output voltage ripple occurs at the highest input voltage, Vin.

At light load currents, the converters operate in Power Save Mode and the output voltage ripple is dependent on the value of the output capacitor. The output voltage ripple is set by the internal comparator delay and the external capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage.

8.2.1.2.1.3 Input Capacitor Selection / Input Voltage

Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input-voltage spikes. The converters need a ceramic input capacitor of 10 μF. The input capacitor can be increased without any limit for better input voltage filtering. Ceramic capacitors suffer from the so-called dc bias effect. A dc voltage applied at a ceramic capacitor will change the effective capacitance to a value lower than the nominal value. Curves about that behavior are available at the capacitor manufacturers and need to be considered when using the capacitors in applications where a dc voltage is applied and a minimum capacitance must be maintained for proper functionality of the circuit. The values given in the Recommended operating Conditions for TPS65912x are for the capacitance. The actual capacitor used may have a larger nominal value that drops with the voltage applied to what is recommended. The capacitance drop depends on the voltage applied, so for a higher voltage; for example, the output voltage of a DC-DC converter or LDO, this must be considered when choosing a proper capacitor.

The input voltage for the step-down converters must be connected to pin VINDCDC1, VINDCDC2, VINDCDC3 and VINDCDC4. These pins need to be tied together with VIN_DCDC_ANA to the power source. VCC must be tied to the highest voltage in the system. If the load switch is used as switch on the output, VCC must be tied to the input voltage of VINDCDx and VIN_DCDC_ANA. If the load switch is used as a current limited switch on the input, VCC must be connected to pin LSI while LSO is connected to VINDCDCx and VINDCDC_ANA. The four step-down converters must not be supplied from different input voltages.

8.2.1.2.1.4 Output Capacitor Table

The DC-DC converters are designed for an output capacitance as listed under the Recommended Operating Conditions. A ceramic capacitor, such as X5R or X7R type, is required at the output. Table 8-4 lists capacitors used for TPS65912x.

Table 8-4 Possible Capacitors

Value Size Vendor Material and Rating
47 µF / 6.3 V 0805 Murata GRM21BR60J476ME15 Ceramic X5R
22 µF / 6.3 V 0805 Murata GRM21BR60J226M Ceramic X5R
10 µF / 10 V 0603 Murata GRM188R61A106ME69 Ceramic X5R
4.7 µF / 6.3 V 0603 Murata GRM188R60J475KE19 Ceramic X5R
4.7 µF / 6.3 V 0402 Murata GRM155R60J475ME87 Ceramic X5R

8.2.1.2.1.5 Voltage Change on DCDC1 to DCDC4

The output voltage of the DC-DC converters can be changed during operation by either the digital interfaces or by toggling the DCDCx_SEL pin or by entering SLEEP state if configured such.

8.2.1.3 Application Curves

TPS659121 TPS659122 dc1_ld_tr_wcs054.gif
VIN = 3.6 V VO = 1.1375 V
Figure 8-2 Load Transient Response DCDC1
TPS659121 TPS659122 dc3_ld_tr_wcs054.gif
VIN = 3.6 V VO = 1.1375 V
Figure 8-4 Load Transient Response DCDC3
TPS659121 TPS659122 dc1_lin_tr_wcs054.gif
VO = 1.1375 V IO = 2500 mA
Figure 8-6 Line Transient Response DCDC1
TPS659121 TPS659122 dc3_lin_tr_wcs054.gif
VO = 1.1375 V IO = 1500 mA
Figure 8-8 Line Transient Response DCDC3
TPS659121 TPS659122 ldo1_ld_tr1_wcs054.gif
VIN = 3.3 V VO = 3.0 V
Figure 8-10 Load Transient Response LDO1, LDO2, LDO3
TPS659121 TPS659122 ldo1_ln_tr1_wcs054.gif
IO = 100 mA VO = 1.2 V
Figure 8-12 Line Transient Response LDO1, LDO2, LDO3
TPS659121 TPS659122 ldo45_ld_tr2_wcs054.gif
VIN = 3.2 V VO = 2.7 V
Figure 8-14 Load Transient Response LDO4, LDO5
TPS659121 TPS659122 ldo4_ln_tr2_wcs054.gif
IO = 100 mA VO = 3.0 V
Figure 8-16 Line Transient Response LDO4, LDO5
TPS659121 TPS659122 ldo68_ld_tr2_wcs054.gif
VIN = 3.3 V VO = 2.85 V
Figure 8-18 Load Transient Response LDO6, LDO8
TPS659121 TPS659122 ldo6_ln_tr2_wcs054.gif
IO = 100 mA VO = 2.85 V
Figure 8-20 Line Transient Response LDO6, LDO8
TPS659121 TPS659122 ldo9_ld_tr1_wcs054.gif
VIN = 3.3 V VO = 2.85 V
Figure 8-22 Load Transient Response LDO9
TPS659121 TPS659122 ldo10_ln_tr1_wcs054.gif
IO = 300 mA VO = 1.8 V
Figure 8-24 Line Transient Response LDO10
TPS659121 TPS659122 dc2_ld_tr_wcs054.gif
VIN = 3.6 V VO = 2.25 V
Figure 8-3 Load Transient Response DCDC2
TPS659121 TPS659122 dc4_ld_tr_wcs054.gif
VIN = 3.6 V VO = 1.1375 V
Figure 8-5 Load Transient Response DCDC4
TPS659121 TPS659122 dc2_lin_tr_wcs054.gif
VO = 1.8 V IO = 750 mA
Figure 8-7 Line Transient Response DCDC2
TPS659121 TPS659122 dc4_lin_tr_wcs054.gif
VO = 1.1375 V IO = 3000 mA
Figure 8-9 Line Transient Response DCDC4
TPS659121 TPS659122 ldo1_ld_tr2_wcs054.gif
VIN = 1.8 V VO = 1.2 V
Figure 8-11 Load Transient Response LDO1, LDO2, LDO3
TPS659121 TPS659122 ldo45_ld_tr1_wcs054.gif
VIN = 2.0 V VO = 1.7 V
Figure 8-13 Load Transient Response LDO4, LDO5
TPS659121 TPS659122 ldo4_ln_tr1_wcs054.gif
IO = 100 mA VO = 1.7 V
Figure 8-15 Line Transient Response LDO4, LDO5
TPS659121 TPS659122 ldo68_ld_tr1_wcs054.gif
VIN = 3.3 V VO = 1.8 V
Figure 8-17 Load Transient Response LDO6, LDO8
TPS659121 TPS659122 ldo6_ln_tr1_wcs054.gif
IO = 100 mA VO = 1.8 V
Figure 8-19 Line Transient Response LDO6, LDO8
TPS659121 TPS659122 ldo7_ld_tr1_wcs054.gif
VIN = 3.2 V VO = 3.0 V
Figure 8-21 Load Transient Response LDO7
TPS659121 TPS659122 ldo10_ld_tr1_wcs054.gif
VIN = 3.3 V VO = 1.8 V
Figure 8-23 Load Transient Response LDO10

8.2.1.4 Layout

8.2.1.4.1 Layout Guidelines

As for all switching power supplies, the layout is an important step in the design. Proper function of the device demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If the layout is not carefully done, the regulators may show poor line and/or load regulation and stability issues, as well as EMI problems. It is critical to provide a low-impedance ground path. Therefore, use wide and short traces for the main current paths. The input capacitors must be placed as close as possible to the IC pins as well as the inductor and output capacitor.

Keep the common path to the GND pins, which returns the small signal components, and the high current of the output capacitors as short as possible to avoid ground noise. The VDCDCx trace should be connected right to the output capacitor and routed away from noisy components and traces (for example, the L1, L2, L3, and L4 traces).

The most critical connections are:

  • PGNDx
  • VDCDCx (positive output voltage sense connection)
  • VDCDCx_GND (ground-sense connection)
  • AGND
  • VINDCDCx, VINDCDC_ANA, VCC

The PGNDx pins are the ground connections of the power stages, so they will carry high dc- and ac- peak currents. A low impedance connection to the GND-plane is needed, which must be independent from other pins in order not to couple noise into other pins. No other pins must be connected to PGNDx pins.

The VDCDCx pins are the positive-sense connections for the feedback loop. The connection must be made directly to the positive terminal of the pad of the output capacitor. Do not tie the pin to the pad of the output inductor or anywhere in between inductor and capacitor. It is also a good practice to shield the connection by GND traces or a GND-plane.

VDCDCx_GND is a sense connection for GND and is only available for DCDC1 and DCDC4. The connection can either be made to the GND pad of the output capacitor (preferred) or to the GND-plane directly if there is a solid connection of the GND-plane to the output capacitor. The pin must not be connected to the PGNDx pins as this will couple switching noise into the feedback loop.

The AGND (analog ground) pin is the main GND connection for internal analog circuitry. A proper connection must be made to a GND plane directly by a via. AGND and DGND (located next to each other) may be connected and a via each be used to the GND-plane.

VINDCDCx, VINDCD_ANA and VCC are supply-voltage-input terminals and need to be properly bypassed by their input capacitors. The CAPACITANCE needed is given in the Section 5.3. As ceramic capacitors will change their capacitance based on the voltage applied, temperature and age, the influence of these parameters need to be considered when choosing the value of a capacitor. The input capacitors are ideally placed on the same layer as the IC, so the connection can be made short and directly on the same layer with multiple vias used from the GND terminal to the GND-plane.

For details about the layout for TPS659121 and TPS659122, see the EVM user's guide, which can be found in the product folder on ti.com.

8.2.1.4.2 Layout Example

TPS659121 TPS659122 tps659121-layout-example.gif Figure 8-25 Layout Example

8.3 Power Supply Recommendations

The TPS65912 device is designed to work with an analog supply voltage range from 2.7 V to 5.5 V. The input supply should be well regulated and connected to the VCC pin, as well as the DCDC and LDO input pins. If the input supply is located more than a few inches from the TPS65912 device, additional capacitance may be required in addition to the recommended input capacitors at the VCC pin and the DCDC and LDO input pins.