JAJSDU6A August   2017  – February 2019 TPS65919-Q1

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 チャネル 1 の機能図
  2. 2改訂履歴
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Attributes
      1.      Pin Attributes
    2. 3.2 Signal Descriptions
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics — LDO Regulators
    6. 4.6  Electrical Characteristics — SMPS1&2 in Dual-Phase Configuration
    7. 4.7  Electrical Characteristics — SMPS1, SMPS2, SMPS3, and SMPS4 Stand-Alone Regulators
    8. 4.8  Electrical Characteristics — Reference Generator (Bandgap)
    9. 4.9  Electrical Characteristics — 32-kHz RC Oscillators and SYNCCLKOUT Output Buffers
    10. 4.10 Electrical Characteristics — 12-Bit Sigma-Delta ADC
    11. 4.11 Electrical Characteristics — Thermal Monitoring and Shutdown
    12. 4.12 Electrical Characteristics — System Control Thresholds
    13. 4.13 Electrical Characteristics — Current Consumption
    14. 4.14 Electrical Characteristics — Digital Input Signal Parameters
    15. 4.15 Electrical Characteristics — Digital Output Signal Parameters
    16. 4.16 I/O Pullup and Pulldown Characteristics
    17. 4.17 Electrical Characteristics — I2C Interface
    18. 4.18 Timing Requirements — I2C Interface
    19. 4.19 Timing Requirements — SPI
    20. 4.20 Switching Characteristics — LDO Regulators
    21. 4.21 Switching Characteristics — SMPS1&2 in Dual-Phase Configuration
    22. 4.22 Switching Characteristics — SMPS1, SMPS2, SMPS3, and SMPS4 Stand-Alone Regulators
    23. 4.23 Switching Characteristics — Reference Generator (Bandgap)
    24. 4.24 Switching Characteristics — PLL for SMPS Clock Generation
    25. 4.25 Switching Characteristics — 32-kHz RC Oscillators and SYNCCLKOUT Output Buffers
    26. 4.26 Switching Characteristics — 12-Bit Sigma-Delta ADC
    27. 4.27 Typical Characteristics
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  Functional Block Diagram
    3. 5.3  Device State Machine
      1. 5.3.1  Embedded Power Controller
      2. 5.3.2  State Transition Requests
        1. 5.3.2.1 ON Requests
        2. 5.3.2.2 OFF Requests
        3. 5.3.2.3 SLEEP and WAKE Requests
      3. 5.3.3  Power Sequences
      4. 5.3.4  Device Power Up Timing
      5. 5.3.5  Power-On Acknowledge
        1. 5.3.5.1 POWERHOLD Mode
        2. 5.3.5.2 AUTODEVON Mode
      6. 5.3.6  BOOT Configuration
        1. 5.3.6.1 Boot Pin Usage and Connection
      7. 5.3.7  Reset Levels
      8. 5.3.8  INT
      9. 5.3.9  Warm Reset
      10. 5.3.10 RESET_IN
    4. 5.4  Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)
      1. 5.4.1 Step-Down Regulators
        1. 5.4.1.1 Output Voltage and Mode Selection
        2. 5.4.1.2 Clock Generation for SMPS
        3. 5.4.1.3 Current Monitoring and Short Circuit Detection
        4. 5.4.1.4 POWERGOOD
        5. 5.4.1.5 DVS-Capable Regulators
          1. 5.4.1.5.1 Non DVS-Capable Regulators
        6. 5.4.1.6 Step-Down Converters SMPS1, SMPS2 or SMPS1&2
        7. 5.4.1.7 Step-Down Converters SMPS3, and SMPS4
      2. 5.4.2 Low Dropout Regulators (LDOs)
        1. 5.4.2.1 LDOVANA
        2. 5.4.2.2 LDOVRTC
        3. 5.4.2.3 LDO1 and LDO2
        4. 5.4.2.4 Low-Noise LDO (LDO5)
        5. 5.4.2.5 Other LDOs
    5. 5.5  SMPS and LDO Input Supply Connections
    6. 5.6  First Supply Detection
    7. 5.7  Long-Press Key Detection
    8. 5.8  12-Bit Sigma-Delta General-Purpose ADC (GPADC)
      1. 5.8.1 Asynchronous Conversion Request (SW)
      2. 5.8.2 Periodic Conversion (AUTO)
      3. 5.8.3 Calibration
    9. 5.9  General-Purpose I/Os (GPIO Pins)
    10. 5.10 Thermal Monitoring
      1. 5.10.1 Hot-Die Function (HD)
      2. 5.10.2 Thermal Shutdown
    11. 5.11 Interrupts
    12. 5.12 Control Interfaces
      1. 5.12.1 I2C Interfaces
        1. 5.12.1.1 I2C Implementation
        2. 5.12.1.2 F/S Mode Protocol
        3. 5.12.1.3 HS Mode Protocol
      2. 5.12.2 Serial Peripheral Interface (SPI)
        1. 5.12.2.1 SPI Modes
        2. 5.12.2.2 SPI Protocol
    13. 5.13 OTP Configuration Memory
    14. 5.14 Watchdog Timer (WDT)
    15. 5.15 System Voltage Monitoring
    16. 5.16 Register Map
      1. 5.16.1 Functional Register Mapping
    17. 5.17 Device Identification
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 SMPS Input Capacitors
        2. 6.2.2.2 SMPS Output Capacitors
        3. 6.2.2.3 SMPS Inductors
        4. 6.2.2.4 LDO Input Capacitors
        5. 6.2.2.5 LDO Output Capacitors
        6. 6.2.2.6 VCCA
          1. 6.2.2.6.1 Meeting the Power-Down Sequence
          2. 6.2.2.6.2 Maintaining Sufficient Input Voltage
        7. 6.2.2.7 VIO_IN
        8. 6.2.2.8 GPADC
      3. 6.2.3 Application Curves
    3. 6.3 Layout
      1. 6.3.1 Layout Guidelines
      2. 6.3.2 Layout Example
    4. 6.4 Power Supply Coupling and Bulk Capacitors
  7. 7デバイスおよびドキュメントのサポート
    1. 7.1 デバイス・サポート
      1. 7.1.1 Third-Party Products Disclaimer
      2. 7.1.2 デバイスの項目表記
    2. 7.2 ドキュメントのサポート
      1. 7.2.1 関連資料
    3. 7.3 ドキュメントの更新通知を受け取る方法
    4. 7.4 Community Resources
    5. 7.5 商標
    6. 7.6 静電気放電に関する注意事項
    7. 7.7 Glossary
  8. 8メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3.1 Layout Guidelines

As in every switch-mode-supply design, general layout rules apply:

  • Use a solid ground-plane for the power ground (PGND)
  • Connect those grounds at a star-point that is located ideally underneath the device.
  • Place input capacitors as close as possible to the input pins of the device. This placement is paramount and more important than the output-loop.
  • Place the inductor and output capacitor as close as possible to the phase node (or switch-node) of the device.
  • Keep the loop-area formed by the phase-node, inductor, output-capacitor, and PGND as small as possible.
  • For traces and vias on power-lines, keep inductance and resistance as small as possible by using wide traces. Avoid switching layers but, if needed, use plenty of vias.

The goal of these guidelines is a layout that minimizes emissions, maximizes EMI immunity, and maintains a safe operating area (SOA) for the device.

To minimize the spiking at the phase-node for both the high-side (VIN to SWx) and low-side (SWx to PGND), the decoupling of VIN is the most important guideline. Appropriate decoupling and thorough layout should ensure that the spikes never exceed 7V across the high-side and low-side FETs.

Figure 6-9 shows a set of guidelines regarding parasitic inductance and resistance that are recommended.

TPS65919-Q1 layout_parasitic_slvsco4.gifFigure 6-9 Parasitic Inductance and Resistance

Table 6-3 lists the maximum allowable parasitic (inductance measured at 100 MHz) and the achievable values in an optimized layout.

Table 6-3 Maximum Allowable Parasitic

CONNECTION MAXIMUM ALLOWABLE INDUCTANCE MAXIMUM ALLOWABLE RESISTANCE OPTIMIZED LAYOUT (EVM) INDUCTANCE OPTIMIZED LAYOUT (EVM) RESISTANCE
PowerPlane to CIN N/A N/A for SOA
Maintain a low resistance value for efficiency 		N/A N/A for SOA
Maintain a low resistance value for efficiency
CIN to SMPSx_IN 0.5 nH 2 mΩ SMPS1 0.2 nH SMPS1 1.1 mΩ
SMPS2 0.2 nH SMPS2 1.6 mΩ
SMPS3 0.2 nH SMPS3 1.5 mΩ
SMPS4 0.2 nH SMPS4 1.8 mΩ
CIN to PGND 0.5 nH 2 mΩ SMPS1 0.3 nH SMPS1 0.4 mΩ
SMPS2 0.3 nH SMPS2 0.4 mΩ
SMPS3 0.4 nH SMPS3 0.5 mΩ
SMPS4 0.3 nH SMPS4 0.6 mΩ
SMPSx_SW to inductor N/A N/A for SOA
Maintain a low resistance value for efficiency 		N/A SMPS1 1 mΩ
SMPS2 0.7 mΩ
SMPS3 1 mΩ
SMPS4 0.7 mΩ
Inductor to COUT N/A N/A for SOA
Maintain a low resistance value for efficiency 		N/A N/A for SOA
Maintain a low resistance value for efficiency
COUT to GND Use dedicated GND plane to keep inductance low 1 mΩ SMPS1 0.8 nH SMPS1 0.7 mΩ
SMPS2 0.6 nH SMPS2 0.8 mΩ
SMPS3 0.5 nH SMPS3 0.6 mΩ
SMPS4 0.4 nH SMPS4 0.6 mΩ
GND (CIN) to GND (COUT) Use dedicated GND plane to keep inductance low 1 mΩ Use dedicated GND plane to keep inductance low mΩ

Texas Instruments recommends measuring the voltages across the high-side FET (voltage at SMPSx_IN versus SMPSx_SW) and the low-side FET (SMPSx_SW versus PGND) with a high bandwidth, high sampling-rate scope with a low-capacitance probe (ideally a differential probe). Measure the voltages as close as possible to the device pins and verify the amplitude of the spikes. A small-loop ground connection to PGND is essential.

When measuring the voltage difference between the SMPSx_IN and SMPSx_SW pins, there should be a maximum of 7 V when measuring at the pins. Similarly, when measuring the voltage difference between the SMPSx_SW and PGND pins, there should be a maximum of 7 V when measuring at the pins.

For more information on cursor-positioning, see Figure 6-10 and Figure 6-11.

TPS65919-Q1 layout_hs_swcs095.gif
Measure across the high-side FET (SMPSx_IN – SMPSx_SW) as close to the IC as possible. The preferred measurement is with a differential probe. The negative side of the probe should be at SMPSx_SW and the positive side of the probe should measure SMPSx_IN. As shown in this image, the voltage across the high-side FET should not exceed 7 V. Repeat the measurement for all SMPSs in use.
Figure 6-10 Measuring the High-Side FET (Differentially)
TPS65919-Q1 layout_ls_swcs095.gif
Measure across the low-side FET (SMPSx_SW – GND) as close to the IC as possible. The preferred measurement is with a differential probe. The negative side of the probe should be at GND and the positive side of the probe should measure SMPSx_SW. As shown in this image, the voltage across the low-side FET should not exceed 7 V.Repeat the measurement for all SMPSs in use.
Figure 6-11 Measuring the Low-Side FET (Differentially)