JAJSDU6A August   2017  – February 2019 TPS65919-Q1

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 チャネル 1 の機能図
  2. 2改訂履歴
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Attributes
      1.      Pin Attributes
    2. 3.2 Signal Descriptions
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics — LDO Regulators
    6. 4.6  Electrical Characteristics — SMPS1&2 in Dual-Phase Configuration
    7. 4.7  Electrical Characteristics — SMPS1, SMPS2, SMPS3, and SMPS4 Stand-Alone Regulators
    8. 4.8  Electrical Characteristics — Reference Generator (Bandgap)
    9. 4.9  Electrical Characteristics — 32-kHz RC Oscillators and SYNCCLKOUT Output Buffers
    10. 4.10 Electrical Characteristics — 12-Bit Sigma-Delta ADC
    11. 4.11 Electrical Characteristics — Thermal Monitoring and Shutdown
    12. 4.12 Electrical Characteristics — System Control Thresholds
    13. 4.13 Electrical Characteristics — Current Consumption
    14. 4.14 Electrical Characteristics — Digital Input Signal Parameters
    15. 4.15 Electrical Characteristics — Digital Output Signal Parameters
    16. 4.16 I/O Pullup and Pulldown Characteristics
    17. 4.17 Electrical Characteristics — I2C Interface
    18. 4.18 Timing Requirements — I2C Interface
    19. 4.19 Timing Requirements — SPI
    20. 4.20 Switching Characteristics — LDO Regulators
    21. 4.21 Switching Characteristics — SMPS1&2 in Dual-Phase Configuration
    22. 4.22 Switching Characteristics — SMPS1, SMPS2, SMPS3, and SMPS4 Stand-Alone Regulators
    23. 4.23 Switching Characteristics — Reference Generator (Bandgap)
    24. 4.24 Switching Characteristics — PLL for SMPS Clock Generation
    25. 4.25 Switching Characteristics — 32-kHz RC Oscillators and SYNCCLKOUT Output Buffers
    26. 4.26 Switching Characteristics — 12-Bit Sigma-Delta ADC
    27. 4.27 Typical Characteristics
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  Functional Block Diagram
    3. 5.3  Device State Machine
      1. 5.3.1  Embedded Power Controller
      2. 5.3.2  State Transition Requests
        1. 5.3.2.1 ON Requests
        2. 5.3.2.2 OFF Requests
        3. 5.3.2.3 SLEEP and WAKE Requests
      3. 5.3.3  Power Sequences
      4. 5.3.4  Device Power Up Timing
      5. 5.3.5  Power-On Acknowledge
        1. 5.3.5.1 POWERHOLD Mode
        2. 5.3.5.2 AUTODEVON Mode
      6. 5.3.6  BOOT Configuration
        1. 5.3.6.1 Boot Pin Usage and Connection
      7. 5.3.7  Reset Levels
      8. 5.3.8  INT
      9. 5.3.9  Warm Reset
      10. 5.3.10 RESET_IN
    4. 5.4  Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)
      1. 5.4.1 Step-Down Regulators
        1. 5.4.1.1 Output Voltage and Mode Selection
        2. 5.4.1.2 Clock Generation for SMPS
        3. 5.4.1.3 Current Monitoring and Short Circuit Detection
        4. 5.4.1.4 POWERGOOD
        5. 5.4.1.5 DVS-Capable Regulators
          1. 5.4.1.5.1 Non DVS-Capable Regulators
        6. 5.4.1.6 Step-Down Converters SMPS1, SMPS2 or SMPS1&2
        7. 5.4.1.7 Step-Down Converters SMPS3, and SMPS4
      2. 5.4.2 Low Dropout Regulators (LDOs)
        1. 5.4.2.1 LDOVANA
        2. 5.4.2.2 LDOVRTC
        3. 5.4.2.3 LDO1 and LDO2
        4. 5.4.2.4 Low-Noise LDO (LDO5)
        5. 5.4.2.5 Other LDOs
    5. 5.5  SMPS and LDO Input Supply Connections
    6. 5.6  First Supply Detection
    7. 5.7  Long-Press Key Detection
    8. 5.8  12-Bit Sigma-Delta General-Purpose ADC (GPADC)
      1. 5.8.1 Asynchronous Conversion Request (SW)
      2. 5.8.2 Periodic Conversion (AUTO)
      3. 5.8.3 Calibration
    9. 5.9  General-Purpose I/Os (GPIO Pins)
    10. 5.10 Thermal Monitoring
      1. 5.10.1 Hot-Die Function (HD)
      2. 5.10.2 Thermal Shutdown
    11. 5.11 Interrupts
    12. 5.12 Control Interfaces
      1. 5.12.1 I2C Interfaces
        1. 5.12.1.1 I2C Implementation
        2. 5.12.1.2 F/S Mode Protocol
        3. 5.12.1.3 HS Mode Protocol
      2. 5.12.2 Serial Peripheral Interface (SPI)
        1. 5.12.2.1 SPI Modes
        2. 5.12.2.2 SPI Protocol
    13. 5.13 OTP Configuration Memory
    14. 5.14 Watchdog Timer (WDT)
    15. 5.15 System Voltage Monitoring
    16. 5.16 Register Map
      1. 5.16.1 Functional Register Mapping
    17. 5.17 Device Identification
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 SMPS Input Capacitors
        2. 6.2.2.2 SMPS Output Capacitors
        3. 6.2.2.3 SMPS Inductors
        4. 6.2.2.4 LDO Input Capacitors
        5. 6.2.2.5 LDO Output Capacitors
        6. 6.2.2.6 VCCA
          1. 6.2.2.6.1 Meeting the Power-Down Sequence
          2. 6.2.2.6.2 Maintaining Sufficient Input Voltage
        7. 6.2.2.7 VIO_IN
        8. 6.2.2.8 GPADC
      3. 6.2.3 Application Curves
    3. 6.3 Layout
      1. 6.3.1 Layout Guidelines
      2. 6.3.2 Layout Example
    4. 6.4 Power Supply Coupling and Bulk Capacitors
  7. 7デバイスおよびドキュメントのサポート
    1. 7.1 デバイス・サポート
      1. 7.1.1 Third-Party Products Disclaimer
      2. 7.1.2 デバイスの項目表記
    2. 7.2 ドキュメントのサポート
      1. 7.2.1 関連資料
    3. 7.3 ドキュメントの更新通知を受け取る方法
    4. 7.4 Community Resources
    5. 7.5 商標
    6. 7.6 静電気放電に関する注意事項
    7. 7.7 Glossary
  8. 8メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

3.1 Pin Attributes

Pin Attributes

PIN I/O DESCRIPTION CONNECTION IF NOT USED PU/PD(1)
NAME NO.
REFERENCE
REFGND 41 — System reference ground Ground —
VBG 40 O Bandgap reference voltage — —
STEP-DOWN CONVERTERS (SMPSs)
SMPS1_IN 32 I Power input for SMPS1 System supply —
SMPS1_FDBK 33 I Output voltage-sense (feedback) input for SMPS1 or differential voltage-sense (feedback) positive input for SMPS12 in dual-phase configuration Ground —
SMPS1_SW 31 O Switch node of SMPS1; connect output inductor Floating —
SMPS2_IN 29 I Power input for SMPS2 System supply —
SMPS2_FDBK 28 I Output voltage-sense (feedback) input for SMPS2 or differential voltage-sense (feedback) negative input for SMPS12 in dual-phase configuration Ground —
SMPS2_SW 30 O Switch node of SMPS2; connect output inductor Floating —
SMPS3_IN 10 I Power input for SMPS3 System supply —
SMPS3_FDBK 9 I Output voltage-sense (feedback) input for SMPS3 Ground —
SMPS3_SW 11 O Switch node of SMPS3; connect output inductor Floating —
SMPS4_IN 18 I Power input for SMPS4 System supply —
SMPS4_FDBK 17 I Output voltage-sense (feedback) input for SMPS4 Ground —
SMPS4_SW 19 O Switch node of SMPS4; connect output inductor Floating —
SMPS_IN 46 I Power input for SMPS System supply —
NC 45 — No Connection Floating —
NC 47 — No Connection Floating —
LOW DROPOUT REGULATORS
LDO12_IN 22 I Power input voltage for LDO1 and LDO2 regulators System supply —
LDO1_OUT 23 O LDO1 output voltage Floating —
LDO2_OUT 21 O LDO2 output voltage Floating —
LDO_IN 5 I Power input voltage for LDO regulator System supply —
NC 6 — No Connection Floating —
LDO4_IN 8 I Power input voltage for LDO4 regulator System supply —
LDO4_OUT 7 O LDO4 output voltage Floating —
LDO5_IN 3 I Power input voltage for LDO5 regulator System supply —
LDO5_OUT 4 O LDO5 output voltage Floating —
LOW-DROPOUT REGULATORS (INTERNAL)
LDOVRTC_OUT 44 O LDOVRTC output voltage. To support rapid power off and on, connect a pulldown resistor on the LDOVRTC_OUT pin. See Section 5.15 for more details. — —
LDOVANA_OUT 43 O LDOVANA output voltage — —
GPADC
ADCIN1 38 I GPADC input 1 Ground —
ADCIN2 39 I GPADC input 2 Ground —
CLOCKING
SYNCCLKOUT 48 O Primary function: 2.2-MHz fallback switching frequency for SMPS Floating —
Secondary function: 32-kHz digital-gated output clock when VIO_IN input supply is present
SYSTEM CONTROL
BOOT 16 I Boot ball for power-up sequence selection Ground or VRTC —
GPIO_0 12 I/O Primary function: General-purpose input(2) and output Ground or VRTC PPD
I Secondary function: ENABLE2 which is the peripheral power request input 2 Floating PPD(2)
Secondary function: PWRDOWN input Ground or VIO PPD
O Secondary function: REGEN1 which is the external regulator enable output 1 Floating —
GPIO_1 13 I/O Primary function: General-purpose input(2) and output Floating PPD
I Secondary function: RESET_IN which is the reset input Floating PPD
Secondary function: VBUS_SENSE input Ground or VIO —
Secondary function: NRESWARM which is the warm reset input VRTC PPD
GPIO_2 2 I/O Primary function: General-purpose input(2) and output Floating PPU
PPD
I Secondary function: ENABLE1 which is the peripheral power request input 1 Floating PPU
PPD(2)
I/O Secondary function: I2C2_SDA_SDO which is the DVS I2C serial bidirectional data (external pullup) and the SPI output data signal Floating —
GPIO_3 14 I/O Primary function: General-purpose input(2) and output Floating PPD
O Secondary function: REGEN1 which is the external regulator enable output 1 Floating —
I Secondary function: ENABLE2 which is the peripheral power request input 2 PPD(2)
I Secondary function: SYNCDCDC which is the synchronization signal for SMPS switching Floating PPD(2)
GPIO_4 1 I/O Primary function: General-purpose input(2) and output Floating PPU
PPD
O Secondary function: REGEN2 which is the external regulator enable output 2 Floating —
I Secondary function: I2C2_SCL_SCE which is the DVS I2C serial clock (external pullup) and the SPI chip enable signal Floating —
GPIO_5 15 I/O Primary function: General-purpose input(2) and output Ground PPD
I Secondary function: POWERHOLD input Ground or VIO PPD
O Secondary function: REGEN3 which is the external regulator enable output 3 Floating —
GPIO_6 27 I/O Primary function: General-purpose input(2) and output Ground PPD
I Secondary function: NSLEEP request signal Floating PPU(2)
PPD
O Secondary function: POWERGOOD which is the indication signal for valid regulator output voltages Floating —
O Secondary function: REGEN3 which is the external regulator enable output 3 Floating —
I2C1_SCL_SCK 35 I Control I2C serial clock (external pullup) and SPI clock signal — —
I2C1_SDA_SDI 36 I/O Control I2C serial bidirectional data (external pullup) and SPI input data signal — —
INT 26 O Maskable interrupt output request to the host processor — —
PWRON 24 I External power-on event (on-button switch-on event) Floating PU
RESET_OUT 25 O System reset or power on output (low = reset, high = active or sleep) Floating —
PROGRAMMING, TESTING
VPROG 20 I Primary function: OTP programming voltage Ground or floating —
O Secondary function: TESTV Floating —
POWER SUPPLIES
VCCA 42 I Analog input voltage for internal LDOs System supply —
VCC_SENSE 37 I System supply sense line System supply —
VIO_IN 34 I Digital supply input for GPIOs and I/O supply voltage N/A —
(1) The PU/PD column shows the pullup and pulldown resistors on the digital input lines. Pullup and pulldown resistors: PU = Pullup, PD = Pulldown, PPU = Software-programmable pullup, PPD = Software-programmable pulldown.
(2) Default option.