JAJSDU6A August   2017  – February 2019 TPS65919-Q1

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 チャネル 1 の機能図
  2. 2改訂履歴
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Attributes
      1.      Pin Attributes
    2. 3.2 Signal Descriptions
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics — LDO Regulators
    6. 4.6  Electrical Characteristics — SMPS1&2 in Dual-Phase Configuration
    7. 4.7  Electrical Characteristics — SMPS1, SMPS2, SMPS3, and SMPS4 Stand-Alone Regulators
    8. 4.8  Electrical Characteristics — Reference Generator (Bandgap)
    9. 4.9  Electrical Characteristics — 32-kHz RC Oscillators and SYNCCLKOUT Output Buffers
    10. 4.10 Electrical Characteristics — 12-Bit Sigma-Delta ADC
    11. 4.11 Electrical Characteristics — Thermal Monitoring and Shutdown
    12. 4.12 Electrical Characteristics — System Control Thresholds
    13. 4.13 Electrical Characteristics — Current Consumption
    14. 4.14 Electrical Characteristics — Digital Input Signal Parameters
    15. 4.15 Electrical Characteristics — Digital Output Signal Parameters
    16. 4.16 I/O Pullup and Pulldown Characteristics
    17. 4.17 Electrical Characteristics — I2C Interface
    18. 4.18 Timing Requirements — I2C Interface
    19. 4.19 Timing Requirements — SPI
    20. 4.20 Switching Characteristics — LDO Regulators
    21. 4.21 Switching Characteristics — SMPS1&2 in Dual-Phase Configuration
    22. 4.22 Switching Characteristics — SMPS1, SMPS2, SMPS3, and SMPS4 Stand-Alone Regulators
    23. 4.23 Switching Characteristics — Reference Generator (Bandgap)
    24. 4.24 Switching Characteristics — PLL for SMPS Clock Generation
    25. 4.25 Switching Characteristics — 32-kHz RC Oscillators and SYNCCLKOUT Output Buffers
    26. 4.26 Switching Characteristics — 12-Bit Sigma-Delta ADC
    27. 4.27 Typical Characteristics
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  Functional Block Diagram
    3. 5.3  Device State Machine
      1. 5.3.1  Embedded Power Controller
      2. 5.3.2  State Transition Requests
        1. 5.3.2.1 ON Requests
        2. 5.3.2.2 OFF Requests
        3. 5.3.2.3 SLEEP and WAKE Requests
      3. 5.3.3  Power Sequences
      4. 5.3.4  Device Power Up Timing
      5. 5.3.5  Power-On Acknowledge
        1. 5.3.5.1 POWERHOLD Mode
        2. 5.3.5.2 AUTODEVON Mode
      6. 5.3.6  BOOT Configuration
        1. 5.3.6.1 Boot Pin Usage and Connection
      7. 5.3.7  Reset Levels
      8. 5.3.8  INT
      9. 5.3.9  Warm Reset
      10. 5.3.10 RESET_IN
    4. 5.4  Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)
      1. 5.4.1 Step-Down Regulators
        1. 5.4.1.1 Output Voltage and Mode Selection
        2. 5.4.1.2 Clock Generation for SMPS
        3. 5.4.1.3 Current Monitoring and Short Circuit Detection
        4. 5.4.1.4 POWERGOOD
        5. 5.4.1.5 DVS-Capable Regulators
          1. 5.4.1.5.1 Non DVS-Capable Regulators
        6. 5.4.1.6 Step-Down Converters SMPS1, SMPS2 or SMPS1&2
        7. 5.4.1.7 Step-Down Converters SMPS3, and SMPS4
      2. 5.4.2 Low Dropout Regulators (LDOs)
        1. 5.4.2.1 LDOVANA
        2. 5.4.2.2 LDOVRTC
        3. 5.4.2.3 LDO1 and LDO2
        4. 5.4.2.4 Low-Noise LDO (LDO5)
        5. 5.4.2.5 Other LDOs
    5. 5.5  SMPS and LDO Input Supply Connections
    6. 5.6  First Supply Detection
    7. 5.7  Long-Press Key Detection
    8. 5.8  12-Bit Sigma-Delta General-Purpose ADC (GPADC)
      1. 5.8.1 Asynchronous Conversion Request (SW)
      2. 5.8.2 Periodic Conversion (AUTO)
      3. 5.8.3 Calibration
    9. 5.9  General-Purpose I/Os (GPIO Pins)
    10. 5.10 Thermal Monitoring
      1. 5.10.1 Hot-Die Function (HD)
      2. 5.10.2 Thermal Shutdown
    11. 5.11 Interrupts
    12. 5.12 Control Interfaces
      1. 5.12.1 I2C Interfaces
        1. 5.12.1.1 I2C Implementation
        2. 5.12.1.2 F/S Mode Protocol
        3. 5.12.1.3 HS Mode Protocol
      2. 5.12.2 Serial Peripheral Interface (SPI)
        1. 5.12.2.1 SPI Modes
        2. 5.12.2.2 SPI Protocol
    13. 5.13 OTP Configuration Memory
    14. 5.14 Watchdog Timer (WDT)
    15. 5.15 System Voltage Monitoring
    16. 5.16 Register Map
      1. 5.16.1 Functional Register Mapping
    17. 5.17 Device Identification
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 SMPS Input Capacitors
        2. 6.2.2.2 SMPS Output Capacitors
        3. 6.2.2.3 SMPS Inductors
        4. 6.2.2.4 LDO Input Capacitors
        5. 6.2.2.5 LDO Output Capacitors
        6. 6.2.2.6 VCCA
          1. 6.2.2.6.1 Meeting the Power-Down Sequence
          2. 6.2.2.6.2 Maintaining Sufficient Input Voltage
        7. 6.2.2.7 VIO_IN
        8. 6.2.2.8 GPADC
      3. 6.2.3 Application Curves
    3. 6.3 Layout
      1. 6.3.1 Layout Guidelines
      2. 6.3.2 Layout Example
    4. 6.4 Power Supply Coupling and Bulk Capacitors
  7. 7デバイスおよびドキュメントのサポート
    1. 7.1 デバイス・サポート
      1. 7.1.1 Third-Party Products Disclaimer
      2. 7.1.2 デバイスの項目表記
    2. 7.2 ドキュメントのサポート
      1. 7.2.1 関連資料
    3. 7.3 ドキュメントの更新通知を受け取る方法
    4. 7.4 Community Resources
    5. 7.5 商標
    6. 7.6 静電気放電に関する注意事項
    7. 7.7 Glossary
  8. 8メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.15 System Voltage Monitoring

Comparators that monitor the voltage on the VCC_SENSE, and VCCA pins control the power state machine of the TPS65919-Q1 device. For electrical parameters, see Section 4.12.

    PORWhen the supply at the VCCA pin is below the POR threshold, the TPS65919-Q1 device is in the NO SUPPLY state. All functionality is off. The device moves from the NO SUPPLY state to the BACKUP state when the voltage in VCCA rises above the POR threshold.
    VSYS_LOWhen the voltage on the VCCA pin rises above VSYS_LO, the device enters from the BACKUP state to the OFF state. When the device is in an ACTIVE, SLEEP, or OFF state and the voltage on VCCA decreases below the VSYS_LO level, the device enters backup mode. When the device transitions from the ACTIVE state to the BACKUP state, all active SMPS and LDO regulators, except LDOVRTC, are disabled simultaneously. There is a 180-µs deglitch time after VCCA becomes less than VSYS_LO and before the regulators are disabled. The level of VSYS_LO is OTP programmable.
    VSYS_MONDuring power up, the value of VSYS_HI OTP is used as a threshold for the VSYS_MON comparator which is gating PMIC start-up (that is, as a threshold for transition from the OFF state to the ACTIVE state). The VSYS_MON comparator monitors the VCC_SENSE pin. After power up, software can configure the comparator threshold in the VSYS_MON register.

Figure 5-25 shows a block diagram of the system comparators and Figure 5-26 shows the state transitions.

TPS65919-Q1 System_Comparators_Auto_SLVSCO4.gifFigure 5-25 System Comparators
TPS65919-Q1 State_Transitions_SLVSCO4.gifFigure 5-26 State Transitions

NOTE

To generate a POR from a falling VCC, VCC is sampled every 1 ms and compared to the POR threshold. In case VCC is discharged and resupplied quickly, a POR may not be reliably generated if VCC crosses the POR threshold between samples. Another way to generate POR is to discharge the LDOVRTC regulator to 0 V after VCC is removed. With no external load, this could take seconds for the LDOVRTC output to discharge to 0 V. The PMIC should not be restarted after VCC is removed but before LDOVRTC is discharged to 0 V. If necessary, TI recommends adding a pulldown resistor from the LDOVRTC output to GND with a minimum of 3.9 kΩ to speed up the LDOVRTC discharge time.

The value of the pulldown resistor should be chosen based on the desired discharge time and acceptable current draw in the OFF state, but no greater than 0.5 mA. Use Equation 7 to calculate the pulldown resistor based on the desired discharge time.

Equation 7. TPS65919-Q1 tps65916-rpd-equation.gif

where

  • tdischarge = discharge time of the VRTC output
  • RPD = pulldown resistance from the VRTC output to GND
  • CO = output capacitance on the VRTC line (typically 2.2 µF)

Because LDOVRTC is always on when VCC is supplied, additional current is drawn through the pulldown resistor. The output current of LDOVRTC while the PMIC is in OFF state should not exceed 0.5 mA. Use Equation 8 to calculate the pulldown current.

Equation 8. TPS65919-Q1 tps65916-ipd-equation.gif

where

  • IPD = current through the pulldown resistor
  • RPD = pulldown resistance from the VRTC regulator

To use comparators in the system:

  • The VSYS_HI and VSYS_LO thresholds are defined in the OTP. Software cannot change these levels.
  • After startup, the VSYS_MON comparator is automatically disabled. Software can select new threshold levels using the VSYS_MON register and then enable the comparators.
  • To have the same coding for rising and falling edge, the VSYS_MON comparator does not include hysteresis and thus can generate multiple interrupts when the voltage level is at threshold level. New interrupt generation has a 125-µs debounce time. This time lets software mask the interrupt and update the threshold level or disable the comparator before receiving a new interrupt.

Figure 5-27 shows more details on VSYS_MON comparator. When the VSYS_MON comparator is enabled, and the internal buffer is bypassed, the input impedance at VCC_SENSE pin is 500 kΩ (typical). When the comparator is disabled, the VCC_SENSE pin is in the high-impedance state. If GPADC is enabled to measure channel 2 or channel 3, 40 kΩ is added in parallel to the corresponding comparator. See Table 5-9 for GPADC input range.

To enable system voltage sensing above 5.25 V, an external resistive divider can be used. Internal buffers can be enabled by setting the OTP bit HIGH_VCC_SENSE to 1 to provide high impedance for the external resistive dividers. The maximum input level for the internal buffer is VCCA – 1 V.

TPS65919-Q1 VCC_SENSE_slvsco4.gif
1. HIGH_VCC_SENSE = 0: buffer bypassed (not enabled). HIGH_VCC_SENSE = 1: buffer enabled, bypass disabled (Hi-Z at SENSE input)
Figure 5-27 VSYS_MON Comparator Details