Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the controller device. The controller device releases the SDA line (HIGH) during the acknowledge clock pulse. The device pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The device generates an acknowledge after each byte has been received.

There is one exception to the acknowledge after every byte rule. When the controller device is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out of the target device. This negative acknowledge still includes the acknowledge clock pulse (generated by the controller device), but the SDA line is not pulled down.

After the START condition, the bus controller device sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE and a 1 indicates a READ. The second byte selects the register to which the data is written. The third byte contains data to write to the selected register. Figure 8-53 shows an example bit format of device address 110000-Bin = 60Hex.

Figure 8-53 Example Device Address

For safety applications, the device supports read and write protocols with embedded CRC data fields. In a write cycle, the I²C controller device (the MCU) must provide the 8-bit CRC value after sending the write data bits and receiving the ACK from the target (the TPS6593-Q1 PMIC). The CRC value must be calculated from every bit included in the write protocol except the ACK bits from the target. See CRC Calculation for I2C and SPI Interface Protocols. In a read cycle, the I²C target must provide the 8-bit CRC value after sending the read data bits and the ACK bit, and expect to receive the NACK from the controller at the end of the protocol. The CRC value must be calculated from every bit included in the read protocol except the ACK and NACK bits. See CRC Calculation for I2C and SPI Interface Protocols.

The embedded CRC field can be enabled or deactivated from the protocol by setting the I2C1_SPI_CRC_EN register bit to '1' - enabled, '0' - deactivated. The default of this bit is configurable through the NVM.

In case the calculated CRC-value does not match the received CRC-check-sum, an I²C-CRC-error is detected, the COMM_CRC_ERR_INT bit is set, unless it is masked by the COMM_CRC_ERR_MASK bit. The MCU must clear this bit by writing a ‘1’ to the COMM_CRC_ERR_INT bit.

When the CRC field is enabled, in the case when MCU attempts to write to a read-only register or a register-address that does not exist, the device sets the COMM_ADR_ERR_INT bit, unless the COMM_ADR_ERR_MASK bit is set. The MCU must clear this bit by writing a ‘1’ to the COMM_ADR_ERR_INT bit.

Figure 8-54 I²C Write Cycle without CRC

The I²C controller device (the MCU) provides R_CRC[7:0], which is calculated from the I2C_ID, R/W, ADDR, and the WDATA bits (24 bits). See CRC Calculation for I2C and SPI Interface Protocols.

Figure 8-55 I²C Write Cycle with CRC

When READ function is to be accomplished, a WRITE function must precede the READ function as shown above.

Figure 8-56 I²C Read Cycle without CRC

The I²C target device (the TPS6593-Q1) provides T_CRC[7:0], which is calculated from the I2C_ID, R/W, ADDR, I2C_ID, R/W, and the RDATA bits (32 bits). See CRC Calculation for I2C and SPI Interface Protocols.

Figure 8-57 I²C READ Cycle with CRC