JAJSLW7B December   2020  – September 2023 TPS6593-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
    1.     5
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Pin Configuration and Functions
    1. 6.1 Digital Signal Descriptions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  General Purpose Low Drop-Out Regulators (LDO1, LDO2, LDO3)
    6. 7.6  Low Noise Low Drop-Out Regulator (LDO4)
    7. 7.7  Internal Low Drop-Out Regulators (LDOVRTC, LDOVINT)
    8. 7.8  BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators
    9. 7.9  Reference Generator (BandGap)
    10. 7.10 Monitoring Functions
    11. 7.11 Clocks, Oscillators, and PLL
    12. 7.12 Thermal Monitoring and Shutdown
    13. 7.13 System Control Thresholds
    14. 7.14 Current Consumption
    15. 7.15 Backup Battery Charger
    16. 7.16 Digital Input Signal Parameters
    17. 7.17 Digital Output Signal Parameters
    18. 7.18 I/O Pullup and Pulldown Resistance
    19. 7.19 I2C Interface
    20. 7.20 Serial Peripheral Interface (SPI)
    21. 7.21 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  System Supply Voltage Monitor
      2. 8.3.2  Power Resources (Bucks and LDOs)
        1. 8.3.2.1 Buck Regulators
          1. 8.3.2.1.1  BUCK Regulator Overview
          2. 8.3.2.1.2  Multi-Phase Operation and Phase-Adding or Shedding
          3. 8.3.2.1.3  Transition Between PWM and PFM Modes
          4. 8.3.2.1.4  Multi-Phase BUCK Regulator Configurations
          5. 8.3.2.1.5  Spread-Spectrum Mode
          6. 8.3.2.1.6  Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support
          7. 8.3.2.1.7  BUCK Output Voltage Setting
          8. 8.3.2.1.8  BUCK Regulator Current Limit
          9. 8.3.2.1.9  SW_Bx Short-to-Ground Detection
          10. 8.3.2.1.10 Sync Clock Functionality
          11.        49
        2. 8.3.2.2 Low Dropout Regulators (LDOs)
          1. 8.3.2.2.1 LDOVINT
          2. 8.3.2.2.2 LDOVRTC
          3. 8.3.2.2.3 LDO1, LDO2, and LDO3
          4. 8.3.2.2.4 Low-Noise LDO (LDO4)
      3. 8.3.3  Output Voltage Monitor and PGOOD Generation
      4. 8.3.4  Thermal Monitoring
        1. 8.3.4.1 Thermal Warning Function
        2. 8.3.4.2 Thermal Shutdown
      5. 8.3.5  Backup Supply Power-Path
      6. 8.3.6  General-Purpose I/Os (GPIO Pins)
      7. 8.3.7  nINT, EN_DRV, and nRSTOUT Pins
      8. 8.3.8  Interrupts
      9. 8.3.9  RTC
        1. 8.3.9.1 General Description
        2. 8.3.9.2 Time Calendar Registers
          1. 8.3.9.2.1 TC Registers Read Access
          2. 8.3.9.2.2 TC Registers Write Access
        3. 8.3.9.3 RTC Alarm
        4. 8.3.9.4 RTC Interrupts
        5. 8.3.9.5 RTC 32-kHz Oscillator Drift Compensation
      10. 8.3.10 Watchdog (WDOG)
        1. 8.3.10.1 Watchdog Fail Counter and Status
        2. 8.3.10.2 Watchdog Start-Up and Configuration
        3. 8.3.10.3 MCU to Watchdog Synchronization
        4. 8.3.10.4 Watchdog Disable Function
        5. 8.3.10.5 Watchdog Sequence
        6. 8.3.10.6 Watchdog Trigger Mode
        7. 8.3.10.7 WatchDog Flow Chart and Timing Diagrams in Trigger Mode
        8.       79
        9. 8.3.10.8 Watchdog Question-Answer Mode
          1. 8.3.10.8.1 Watchdog Q&A Related Definitions
          2. 8.3.10.8.2 Question Generation
          3. 8.3.10.8.3 Answer Comparison
            1. 8.3.10.8.3.1 Sequence of the 2-bit Watchdog Answer Counter
            2. 8.3.10.8.3.2 Watchdog Sequence Events and Status Updates
            3. 8.3.10.8.3.3 Watchdog Q&A Sequence Scenarios
      11. 8.3.11 Error Signal Monitor (ESM)
        1. 8.3.11.1 ESM Error-Handling Procedure
          1. 8.3.11.1.1 Level Mode
          2.        90
          3. 8.3.11.1.2 PWM Mode
            1. 8.3.11.1.2.1 Good-Events and Bad-Events
            2. 8.3.11.1.2.2 ESM Error-Counter
            3. 8.3.11.1.2.3 ESM Start-Up in PWM Mode
            4. 8.3.11.1.2.4 ESM Flow Chart and Timing Diagrams in PWM Mode
            5.         96
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device State Machine
        1. 8.4.1.1 Fixed Device Power FSM
          1. 8.4.1.1.1 Register Resets and NVM Read at INIT State
        2. 8.4.1.2 Pre-Configurable Mission States
          1. 8.4.1.2.1 PFSM Commands
            1. 8.4.1.2.1.1  REG_WRITE_IMM Command
            2. 8.4.1.2.1.2  REG_WRITE_MASK_IMM Command
            3. 8.4.1.2.1.3  REG_WRITE_MASK_PAGE0_IMM Command
            4. 8.4.1.2.1.4  REG_WRITE_BIT_PAGE0_IMM Command
            5. 8.4.1.2.1.5  REG_WRITE_WIN_PAGE0_IMM Command
            6. 8.4.1.2.1.6  REG_WRITE_VOUT_IMM Command
            7. 8.4.1.2.1.7  REG_WRITE_VCTRL_IMM Command
            8. 8.4.1.2.1.8  REG_WRITE_MASK_SREG Command
            9. 8.4.1.2.1.9  SREG_READ_REG Command
            10. 8.4.1.2.1.10 SREG_WRITE_IMM Command
            11. 8.4.1.2.1.11 WAIT Command
            12. 8.4.1.2.1.12 DELAY_IMM Command
            13. 8.4.1.2.1.13 DELAY_SREG Command
            14. 8.4.1.2.1.14 TRIG_SET Command
            15. 8.4.1.2.1.15 TRIG_MASK Command
            16. 8.4.1.2.1.16 END Command
          2. 8.4.1.2.2 Configuration Memory Organization and Sequence Execution
          3. 8.4.1.2.3 Mission State Configuration
          4. 8.4.1.2.4 Pre-Configured Hardware Transitions
            1. 8.4.1.2.4.1 ON Requests
            2. 8.4.1.2.4.2 OFF Requests
            3. 8.4.1.2.4.3 NSLEEP1 and NSLEEP2 Functions
            4. 8.4.1.2.4.4 WKUP1 and WKUP2 Functions
            5. 8.4.1.2.4.5 LP_WKUP Pins for Waking Up from LP STANDBY
        3. 8.4.1.3 Error Handling Operations
          1. 8.4.1.3.1 Power Rail Output Error
          2. 8.4.1.3.2 Catastrophic Error
          3. 8.4.1.3.3 Watchdog (WDOG) Error
          4. 8.4.1.3.4 Warnings
        4. 8.4.1.4 Device Start-up Timing
        5. 8.4.1.5 Power Sequences
        6. 8.4.1.6 First Supply Detection
        7. 8.4.1.7 Register Power Domains and Reset Levels
      2. 8.4.2 Multi-PMIC Synchronization
        1. 8.4.2.1 SPMI Interface System Setup
        2. 8.4.2.2 Transmission Protocol and CRC
          1. 8.4.2.2.1 Operation with Transmission Errors
          2. 8.4.2.2.2 Transmitted Information
        3. 8.4.2.3 SPMI Target Device Communication to SPMI Controller Device
          1. 8.4.2.3.1 Incomplete Communication from SPMI Target Device to SPMI Controller Device
        4. 8.4.2.4 SPMI-BIST Overview
          1. 8.4.2.4.1 SPMI Bus during Boot BIST and RUNTIME BIST
          2. 8.4.2.4.2 Periodic Checking of the SPMI
          3. 8.4.2.4.3 SPMI Message Priorities
    5. 8.5 Control Interfaces
      1. 8.5.1 CRC Calculation for I2C and SPI Interface Protocols
      2. 8.5.2 I2C-Compatible Interface
        1. 8.5.2.1 Data Validity
        2. 8.5.2.2 Start and Stop Conditions
        3. 8.5.2.3 Transferring Data
        4. 8.5.2.4 Auto-Increment Feature
      3. 8.5.3 Serial Peripheral Interface (SPI)
    6. 8.6 Configurable Registers
      1. 8.6.1 Register Page Partitioning
      2. 8.6.2 CRC Protection for Configuration, Control, and Test Registers
      3. 8.6.3 CRC Protection for User Registers
      4. 8.6.4 Register Write Protection
        1. 8.6.4.1 Watchdog and ESM Configuration Registers
        2. 8.6.4.2 User Registers
    7. 8.7 Register Maps
      1. 8.7.1 TPS6593-Q1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Powering a Processor
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 VCCA
          2. 9.2.1.2.2 Internal LDOs
          3. 9.2.1.2.3 Crystal Oscillator
          4. 9.2.1.2.4 Buck Input Capacitors
          5. 9.2.1.2.5 Buck Output Capacitors
          6. 9.2.1.2.6 Buck Inductors
          7. 9.2.1.2.7 LDO Input Capacitors
          8. 9.2.1.2.8 LDO Output Capacitors
          9. 9.2.1.2.9 Digital Signal Connections
      2. 9.2.2 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
    2. 10.2 Device Nomenclature
    3. 10.3 Documentation Support
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 サポート・リソース
    6. 10.6 Trademarks
    7. 10.7 静電気放電に関する注意事項
    8. 10.8 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.8 Interrupts

The interrupt registers in the device are organized in hierarchical fashion. The interrupts are grouped into the following categories:

    BUCK ERROR These interrupts indicate over-voltage (OV), under-voltage (UV), short-circuit (SC) and over-current (ILIM) error conditions found on the BUCK regulators .
    LDO ERROR These interrupts indicate OV, UV, and SC error conditions found on the LDO regulators, as well as OV and UV error conditions found on the VCCA supply.
    VMON ERROR These interrupts indicate OV and UV error conditions found on the VCCA supply.
    SEVERE ERROR These errors indicate severe device error conditions, such as thermal shutdown, PFSM sequencing and execution error and VCCA over-voltage, that causes the device to trigger the PFSM to execute immediate shutdown of all digital outputs, external voltage rails and monitors, and proceed to the Safe Recovery State.
    MODERATE ERROR These interrupts provide warnings to the system to indicate multiple restart attempts from SAFE RECOVERY state exceeding the allowed recovery count, multiple warm-reset executions exceeding the allowed recovery count, detection of long press nPWRON button, SPMI communication error, register CRC error, BIST failure, read-back error on nRSTOUT or nINT pins, or junction temperature reaching orderly shutdown level. These warning causes the device to trigger the PFSM to execute orderly shutdown of all digital outputs, external voltage rails and monitors, and proceed to the SAFE RECOVERY state.(1)
    MISCELLANEOUS WARNING These interrupts provide information to the system to indicate detection of WDOG or ESM errors, die temperature crossing thermal warning threshold, device passing BIST test, or external sync clock availability.
    START-UP SOURCE These interrupts provide information to the system on the mechanism that caused the device to start up, which includes FSD, RTC alarm or timer interrupts, the activation of the ENABLE pin or the nPRWON pin button detection.
    GPIO DETECTION These interrupts indicate a High-Level or Rising-Edge detection, or indicate a Low-Level or Falling-Edge detection at the GPIO1 through GPIO11 pins.
    FSM ERROR INTERRUPT These interrupts indicate the detection of an error that causes the device mission state changes.

All interrupts are logically combined on a single output pin, nINT (active low). The host processor can read the INT_TOP register to find the interrupt registers to find out the source of the interrupt, and write '1' to the corresponding interrupt register bit to clear the interrupt. This mechanism ensures when a new interrupt occurs while the nINT pin is still active, all of the corresponding interrupt register bits retain the interrupt source information until it is cleared by the host.

Hierarchical Structure of Interrupt Registers shows the hierarchical structure of the interrupt registers according to the categories described above. The purpose of this register structure is to reduce the number of interrupt register read cycles the host has to perform in order to identify the source of the interrupt. Summary of Interrupt Signals summarizes the trigger and the clearing mechanism for all of the interrupt signals. This table also shows which interrupt sources can be masked by setting the corresponding mask register to '1'. When an interrupt is masked, the interrupt bit is not updated when the associated event occurs, the nINT line is not affected, and the event is not recorded. If an interrupt is masked after the event occurred, the interrupt register bit reflects the event until the bit is cleared. While the event is masked, the interrupt register bit is not over-written when a new event occurs.

GUID-1AD446B7-F5DD-424D-8136-287266ABF350-low.svg Figure 8-12 Hierarchical Structure of Interrupt Registers
Table 8-6 Summary of Interrupt Signals
EVENT TRIGGER FOR FSM RESULT (1) RECOVERY INTERRUPT BIT MASK FOR INTERRUPT LIVE STATUS BIT INTERRUPT CLEAR
BUCK regulator forward current limit triggered EN_ILIM_FSM_CTRL=1:
According to BUCKn_GRP_SEL and x_RAIL_TRIG bits
EN_ILIM_FSM_CTRL=0:
N/A		 EN_ILIM_FSM_CTRL=1:
Transition according to FSM trigger and interrupt
EN_ILIM_FSM_CTRL=0:
Interrupt only		 Depends on PFSM configuration, see PFSM transition diagram BUCKn_ILIM_INT = 1 BUCKn_ILIM_MASK BUCKn_ILIM_STAT Write 1 to BUCKn_ILIM_INT bit
Interrupt is not cleared if current limit violation is active
LDO regulator current limit triggered EN_ILIM_FSM_CTRL=1:
According to LDOn_GRP_SEL and x_RAIL_TRIG bits
EN_ILIM_FSM_CTRL=0:
N/A		 EN_ILIM_FSM_CTRL=1:
Transition according to FSM trigger and interrupt
EN_ILIM_FSM_CTRL=0:
Interrupt only		 Depends on PFSM configuration, see PFSM transition diagram LDOn_ILIM_INT = 1 LDOn_ILIM_MASK LDOn_ILIM_STAT Write 1 to LDOn_ILIM_INT bit
Interrupt is not cleared if current limit violation is active
BUCK output or switch short circuit detected According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Regulator disable and transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_SC_INT = 1 N/A N/A Write 1 to BUCKn_SC_INT bit
Interrupt is not cleared if the BUCKn is enabled and the BUCKn output voltage is below the short-circuit threshold after elapse of expected ramp-up time interval
LDO output short circuit detected According to LDOn_GRP_SEL and x_RAIL_TRIG bits Regulator disable and transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_SC_INT = 1 N/A N/A Write 1 to LDOn_SC_INT bit
Interrupt is not cleared if the LDOn is enabled and the LDOn output voltage is below the short-circuit threshold after elapse of expected ramp-up time interval
BUCK regulator overvoltage According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_OV_INT = 1 BUCKn_OV_MASK BUCKn_OV_STAT Write 1 to BUCKn_OV_INT bit
Interrupt is not cleared if the associated fault condition is still present
BUCK regulator undervoltage According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_UV_INT = 1 BUCKn_UV_MASK BUCKn_UV_STAT Write 1 to BUCKn_UV_INT bit
Interrupt is not cleared if the associated fault condition is still present
LDO regulator overvoltage According to LDOn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_OV_INT = 1 LDOn_OV_MASK LDOn_OV_STAT Write 1 to LDOn_OV_INT bit
Interrupt is not cleared if the associated fault condition is still present
LDO regulator undervoltage According to LDOn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_UV_INT = 1 LDOn_UV_MASK LDOn_UV_STAT Write 1 to LDOn_UV_INT bit
Interrupt is not cleared if the associated fault condition is still present
VCCA input overvoltage monitoring According to VCCA_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram VCCA_OV_INT = 1 VCCA_OV_MASK VCCA_OV_STAT Write 1 to VCCA_OV_INT bit
Interrupt is not cleared if the associated fault condition is still present
VCCA input undervoltage monitoring According to VCCA_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram VCCA_UV_INT = 1 VCCA_UV_MASK VCCA_UV_STAT Write 1 to VCCA_UV_INT bit
Interrupt is not cleared if the associated fault condition is still present
Thermal warning N/A Interrupt only Not valid TWARN_INT = 1 TWARN_MASK TWARN_STAT Write 1 to TWARN_INT bit
Interrupt is not cleared if temperature is above thermal warning level
Thermal shutdown, orderly sequenced ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low in a sequence and interrupt(1) Automatic start-up to STARTUP_DEST[1:0] state after temperature is below TWARN level TSD_ORD_INT = 1 N/A TSD_ORD_STAT Write 1 to TSD_ORD_INT bit
This interrupt bit can only be read by the MCU after the device has recovered from a previously occurred over-temperature event.
Thermal shutdown, immediate IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deavtivated with pull-down resistors and Output GPIOx set to low immediately and interrupt(1) Automatic start-up to STARTUP_DEST[1:0] state after temperature is below TWARN level TSD_IMM_INT = 1 N/A TSD_IMM_STAT Write 1 to TSD_IMM_INT bit
This interrupt bit can only be read by the MCU after the device has recovered from a previously occurred over-temperature event.
BIST error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt(1) Automatic start-up to STARTUP_DEST[1:0] state BIST_FAIL_INT = 1 BIST_FAIL_MASK N/A Write 1 to BIST_FAIL_INT bit
Register CRC error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt(1) Automatic start-up to STARTUP_DEST[1:0] state REG_CRC_ERR_INT = 1 REG_CRC_ERR_MASK N/A Write 1 to REG_CRC_ERR_INT bit
SPMI communication error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt(1) Automatic start-up to STARTUP_DEST[1:0] state SPMI_ERR_INT = 1 SPMI_ERR_MASK N/A Write 1 to SPMI_ERR_INT bit
SPI frame error N/A Interrupt only Not valid COMM_FRM_ERR_INT = 1(4) COMM_FRM_ERR_MASK N/A Write 1 to COMM_FRM_ERR_INT bit
I2C1 or SPI CRC error N/A Interrupt only Not valid COMM_CRC_ERR_INT = 1 COMM_CRC_ERR_MASK N/A Write 1 to COMM_CRC_ERR_INT bit
I2C1 or SPI address error(5) N/A Interrupt only Not valid COMM_ADR_ERR_INT = 1 COMM_ADR_ERR_MASK N/A Write 1 to COMM_ADR_ERR_INT bit
I2C2 CRC error N/A Interrupt only Not valid I2C2_CRC_ERR_INT = 1 I2C2_CRC_ERR_MASK N/A Write 1 to I2C2_CRC_ERR_INT bit
I2C2 address error(5) N/A Interrupt only Not valid I2C2_ADR_ERR_INT = 1 I2C2_ADR_ERR_MASK N/A Write 1 to I2C2_ADR_ERR_INT bit
PFSM error IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately and interrupt(1) Automatic start-up to STARTUP_DEST[1:0] state. If previous PFSM_ERR_INT is pending, VCCA power cycle needed for recovery. PFSM_ERR_INT = 1 N/A Write 1 to PFSM_ERR_INT bit
EN_DRV pin read-back error (monitoring high and low states) N/A Interrupt only Not valid EN_DRV_READBACK_INT = 1 EN_DRV_READBACK_MASK EN_DRV_READBACK_STAT Write 1 to EN_DRV_READBACK_INT bit
Interrupt is not cleared if the associated fault condition is still present
NINT pin read-back error (monitoring low state) ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt(1) Automatic start-up to STARTUP_DEST[1:0] state NINT_READBACK_INT = 1 NINT_READBACK_MASK NINT_READBACK_STAT Write 1 to NINT_READBACK_INT bit
Interrupt is not cleared if the associated fault condition is still present
NRSTOUT pin read-back error (monitoring low state) ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt(1) Automatic start-up to STARTUP_DEST[1:0] state NRSTOUT_READBACK_INT = 1 NRSTOUT_READBACK_MASK NRSTOUT_READBACK_STAT Write 1 to NRSTOUT_READBACK_INT bit
Interrupt is not cleared if the associated fault condition is still present
NRSTOUT_SOC pin read-back error (monitoring low state) N/A Interrupt only Not valid NRSTOUT_SOC_READBACK_INT = 1 NRSTOUT_SOC_READBACK_MASK NRSTOUT_SOC_READBACK_STAT Write 1 to NRSTOUT_SOC_READBACK_INT bit
Interrupt is not cleared if the associated fault condition is still present
Fault detected by SOC ESM (level mode: low level detected, PWM mode: PWM signal timing violation) N/A Interrupt only Not valid ESM_SOC_PIN_INT = 1 ESM_SOC_PIN_MASK N/A Write 1 to ESM_SOC_PIN_INT bit
Interrupt is not cleared if the associated fault condition is still present
Fault detected by SOC ESM (level mode: low level longer than DELAY1 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1time) N/A Interrupt and EN_DRV = 0 (configurable) Not valid ESM_SOC_FAIL_INT = 1 ESM_SOC_FAIL_MASK N/A Write 1 to ESM_SOC_FAIL_INT bit
Interrupt is not cleared if the associated fault condition is still present
Fault detected by SOC ESM (level mode: low level longer than DELAY1+DELAY2 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1+DELAY2 time) ESM_SOC_RST Interrupt, and NRSTOUT_SOC toggle(1) Automatically returns to the current operating state after the completion of SoC warm reset ESM_SOC_RST_INT = 1 ESM_SOC_RST_MASK N/A Write 1 to ESM_SOC_RST_INT bit
This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold
Fault detected by MCU ESM (level mode: low level detected, PWM mode: PWM signal timing violation N/A Interrupt only Not valid ESM_MCU_PIN_INT = 1 ESM_MCU_PIN_MASK N/A Write 1 to ESM_MCU_PIN_INT bit
Interrupt is not cleared if the associated fault condition is still present
Fault detected by MCU ESM (level mode: low level longer than DELAY1 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1 time) N/A Interrupt and EN_DRV = 0 (configurable) Not valid ESM_MCU_FAIL_INT = 1 ESM_MCU_FAIL_MASK N/A Write 1 to ESM_MCU_FAIL_INT bit
Interrupt is not cleared if the associated fault condition is still present
Fault detected by MCU ESM (level mode: low level longer than DELAY1+DELAY2 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1+DELAY2 time) ESM_MCU_RST Interrupt and Warm Reset (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)(1) Automatically returns to the current operating state after the completion of warm reset ESM_MCU_RST_INT = 1 ESM_MCU_RST_MASK N/A Write 1 to ESM_MCU_RST_INT bit
This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold
External clock is expected, but it is not available or the frequency is not in the valid range N/A Interrupt only Not valid EXT_CLK_INT = 1(2) EXT_CLK_MASK EXT_CLK_STAT Write 1 to EXT_CLK_INT bit
Interrupt is not cleared if the associated fault condition is still present
BIST completed successfully N/A Interrupt only Not valid BIST_PASS_INT = 1 BIST_PASS_MASK N/A Write 1 to BIST_PASS_INT bit
Watchdog fail counter above fail threshold N/A Interrupt and EN_DRV = 0 Clear interrupt and WD_FAIL_CNT < WD_FAIL_TH WD_FAIL_INT = 1 N/A N/A Write 1 to WD_FAIL_INT bit
Watchdog fail counter above reset threshold WD_RST (if WD_RST_EN = 1) Interrupt and Warm Reset if WD_RST_EN = 1 (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)(1) Automatically returns to the current operating state after the completion of warm reset WD_RST_INT = 1 N/A N/A Write 1 to WD_RST_INT bit
This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold
Watchdog long window timeout WD_RST Interrupt and Warm Reset (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)(1) Automatically returns to the current operating state after the completion of warm reset WD_LONGWIN_TIMEOUT_INT = 1 N/A N/A Write 1 to WD_LONGWIN_TIMEOUT_INT bit
This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold
RTC alarm wake-up TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt(1) Not valid ALARM = 1 IT_ALARM = 0 N/A Write 1 to ALARM bit
RTC timer wake-up TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt(1) Not valid TIMER = 1 IT_TIMER = 0 N/A Write 1 to TIMER bit
Low state in NPWRON pin TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt(1) Not valid NPWRON_START_INT = 1 NPWRON_START_MASK NPWRON_IN Write 1 to NPWRON_START_INT bit
Long low state in NPWRON pin ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence and interrupt(1) Valid power-on request NPWRON_LONG_INT = 1 NPWRON_LONG_MASK NPWRON_IN Write 1 to NPWRON_LONG_INT bit
Low state in ENABLE pin TRIGGER_FORCE_STANDBY/TRIGGER_FORCE_LP_STANDBY Transition to STANDBY or LP_STANDBY depending on the LP_STANDBY_SEL bit setting(1) ENABLE pin rise N/A N/A N/A N/A
ENABLE pin rise TRIGGER_SU_x (1) Not valid ENABLE_INT = 1 ENABLE_MASK ENABLE_STAT Write 1 to ENABLE_INT bit
Fault causing orderly shutdown ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence and interrupt(1) Automatic start-up to STARTUP_DEST[1:0] state ORD_SHUTDOWN_INT ORD_SHUTDOWN_MASK N/A Write 1 to ORD_SHUTDOWN_INT
Fault causing immediate shutdown IMMEDIATE_SHUTDOWN All regulators deactivated (depending on NVM configuration with or without pull-down resistors) and Output GPIOx set to low immediately and interrupt(1) Automatic start-up to STARTUP_DEST[1:0] state IMM_SHUTDOWN_INT IMM_SHUTDOWN_MASK N/A Write 1 to IMM_SHUTDOWN_INT
Power supply error for MCU MCU_POWER_ERROR Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram MCU_PWR_ERR_INT MCU_PWR_ERR_MASK N/A Write 1 to MCU_PWR_ERR_INT
Power supply error for SOC SOC_POWER_ERROR Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram SOC_PWR_ERR_INT SOC_PWR_ERR_MASK N/A Write 1 to SOC_PWR_ERR_INT
VCCA over-voltage (VCCAOVP) IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately and interrupt(1) Automatic start-up to STARTUP_DEST[1:0] state after VCCA voltage is below VCCAOVP VCCA_OVP_INT = 1 N/A VCCA_OVP_STAT Write 1 to VCCA_OVP _INT bit
This bit can only be read by the MCU if VCCA < VCCAOVP level. As long as VCCA ⩾ VCCAOVP level, device stays in SAFE RECOVEY state, and hence this interrupt cannot be not cleared.
GPIO interrupt According to GPIOx_FSM_MASK and GPIOx_FSM_MASK_POL bits Transition according to FSM trigger and interrupt Not valid GPIOx_INT = 1 GPIOx_RISE_MASK
GPIOx_FALL_MASK		 GPIOx_IN Write 1 to GPIOx_INT bit
WKUP1 and LP_WKUP1 signals WKUP1 Transition to ACTIVE state and interrupt(1) Not valid N/A GPIOx_RISE_MASK
GPIOx_FALL_MASK		 GPIOx_IN Write 1 to GPIOx_INT bit
WKUP2 and LP_WKUP2 signals WKUP2 Transition to MCU ONLY state and interrupt(1) Not valid N/A GPIOx_RISE_MASK
GPIOx_FALL_MASK		 GPIOx_IN Write 1 to GPIOx_INT bit
NSLEEP1 signal, NSLEEP1B bit According to NSLEEP1 and NSLEEP2 State transition based on NSLEEP1 and NSLEEP2 Not valid N/A NSLEEP1_MASK GPIOx_IN N/A
NSLEEP2 signal, NSLEEP2B bit According to NSLEEP1 and NSLEEP2 State transition based on NSLEEP1 and NSLEEP2 Not valid N/A NSLEEP2_MASK GPIOx_IN N/A
LDOVINT over- or undervoltage Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately(1) Valid LDOVINT voltage N/A N/A N/A N/A
Main clock outside valid frequency Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately(1) VCCA power cycle N/A N/A N/A N/A
Recovery counter limit exceeded(4) ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence(1) VCCA power cycle N/A N/A N/A N/A
VCCA supply falling below VCCAUVLO Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately(1) VCCA voltage rising N/A N/A N/A N/A
First supply detection, VCCA supply rising above VCCAUVLO TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt(1) Not valid FSD_INT = 1 FSD_MASK N/A Write 1 to FSD_INT bit
(1) The results shown in this column are selected to meet functional safety assumptions and device specifications. The actual results can be configured differently in NVM memory. TI recommends reviewing of the system and device functional safety goal and documentation before deviating from these recommendations.
(2) Interrupt is generated during clock detector operation and in case clock is not available when clock detector is enabled.
(4) This event does not occur if RECOV_CNT_THR = 0, even though RECOV_CNT continues to accumulate and increase, and eventually saturates when it reaches the maximum count of 15.
(4) Due to a digital logic errata in the device, a write or read SPI command which coincide with the rising edge of the CS signal may not cause the COMM_FRM_ERR_INT interrupt.
(5) I2C1, I2C2, or SPI address error only occur in safety applications if the interface CRC feature is enabled, when both I2C1_SPI_CRC_EN and I2C2_CRC_EN are set to '1'.
1. The SEVERE ERROR and the MODERATE ERROR are handled in NVM memory but TI requires that the NVM pre-configurable finite state machine (PFSM) settings always follow this described error handling to meet device specifications.