JAJSLW7B December   2020  – September 2023 TPS6593-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
    1.     5
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Pin Configuration and Functions
    1. 6.1 Digital Signal Descriptions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  General Purpose Low Drop-Out Regulators (LDO1, LDO2, LDO3)
    6. 7.6  Low Noise Low Drop-Out Regulator (LDO4)
    7. 7.7  Internal Low Drop-Out Regulators (LDOVRTC, LDOVINT)
    8. 7.8  BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators
    9. 7.9  Reference Generator (BandGap)
    10. 7.10 Monitoring Functions
    11. 7.11 Clocks, Oscillators, and PLL
    12. 7.12 Thermal Monitoring and Shutdown
    13. 7.13 System Control Thresholds
    14. 7.14 Current Consumption
    15. 7.15 Backup Battery Charger
    16. 7.16 Digital Input Signal Parameters
    17. 7.17 Digital Output Signal Parameters
    18. 7.18 I/O Pullup and Pulldown Resistance
    19. 7.19 I2C Interface
    20. 7.20 Serial Peripheral Interface (SPI)
    21. 7.21 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  System Supply Voltage Monitor
      2. 8.3.2  Power Resources (Bucks and LDOs)
        1. 8.3.2.1 Buck Regulators
          1. 8.3.2.1.1  BUCK Regulator Overview
          2. 8.3.2.1.2  Multi-Phase Operation and Phase-Adding or Shedding
          3. 8.3.2.1.3  Transition Between PWM and PFM Modes
          4. 8.3.2.1.4  Multi-Phase BUCK Regulator Configurations
          5. 8.3.2.1.5  Spread-Spectrum Mode
          6. 8.3.2.1.6  Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support
          7. 8.3.2.1.7  BUCK Output Voltage Setting
          8. 8.3.2.1.8  BUCK Regulator Current Limit
          9. 8.3.2.1.9  SW_Bx Short-to-Ground Detection
          10. 8.3.2.1.10 Sync Clock Functionality
          11.        49
        2. 8.3.2.2 Low Dropout Regulators (LDOs)
          1. 8.3.2.2.1 LDOVINT
          2. 8.3.2.2.2 LDOVRTC
          3. 8.3.2.2.3 LDO1, LDO2, and LDO3
          4. 8.3.2.2.4 Low-Noise LDO (LDO4)
      3. 8.3.3  Output Voltage Monitor and PGOOD Generation
      4. 8.3.4  Thermal Monitoring
        1. 8.3.4.1 Thermal Warning Function
        2. 8.3.4.2 Thermal Shutdown
      5. 8.3.5  Backup Supply Power-Path
      6. 8.3.6  General-Purpose I/Os (GPIO Pins)
      7. 8.3.7  nINT, EN_DRV, and nRSTOUT Pins
      8. 8.3.8  Interrupts
      9. 8.3.9  RTC
        1. 8.3.9.1 General Description
        2. 8.3.9.2 Time Calendar Registers
          1. 8.3.9.2.1 TC Registers Read Access
          2. 8.3.9.2.2 TC Registers Write Access
        3. 8.3.9.3 RTC Alarm
        4. 8.3.9.4 RTC Interrupts
        5. 8.3.9.5 RTC 32-kHz Oscillator Drift Compensation
      10. 8.3.10 Watchdog (WDOG)
        1. 8.3.10.1 Watchdog Fail Counter and Status
        2. 8.3.10.2 Watchdog Start-Up and Configuration
        3. 8.3.10.3 MCU to Watchdog Synchronization
        4. 8.3.10.4 Watchdog Disable Function
        5. 8.3.10.5 Watchdog Sequence
        6. 8.3.10.6 Watchdog Trigger Mode
        7. 8.3.10.7 WatchDog Flow Chart and Timing Diagrams in Trigger Mode
        8.       79
        9. 8.3.10.8 Watchdog Question-Answer Mode
          1. 8.3.10.8.1 Watchdog Q&A Related Definitions
          2. 8.3.10.8.2 Question Generation
          3. 8.3.10.8.3 Answer Comparison
            1. 8.3.10.8.3.1 Sequence of the 2-bit Watchdog Answer Counter
            2. 8.3.10.8.3.2 Watchdog Sequence Events and Status Updates
            3. 8.3.10.8.3.3 Watchdog Q&A Sequence Scenarios
      11. 8.3.11 Error Signal Monitor (ESM)
        1. 8.3.11.1 ESM Error-Handling Procedure
          1. 8.3.11.1.1 Level Mode
          2.        90
          3. 8.3.11.1.2 PWM Mode
            1. 8.3.11.1.2.1 Good-Events and Bad-Events
            2. 8.3.11.1.2.2 ESM Error-Counter
            3. 8.3.11.1.2.3 ESM Start-Up in PWM Mode
            4. 8.3.11.1.2.4 ESM Flow Chart and Timing Diagrams in PWM Mode
            5.         96
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device State Machine
        1. 8.4.1.1 Fixed Device Power FSM
          1. 8.4.1.1.1 Register Resets and NVM Read at INIT State
        2. 8.4.1.2 Pre-Configurable Mission States
          1. 8.4.1.2.1 PFSM Commands
            1. 8.4.1.2.1.1  REG_WRITE_IMM Command
            2. 8.4.1.2.1.2  REG_WRITE_MASK_IMM Command
            3. 8.4.1.2.1.3  REG_WRITE_MASK_PAGE0_IMM Command
            4. 8.4.1.2.1.4  REG_WRITE_BIT_PAGE0_IMM Command
            5. 8.4.1.2.1.5  REG_WRITE_WIN_PAGE0_IMM Command
            6. 8.4.1.2.1.6  REG_WRITE_VOUT_IMM Command
            7. 8.4.1.2.1.7  REG_WRITE_VCTRL_IMM Command
            8. 8.4.1.2.1.8  REG_WRITE_MASK_SREG Command
            9. 8.4.1.2.1.9  SREG_READ_REG Command
            10. 8.4.1.2.1.10 SREG_WRITE_IMM Command
            11. 8.4.1.2.1.11 WAIT Command
            12. 8.4.1.2.1.12 DELAY_IMM Command
            13. 8.4.1.2.1.13 DELAY_SREG Command
            14. 8.4.1.2.1.14 TRIG_SET Command
            15. 8.4.1.2.1.15 TRIG_MASK Command
            16. 8.4.1.2.1.16 END Command
          2. 8.4.1.2.2 Configuration Memory Organization and Sequence Execution
          3. 8.4.1.2.3 Mission State Configuration
          4. 8.4.1.2.4 Pre-Configured Hardware Transitions
            1. 8.4.1.2.4.1 ON Requests
            2. 8.4.1.2.4.2 OFF Requests
            3. 8.4.1.2.4.3 NSLEEP1 and NSLEEP2 Functions
            4. 8.4.1.2.4.4 WKUP1 and WKUP2 Functions
            5. 8.4.1.2.4.5 LP_WKUP Pins for Waking Up from LP STANDBY
        3. 8.4.1.3 Error Handling Operations
          1. 8.4.1.3.1 Power Rail Output Error
          2. 8.4.1.3.2 Catastrophic Error
          3. 8.4.1.3.3 Watchdog (WDOG) Error
          4. 8.4.1.3.4 Warnings
        4. 8.4.1.4 Device Start-up Timing
        5. 8.4.1.5 Power Sequences
        6. 8.4.1.6 First Supply Detection
        7. 8.4.1.7 Register Power Domains and Reset Levels
      2. 8.4.2 Multi-PMIC Synchronization
        1. 8.4.2.1 SPMI Interface System Setup
        2. 8.4.2.2 Transmission Protocol and CRC
          1. 8.4.2.2.1 Operation with Transmission Errors
          2. 8.4.2.2.2 Transmitted Information
        3. 8.4.2.3 SPMI Target Device Communication to SPMI Controller Device
          1. 8.4.2.3.1 Incomplete Communication from SPMI Target Device to SPMI Controller Device
        4. 8.4.2.4 SPMI-BIST Overview
          1. 8.4.2.4.1 SPMI Bus during Boot BIST and RUNTIME BIST
          2. 8.4.2.4.2 Periodic Checking of the SPMI
          3. 8.4.2.4.3 SPMI Message Priorities
    5. 8.5 Control Interfaces
      1. 8.5.1 CRC Calculation for I2C and SPI Interface Protocols
      2. 8.5.2 I2C-Compatible Interface
        1. 8.5.2.1 Data Validity
        2. 8.5.2.2 Start and Stop Conditions
        3. 8.5.2.3 Transferring Data
        4. 8.5.2.4 Auto-Increment Feature
      3. 8.5.3 Serial Peripheral Interface (SPI)
    6. 8.6 Configurable Registers
      1. 8.6.1 Register Page Partitioning
      2. 8.6.2 CRC Protection for Configuration, Control, and Test Registers
      3. 8.6.3 CRC Protection for User Registers
      4. 8.6.4 Register Write Protection
        1. 8.6.4.1 Watchdog and ESM Configuration Registers
        2. 8.6.4.2 User Registers
    7. 8.7 Register Maps
      1. 8.7.1 TPS6593-Q1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Powering a Processor
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 VCCA
          2. 9.2.1.2.2 Internal LDOs
          3. 9.2.1.2.3 Crystal Oscillator
          4. 9.2.1.2.4 Buck Input Capacitors
          5. 9.2.1.2.5 Buck Output Capacitors
          6. 9.2.1.2.6 Buck Inductors
          7. 9.2.1.2.7 LDO Input Capacitors
          8. 9.2.1.2.8 LDO Output Capacitors
          9. 9.2.1.2.9 Digital Signal Connections
      2. 9.2.2 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
    2. 10.2 Device Nomenclature
    3. 10.3 Documentation Support
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 サポート・リソース
    6. 10.6 Trademarks
    7. 10.7 静電気放電に関する注意事項
    8. 10.8 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
9.2.1.2.5 Buck Output Capacitors

The buck converters have seven potential NVM configurations which can impact the output capacitor selection. Refer the part number specific user's guide to identify which configuration applies to each buck regulator. The actual minimal capacitance requirements to achieve a specific accuracy or ripple target varies depending on the input voltage, output voltage, and load transient characteristics; some guidance, however, is provided below. The local output capacitors must be placed as close to the inductor as possible to minimize electromagnetic emissions. Every buck output requires a local output capacitor to form the capacitive part of the LC output filter. It is recommended to place all large capacitors near the inductor. See Section 9.4 for more information about component placement. Use ceramic local output capacitors, X7R or X7T types; do not use Y5V or F. DC bias voltage characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR and ESL to perform these functions. Minimum effective output capacitance (including the DC voltage roll-off, tolerances, aging and temperature effects) is defined in Electrical Characteristics table for different buck configurations. The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for selection process is at the switching frequency of the part.

To achieve better ripple and transient performance, additional high pass filter caps are recommended to compensate for the parasitic impedance due to board routing and provide faster transient response to a load step. These caps are placed close to the point of load and are also the input capacitors of the load. These capacitors are referred to as POL caps later in this document. POL capacitor usage varies based on the application and generally follows the SoC or FPGA input capacitor requirements. Low ESL 3-terminal caps are recommended, as their high performance can help reduce the total number of capacitors required which simplifies board layout design and saves board area. They also help to reduce the total cost of the solution.

Note that the output capacitor may be the limiting factor in the output voltage ramp and the maximum total output capacitance listed in electrical characteristics must not be exceeded. At shutdown the output capacitors are discharged to 0.15-V level using forced-PWM operation. This discharge of the output capacitors can cause an increase of the input voltage if the load current is small and the output capacitor is large. Below 0.15-V level the output capacitor is discharged by the internal discharge resistor and with large capacitor more time is required to settle VOUT down as a consequence of the increased time constant.

Figure 9-3 is an example power distribution network (PDN) of local and POL caps at the output of a buck for optimal ripple and transient performance. Table 9-6 lists the local and POL capacitors used to validate the buck transient and ripple performance specified in the parametric table for each of the seven configurations. Table 9-7 lists the actual capacitor part numbers used for the different use case tests, neglecting capacitors below 10-µF. It is recommended to simulate and validate that the capacitor network chosen for a particular design meets the desired requirements as these are provided as guidelines.

GUID-20210624-CA0I-9LLB-CT18-QPZCTWJX6F5T-low.svgFigure 9-3 Example Power Distribution Network (PDN) of Local and POL Capacitors
Table 9-6 Local and POL Capacitors used for Buck Use Case Validation
Configuration COUT L CL / phase RPCB per phase1 LPCB per phase2 CPOL1 (total) CPOL2 (total)
4.4 MHz VOUT Less than 1.9 V, Low Load Step, Single Phase with low COUT

Low

470 nH

22 uF x 1

 8 mΩ 2.5 nH

1 uF x 1
4.4 MHz VOUT Less than 1.9 V, Multiphase Low 220 nH 47 µF × 2 8 mΩ 2.5 nH 10 µF × 4
High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2
4.4 MHz VOUT Less than 1.9 V, Single Phase with high COUT Low 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4
High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2
4.4 MHz VOUT Less than 1.9 V, Single Phase with low COUT Low 220 nH 22 µF × 1 8 mΩ 2.5 nH 10 µF × 2
High 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4
4.4 MHz VOUT Greater than 1.7 V, Single Phase Only (VIN Greater than 4.5 V) Low 470 nH 47 µF × 1 27 mΩ 6 nH 10 µF × 4
High 470 nH 47 µF × 2 27 mΩ 6 nH 10 µF × 2
2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only Low 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4
High 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 680 µF × 1
2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase Low 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4
High 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 680 µF × 1
2.2 MHz Full VOUT and Full VIN Range, Single Phase Only Low 1000 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 2
High 1000 nH 100 µF × 4 4.1 mΩ 1.3 nH 10 µF × 2
DDR VTT Termination, 2.2 MHz Single Phase Only - 470 nH 22 µF × 1 27 mΩ 6 nH 10 µF × 1 + 22 µF x 1
  1. RPCB is the PCB wiring resistance between local and POL capacitors including both positive and negative paths. For multi-phase outputs the total resistance is divided by the number of phases.
  2. LPCB is the PCB wiring inductance between local and POL capacitors including both positive and negative paths. For multi-phase outputs the total inductance is divided by the number of phases.

Power input and output wiring parasitic resistance and inductance must be minimized.

Table 9-7 Recommended Buck Converter Output Capacitor Components
MANUFACTURER PART NUMBER VALUE EIA Size Code SIZE (mm) Used for Validation
Murata NFM15HC105D0G(1) 1 µF, 4 V, X7S 0402 1.0 × 0.5 Yes
TDK YFF18AC0J105M(1) 1 µF, 6.3 V 0603 1.6 × 0.8 -
Murata NFM18HC106D0G(1) 10 µF, 4 V, X7S 0603 1.6 × 0.8 Yes
TDK YFF18AC0G475M(1) 4.7 µF, 6.3 V 0603 1.6 × 0.8 -
Murata GCM31CR71A226KE02 22 µF, 10 V, X7R 1206 3.2 × 1.6 Yes
Murata GCM21BD7CGA5L1X7R0J226MT0J226M 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 -
TDK CGA5L1X7R0J226MT 22 µF, 6.3 V, X7R 1206 3.2 × 1.6 -
TDK CGA4J1X7T0J226MT 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 -
Murata GCM32ER70J476ME19 47 µF, 6.3 V, X7R 1210 3.2 × 2.5 Yes
Murata GCM31CD70G476M 47 µF, 4 V, X7T 1206 3.2 × 1.6 -
TDK CGA6P1X7S1A476MT 47 µF, 10 V, X7S 1210 3.2 × 2.5 -
TDK CGA5L1X7T0G476MT 47 µF, 4 V, X7T 1206 3.2 × 1.6 -
Murata GCM32ED70G107MEC4 100 µF, 4 V, X7S 1210 3.2 × 2.5 Yes
TDK CGA6P1X7T0G107MT 100 µF, 4 V, X7T 1210 3.2 × 2.5 -
Kemet T510X687K006ATA023(2) 680 µF, 6.3 V 2917 7.4 × 5.0 Yes

Murata

GCM188D70E226ME36D

22uF, 2.5 V, X7T

0603

 1.6 × 0.8

Yes
(1) Low ESL 3-terminal cap.
(2) Dependent on availability; may switch to 470 µF.