JAJSLW7B December 2020 – September 2023 TPS6593-Q1
PRODUCTION DATA
A power sequence is an automatic preconfigured sequence the TPS6593-Q1 device applies to its resources, which include the states of the BUCKs, LDOs, 32-kHz clock and the GPIO output signals. For a detailed description of the GPIOs signals, please refer to General-Purpose I/Os (GPIO Pins).
Figure 8-42 shows an example of a power up transition followed by a power down transition. The power up sequence is triggered through a valid on request, and the power down sequence is trigger by a valid off request. The resources controlled (for this example) are: BUCK3, LDO1, BUCK2, LDO2, GPIO1, LDO4, and LDO3. The time between each resource enable and disable (TinstX) is also part of the preconfigured sequence definition.
A resource not assigned to any power sequence remains in off mode during the power-up sequence. The attached MCU or SoC can enable and configure this resource independently when the power-up sequence completes. Also the EN_DRV remains low during the power-up sequence. The attached MCU or SoC can release the EN_DRV pin by setting the ENABLE_DRV bit (requires running watchdog, ESM started and no pending interrupt bits).
As the power sequences of the TPS6593-Q1 device are defined according to the processor requirements, the total time for the completion of the power sequence varies across various system definitions.