The Fixed Device Power portion of the
FSM engine manages the power up of the device before the power rails are fully
enabled and ready to power external loadings, and the power down of the device when
in the event of insufficient power supply or device or system error conditions.
While the device is in one of the Hardware Device Powers states, the
ENABLE_DRV bit remains low.
The definitions and transition
triggers of the Device Power States are fixed and cannot be reconfigured.
Following are the definitions of the
Device Power states:
NO SUPPLY
The device is not powered by a valid energy source on the system power
rail. The device is completely powered off.
BACKUP (RTC backup battery)
The device is not powered by a valid supply on the system power rail
(VCCA < VCCA_UVLO); a backup power source, however, is present and is
within the operating range of the LDOVRTC. The RTC clock counter remains
active in this state if it has been previously activated by appropriate
register enable bit. The calendar function of the RTC block is
activated, but not accessible in this state. Customer has the option to
enable the shelf mode by
disconnecting the VCCA supply completely, even while the backup battery
is connected to the VBACKUP pin. The shelf mode forces the device to skip the BACKUP state
and enters the NO SUPPLY state under VCCA_UVLO condition to reduce
current draining from the backup battery.
LP_STANDBY
The device can enter this state from a mission state after receiving a
valid OFF request
or an I2C trigger,
and the LP_STANDBY_SEL= 1. When the device is in this state, the RTC clock counter and the RTC Alarm or
Timer Wake-up functions are active if they have been previously
activated by appropriate register enable bit. Low Power
Wake-up input monitor in the LDOVRTC domain (LP_WKUP secondary
function through GPIO3 or GPIO4) and the on request monitors are also enabled in this state. When
a logic level transition from high-to-low or low-to-high with a
minimum pulse length of tLP_WKUP is detected on the
assigned LP_WKUP pin, or if the device detects a valid
on-request or a wake-up signal
from the RTC block, the device proceeds to power
up the device and reach the default mission state. More details
regarding the LP_WAKE function can be found in Section 8.4.1.2.4.5.
INIT
The device is powered by a valid supply on the system power rail (VCCA ≥
VCCA_UV). If the device was previously in LP_STANDBY state, it has received
an external wake-up signal at the LP_WKUP1/2
pins, the RTC alarm or timer
wake-up signal, or an On Request from the nPWRON/ENABLE pin. Device digital and monitor circuits
are powered up. The PMIC reads its internal NVM memory in this state and
configures default values to registers, IO configuration and FSM
accordingly.
BOOT BIST
The device is running the built-in self-test routine
that includesNote: The ABIST on the voltage monitor
circuits for the BUCK regulators, the LDO regulators is performed
after the start-up of these regulators. The ABIST on the VMON1 and
VMON2 is performed after these voltage monitors are enabled. See
Voltage Monitors.
An option is available to shorten the device power up time from the
NO_SUPPLY state by setting the NVM bit FAST_BOOT_BIST = '1' to skip
the LBIST. Software can also set the FAST_BIST = '1' to skip LBIST
after the device wakes up from the LP STANDBY state. When the device
arrives at this state from the SAFE_RECOVERY state, LBIST is
automatically skipped if it has not previously failed. If LBIST
failed, but passed after multiple re-tries before exceeding the
recovery counter limit, the device powers up normally. The
following NVM bits are pre-configured options to enable or disable parts
of the CRC tests if further sequence time reduction is
required (please refer to the user's guide of the orderable part
number):
- REG_CRC_EN = '0':
disables the register map and SRAM CRC check
Note: Note: the BIST
tests are executed as parallel processes, and the longest process
determines the total BIST duration
Note: the ABIST on the voltage monitor circuits of the BUCKx
regulator, LDOn regulators, VMON1 and VMON2 is performed
individually after these voltage monitors are enabled. See Voltage
Monitors)
RUNTIME BIST
A request was received from the MCU to exercise a
run-time built-in self-test (RUNTIME_BIST) on the device. No rails are
modified and all external signals, including all I2C or SPI
interface communications, are ignored during the RUNTIME_ BIST. During
the RUNTIME_BIST, the device performs the same self-test routines as
listed for the BOOT_BIST state. Furthermore, during RUNTIME_BIST the
device performs the ABIST routine on all enabled voltage monitor
circuits.
If the device passed BIST, it resumes the previous operation. If the
device failed BIST, it shuts down all of the regulator outputs and
proceed to the SAFE RECOVERY state. In order to avoid a register CRC
error, all register writes must be avoided after the request for the
BIST operation until the device pulls the nINT pin low to indicate the
completion of BIST. The results of the RUNTIME_BIST are indicated by the
BIST_PASS_INT or the BIST_FAIL_INT interrupt bits.Note: After completion of
the RUNTIME_BIST, the LDOx_UV detections are masked for a
time-interval equal to the configured LDOx ramp-up time (25 mV/μs or
3 mV/μs according configuration bit LDOx_SLOW_RAMP). The actual LDOx
output voltages are not affected by this masking of the LDOx_UV
detections.
SAFE RECOVERY
The device meets the qualified error condition for immediate or ordered
shutdown request. If the error is recovered within the recovery time
interval or meets the restart condition, the device increments the
recovery counter, and returns to INIT state if the recovery counter
value does not exceed the threshold value. Until a supply power cycle
occurs, the device stays in the SAFE RECOVERY state if one of the
following conditions occur:
- the recovery counter exceeds the threshold value
- the die temperature cannot be reduced to less than
TWARN level
- VCCA stays above OVP threshold
When multiple system conditions occur
simultaneously that demand power state arbitration, the device goes to the higher
priority state according to the following priority order:
- NO SUPPLY
- BACKUP
- SAFE_RECOVERY
- LP_STANDBY
- MISSION STATES
Figure 8-36 shows the power transition states of the FSM engine.