JAJSLW7B December   2020  – September 2023 TPS6593-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
    1.     5
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Pin Configuration and Functions
    1. 6.1 Digital Signal Descriptions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  General Purpose Low Drop-Out Regulators (LDO1, LDO2, LDO3)
    6. 7.6  Low Noise Low Drop-Out Regulator (LDO4)
    7. 7.7  Internal Low Drop-Out Regulators (LDOVRTC, LDOVINT)
    8. 7.8  BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators
    9. 7.9  Reference Generator (BandGap)
    10. 7.10 Monitoring Functions
    11. 7.11 Clocks, Oscillators, and PLL
    12. 7.12 Thermal Monitoring and Shutdown
    13. 7.13 System Control Thresholds
    14. 7.14 Current Consumption
    15. 7.15 Backup Battery Charger
    16. 7.16 Digital Input Signal Parameters
    17. 7.17 Digital Output Signal Parameters
    18. 7.18 I/O Pullup and Pulldown Resistance
    19. 7.19 I2C Interface
    20. 7.20 Serial Peripheral Interface (SPI)
    21. 7.21 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  System Supply Voltage Monitor
      2. 8.3.2  Power Resources (Bucks and LDOs)
        1. 8.3.2.1 Buck Regulators
          1. 8.3.2.1.1  BUCK Regulator Overview
          2. 8.3.2.1.2  Multi-Phase Operation and Phase-Adding or Shedding
          3. 8.3.2.1.3  Transition Between PWM and PFM Modes
          4. 8.3.2.1.4  Multi-Phase BUCK Regulator Configurations
          5. 8.3.2.1.5  Spread-Spectrum Mode
          6. 8.3.2.1.6  Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support
          7. 8.3.2.1.7  BUCK Output Voltage Setting
          8. 8.3.2.1.8  BUCK Regulator Current Limit
          9. 8.3.2.1.9  SW_Bx Short-to-Ground Detection
          10. 8.3.2.1.10 Sync Clock Functionality
          11.        49
        2. 8.3.2.2 Low Dropout Regulators (LDOs)
          1. 8.3.2.2.1 LDOVINT
          2. 8.3.2.2.2 LDOVRTC
          3. 8.3.2.2.3 LDO1, LDO2, and LDO3
          4. 8.3.2.2.4 Low-Noise LDO (LDO4)
      3. 8.3.3  Output Voltage Monitor and PGOOD Generation
      4. 8.3.4  Thermal Monitoring
        1. 8.3.4.1 Thermal Warning Function
        2. 8.3.4.2 Thermal Shutdown
      5. 8.3.5  Backup Supply Power-Path
      6. 8.3.6  General-Purpose I/Os (GPIO Pins)
      7. 8.3.7  nINT, EN_DRV, and nRSTOUT Pins
      8. 8.3.8  Interrupts
      9. 8.3.9  RTC
        1. 8.3.9.1 General Description
        2. 8.3.9.2 Time Calendar Registers
          1. 8.3.9.2.1 TC Registers Read Access
          2. 8.3.9.2.2 TC Registers Write Access
        3. 8.3.9.3 RTC Alarm
        4. 8.3.9.4 RTC Interrupts
        5. 8.3.9.5 RTC 32-kHz Oscillator Drift Compensation
      10. 8.3.10 Watchdog (WDOG)
        1. 8.3.10.1 Watchdog Fail Counter and Status
        2. 8.3.10.2 Watchdog Start-Up and Configuration
        3. 8.3.10.3 MCU to Watchdog Synchronization
        4. 8.3.10.4 Watchdog Disable Function
        5. 8.3.10.5 Watchdog Sequence
        6. 8.3.10.6 Watchdog Trigger Mode
        7. 8.3.10.7 WatchDog Flow Chart and Timing Diagrams in Trigger Mode
        8.       79
        9. 8.3.10.8 Watchdog Question-Answer Mode
          1. 8.3.10.8.1 Watchdog Q&A Related Definitions
          2. 8.3.10.8.2 Question Generation
          3. 8.3.10.8.3 Answer Comparison
            1. 8.3.10.8.3.1 Sequence of the 2-bit Watchdog Answer Counter
            2. 8.3.10.8.3.2 Watchdog Sequence Events and Status Updates
            3. 8.3.10.8.3.3 Watchdog Q&A Sequence Scenarios
      11. 8.3.11 Error Signal Monitor (ESM)
        1. 8.3.11.1 ESM Error-Handling Procedure
          1. 8.3.11.1.1 Level Mode
          2.        90
          3. 8.3.11.1.2 PWM Mode
            1. 8.3.11.1.2.1 Good-Events and Bad-Events
            2. 8.3.11.1.2.2 ESM Error-Counter
            3. 8.3.11.1.2.3 ESM Start-Up in PWM Mode
            4. 8.3.11.1.2.4 ESM Flow Chart and Timing Diagrams in PWM Mode
            5.         96
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device State Machine
        1. 8.4.1.1 Fixed Device Power FSM
          1. 8.4.1.1.1 Register Resets and NVM Read at INIT State
        2. 8.4.1.2 Pre-Configurable Mission States
          1. 8.4.1.2.1 PFSM Commands
            1. 8.4.1.2.1.1  REG_WRITE_IMM Command
            2. 8.4.1.2.1.2  REG_WRITE_MASK_IMM Command
            3. 8.4.1.2.1.3  REG_WRITE_MASK_PAGE0_IMM Command
            4. 8.4.1.2.1.4  REG_WRITE_BIT_PAGE0_IMM Command
            5. 8.4.1.2.1.5  REG_WRITE_WIN_PAGE0_IMM Command
            6. 8.4.1.2.1.6  REG_WRITE_VOUT_IMM Command
            7. 8.4.1.2.1.7  REG_WRITE_VCTRL_IMM Command
            8. 8.4.1.2.1.8  REG_WRITE_MASK_SREG Command
            9. 8.4.1.2.1.9  SREG_READ_REG Command
            10. 8.4.1.2.1.10 SREG_WRITE_IMM Command
            11. 8.4.1.2.1.11 WAIT Command
            12. 8.4.1.2.1.12 DELAY_IMM Command
            13. 8.4.1.2.1.13 DELAY_SREG Command
            14. 8.4.1.2.1.14 TRIG_SET Command
            15. 8.4.1.2.1.15 TRIG_MASK Command
            16. 8.4.1.2.1.16 END Command
          2. 8.4.1.2.2 Configuration Memory Organization and Sequence Execution
          3. 8.4.1.2.3 Mission State Configuration
          4. 8.4.1.2.4 Pre-Configured Hardware Transitions
            1. 8.4.1.2.4.1 ON Requests
            2. 8.4.1.2.4.2 OFF Requests
            3. 8.4.1.2.4.3 NSLEEP1 and NSLEEP2 Functions
            4. 8.4.1.2.4.4 WKUP1 and WKUP2 Functions
            5. 8.4.1.2.4.5 LP_WKUP Pins for Waking Up from LP STANDBY
        3. 8.4.1.3 Error Handling Operations
          1. 8.4.1.3.1 Power Rail Output Error
          2. 8.4.1.3.2 Catastrophic Error
          3. 8.4.1.3.3 Watchdog (WDOG) Error
          4. 8.4.1.3.4 Warnings
        4. 8.4.1.4 Device Start-up Timing
        5. 8.4.1.5 Power Sequences
        6. 8.4.1.6 First Supply Detection
        7. 8.4.1.7 Register Power Domains and Reset Levels
      2. 8.4.2 Multi-PMIC Synchronization
        1. 8.4.2.1 SPMI Interface System Setup
        2. 8.4.2.2 Transmission Protocol and CRC
          1. 8.4.2.2.1 Operation with Transmission Errors
          2. 8.4.2.2.2 Transmitted Information
        3. 8.4.2.3 SPMI Target Device Communication to SPMI Controller Device
          1. 8.4.2.3.1 Incomplete Communication from SPMI Target Device to SPMI Controller Device
        4. 8.4.2.4 SPMI-BIST Overview
          1. 8.4.2.4.1 SPMI Bus during Boot BIST and RUNTIME BIST
          2. 8.4.2.4.2 Periodic Checking of the SPMI
          3. 8.4.2.4.3 SPMI Message Priorities
    5. 8.5 Control Interfaces
      1. 8.5.1 CRC Calculation for I2C and SPI Interface Protocols
      2. 8.5.2 I2C-Compatible Interface
        1. 8.5.2.1 Data Validity
        2. 8.5.2.2 Start and Stop Conditions
        3. 8.5.2.3 Transferring Data
        4. 8.5.2.4 Auto-Increment Feature
      3. 8.5.3 Serial Peripheral Interface (SPI)
    6. 8.6 Configurable Registers
      1. 8.6.1 Register Page Partitioning
      2. 8.6.2 CRC Protection for Configuration, Control, and Test Registers
      3. 8.6.3 CRC Protection for User Registers
      4. 8.6.4 Register Write Protection
        1. 8.6.4.1 Watchdog and ESM Configuration Registers
        2. 8.6.4.2 User Registers
    7. 8.7 Register Maps
      1. 8.7.1 TPS6593-Q1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Powering a Processor
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 VCCA
          2. 9.2.1.2.2 Internal LDOs
          3. 9.2.1.2.3 Crystal Oscillator
          4. 9.2.1.2.4 Buck Input Capacitors
          5. 9.2.1.2.5 Buck Output Capacitors
          6. 9.2.1.2.6 Buck Inductors
          7. 9.2.1.2.7 LDO Input Capacitors
          8. 9.2.1.2.8 LDO Output Capacitors
          9. 9.2.1.2.9 Digital Signal Connections
      2. 9.2.2 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
    2. 10.2 Device Nomenclature
    3. 10.3 Documentation Support
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 サポート・リソース
    6. 10.6 Trademarks
    7. 10.7 静電気放電に関する注意事項
    8. 10.8 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.1.1 Fixed Device Power FSM

The Fixed Device Power portion of the FSM engine manages the power up of the device before the power rails are fully enabled and ready to power external loadings, and the power down of the device when in the event of insufficient power supply or device or system error conditions. While the device is in one of the Hardware Device Powers states, the ENABLE_DRV bit remains low.

The definitions and transition triggers of the Device Power States are fixed and cannot be reconfigured.

Following are the definitions of the Device Power states:

    NO SUPPLY The device is not powered by a valid energy source on the system power rail. The device is completely powered off.
    BACKUP (RTC backup battery) The device is not powered by a valid supply on the system power rail (VCCA < VCCA_UVLO); a backup power source, however, is present and is within the operating range of the LDOVRTC. The RTC clock counter remains active in this state if it has been previously activated by appropriate register enable bit. The calendar function of the RTC block is activated, but not accessible in this state. Customer has the option to enable the shelf mode by disconnecting the VCCA supply completely, even while the backup battery is connected to the VBACKUP pin. The shelf mode forces the device to skip the BACKUP state and enters the NO SUPPLY state under VCCA_UVLO condition to reduce current draining from the backup battery.
    LP_STANDBY The device can enter this state from a mission state after receiving a valid OFF request or an I2C trigger, and the LP_STANDBY_SEL= 1. When the device is in this state, the RTC clock counter and the RTC Alarm or Timer Wake-up functions are active if they have been previously activated by appropriate register enable bit. Low Power Wake-up input monitor in the LDOVRTC domain (LP_WKUP secondary function through GPIO3 or GPIO4) and the on request monitors are also enabled in this state. When a logic level transition from high-to-low or low-to-high with a minimum pulse length of tLP_WKUP is detected on the assigned LP_WKUP pin, or if the device detects a valid on-request or a wake-up signal from the RTC block, the device proceeds to power up the device and reach the default mission state. More details regarding the LP_WAKE function can be found in Section 8.4.1.2.4.5.
    INIT The device is powered by a valid supply on the system power rail (VCCA ≥ VCCA_UV). If the device was previously in LP_STANDBY state, it has received an external wake-up signal at the LP_WKUP1/2 pins, the RTC alarm or timer wake-up signal, or an On Request from the nPWRON/ENABLE pin. Device digital and monitor circuits are powered up. The PMIC reads its internal NVM memory in this state and configures default values to registers, IO configuration and FSM accordingly.
    BOOT BIST The device is running the built-in self-test routine that includes
    Note: The ABIST on the voltage monitor circuits for the BUCK regulators, the LDO regulators is performed after the start-up of these regulators. The ABIST on the VMON1 and VMON2 is performed after these voltage monitors are enabled. See Voltage Monitors.
     An option is available to shorten the device power up time from the NO_SUPPLY state by setting the NVM bit FAST_BOOT_BIST = '1' to skip the LBIST. Software can also set the FAST_BIST = '1' to skip LBIST after the device wakes up from the LP STANDBY state. When the device arrives at this state from the SAFE_RECOVERY state, LBIST is automatically skipped if it has not previously failed. If LBIST failed, but passed after multiple re-tries before exceeding the recovery counter limit, the device powers up normally. The following NVM bits are pre-configured options to enable or disable parts of the CRC tests if further sequence time reduction is required (please refer to the user's guide of the orderable part number):
    • REG_CRC_EN = '0': disables the register map and SRAM CRC check
    Note: Note: the BIST tests are executed as parallel processes, and the longest process determines the total BIST duration
    Note: the ABIST on the voltage monitor circuits of the BUCKx regulator, LDOn regulators, VMON1 and VMON2 is performed individually after these voltage monitors are enabled. See Voltage Monitors)
    RUNTIME BIST A request was received from the MCU to exercise a run-time built-in self-test (RUNTIME_BIST) on the device. No rails are modified and all external signals, including all I2C or SPI interface communications, are ignored during the RUNTIME_ BIST. During the RUNTIME_BIST, the device performs the same self-test routines as listed for the BOOT_BIST state. Furthermore, during RUNTIME_BIST the device performs the ABIST routine on all enabled voltage monitor circuits. If the device passed BIST, it resumes the previous operation. If the device failed BIST, it shuts down all of the regulator outputs and proceed to the SAFE RECOVERY state. In order to avoid a register CRC error, all register writes must be avoided after the request for the BIST operation until the device pulls the nINT pin low to indicate the completion of BIST. The results of the RUNTIME_BIST are indicated by the BIST_PASS_INT or the BIST_FAIL_INT interrupt bits.
    Note: After completion of the RUNTIME_BIST, the LDOx_UV detections are masked for a time-interval equal to the configured LDOx ramp-up time (25 mV/μs or 3 mV/μs according configuration bit LDOx_SLOW_RAMP). The actual LDOx output voltages are not affected by this masking of the LDOx_UV detections.
    SAFE RECOVERY The device meets the qualified error condition for immediate or ordered shutdown request. If the error is recovered within the recovery time interval or meets the restart condition, the device increments the recovery counter, and returns to INIT state if the recovery counter value does not exceed the threshold value. Until a supply power cycle occurs, the device stays in the SAFE RECOVERY state if one of the following conditions occur:
    • the recovery counter exceeds the threshold value
    • the die temperature cannot be reduced to less than TWARN level
    • VCCA stays above OVP threshold

When multiple system conditions occur simultaneously that demand power state arbitration, the device goes to the higher priority state according to the following priority order:

  1. NO SUPPLY
  2. BACKUP
  3. SAFE_RECOVERY
  4. LP_STANDBY
  5. MISSION STATES

Figure 8-36 shows the power transition states of the FSM engine.

GUID-20201118-CA0I-4RS6-0XJT-5LSKZCLCJRHL-low.svg Figure 8-36 State Diagram for Device Power States