JAJSLW7B December 2020 – September 2023 TPS6593-Q1
PRODUCTION DATA
All of the LDO regulators in the TPS6593-Q1 device can be supplied by the system supply or another pre-regulated voltage source which are within the specified VIN range. The PVIN_LDOn voltage level must be equal or less than the VCCA voltage level to ensure proper operation of the LDOs. The default output voltages of all LDOs are loaded from the NVM memory and can be configured by the LDOn_VSET[7:0]. There is no hardware protection to prevent software from selecting an improper output voltage if the minimum level of PVIN_LDOn is lower than the dropout voltage of the LDO regulator in addition to the configured LDO output voltage. In such conditions, the output voltage droops to near the PVIN_LDOn level.
The LDO regulators do not have slew rate control for voltage ramp; by setting the LDOn_SLOW_RAMP bit to '1', however, the ramp up speed of the regulator output voltage is < 3 V/ms.
If an LDO is not needed, its associated UV/OV Voltage Monitor can be used to monitor an external voltage rail by connecting the external rail to the VOUT_LDOn pin. The voltage level of the monitored external rail must be within the PGOOD monitor range of the LDOn_VSET[7:0] of the LDO. If an external resistor divider is necessary in this case, the user must take into account the input impedance at the VOUT_LDOn pin (as shown in Figure 8-9), and adjust the resistor values to compensate for the voltage shift.