JAJSLW7B December 2020 – September 2023 TPS6593-Q1
PRODUCTION DATA
In Level Mode, after MCU has set the start bit (bit ESM_MCU_START or bit ESM_SOC_START), the ESM monitors its nERR_MCU or nERR_SoC input pin. Each ESM detects an ESM-error when the voltage level on its input pin remains low for a time equal or longer than the deglitch-time tdegl_ESMx. When an ESM_x detects an ESM-error, it starts the ESM Error-Handling procedure as described in Section 8.3.11.1. The Error-Handling Procedure is stopped if, before elapse of the delay-1 or delay-2 interval, the voltage level on the input pin remains high for a time equal or longer than the deglitch-time tdegl_ESMx and the MCU clears all corresponding interrupt bits. If the ESM-error persists such that the configured delay-1 and delay-2 times elapse, the ESM sends a ESM_x_RST trigger to the PFSM and the device clear the ESM_x_START bit. After the PFSM completes the handling of the ESM_x_RST trigger, the device re-initializes the ESM.
For a complete overview on how the ESM works in Level Mode, please refer to the flow-chart in Figure 8-25. In this flow-chart, the _x stands for either _MCU or _SoC. Figure 8-26, Figure 8-27, Figure 8-28, and Figure 8-29 show example wave forms for several error-cases for the ESM in Level Mode. In these examples, only the ESM_MCU is shown.