JAJSLW7B December 2020 – September 2023 TPS6593-Q1
PRODUCTION DATA
The watchdog includes a watchdog fail counter WD_FAIL_CNT[3:0] that increments because of bad events or decrements because of good events. Furthermore, the watchdog includes two configurable thresholds:
When the WD_FAIL_CNT[3:0] counter value is less than or equal to the configured Watchdog-Fail threshold (WD_FAIL_TH[2:0]) and bit WD_FIRST_OK=1, the MCU can set the ENABLE_DRV bit when no other error-flags are set.
When the WD_FAIL_CNT[3:0] counter value is greater than the configured Watchdog-Fail threshold (WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]), the device clears the ENABLE_DRV bit, sets the error-flag WD_FAIL_INT, and pulls the nINT pin low.
When the WD_FAIL_CNT[3:0] counter value is greater than the configured Watchdog-Fail plus Watchdog-Reset threshold (WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0])) and the watchdog-reset function is enabled (configuration bit WD_RST_EN=1), the device generates a WD_ERROR trigger in the state machine (see PFSM Trigger Selections) and sets the error-flag WD_RST_INT, and pulls the nINT pin low. Unless described otherwise in the user's guide of the orderable part number, this WD_ERROR trigger in the state machine causes the TPS6593-Q1 to execute a warm-reset, during which the nRSTOUT pin pulled low, and released after a pre-configured delay time.
The device clears the WD_FAIL_CNT[3:0] each time the watchdog enters the Long Window. The status bits WD_FAIL_INT and WD_RST_INT are latched until the MCU writes a ‘1’ to these bits.
Overview of Watchdog Fail Counter Value Ranges and Corresponding Device Status gives an overview of the Watchdog Fail Counter value ranges and the corresponding device status.
Watchdog Fail Counter value WD_FAIL_CNT[3:0] | Device Status |
---|---|
WD_FAIL_CNT[3:0] ≤ WD_FAIL_TH[2:0] | MCU can set the ENABLE_DRV bit if WD_FIRST_OK=1 and no other error-flags are set. |
WD_FAIL_TH[2:0] < WD_FAIL_CNT[3:0] ≤ (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) | The device sets error-flag WD_FAIL_INT and pulls the nINT pin low. Furthermore, , the device clears the ENABLE_DRV bit. |
WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) | If configuration bit WD_RST_EN=1, device generates WD_ERROR trigger in the state machine and reacts as defined in the PFSM, sets the error-flag WD_RST_INT, and pulls the nINT pin low. See Summary of Interrupt Signals for the interrupt handling of WD_RST. |
The WD_FAIL_CNT[3:0] counter responds as follows:
Refer to Watchdog Trigger Mode and Watchdog Q&A Related Definitions respectively for definitions of good events and bad events.