JAJSLW7B December   2020  – September 2023 TPS6593-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
    1.     5
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Pin Configuration and Functions
    1. 6.1 Digital Signal Descriptions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  General Purpose Low Drop-Out Regulators (LDO1, LDO2, LDO3)
    6. 7.6  Low Noise Low Drop-Out Regulator (LDO4)
    7. 7.7  Internal Low Drop-Out Regulators (LDOVRTC, LDOVINT)
    8. 7.8  BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators
    9. 7.9  Reference Generator (BandGap)
    10. 7.10 Monitoring Functions
    11. 7.11 Clocks, Oscillators, and PLL
    12. 7.12 Thermal Monitoring and Shutdown
    13. 7.13 System Control Thresholds
    14. 7.14 Current Consumption
    15. 7.15 Backup Battery Charger
    16. 7.16 Digital Input Signal Parameters
    17. 7.17 Digital Output Signal Parameters
    18. 7.18 I/O Pullup and Pulldown Resistance
    19. 7.19 I2C Interface
    20. 7.20 Serial Peripheral Interface (SPI)
    21. 7.21 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  System Supply Voltage Monitor
      2. 8.3.2  Power Resources (Bucks and LDOs)
        1. 8.3.2.1 Buck Regulators
          1. 8.3.2.1.1  BUCK Regulator Overview
          2. 8.3.2.1.2  Multi-Phase Operation and Phase-Adding or Shedding
          3. 8.3.2.1.3  Transition Between PWM and PFM Modes
          4. 8.3.2.1.4  Multi-Phase BUCK Regulator Configurations
          5. 8.3.2.1.5  Spread-Spectrum Mode
          6. 8.3.2.1.6  Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support
          7. 8.3.2.1.7  BUCK Output Voltage Setting
          8. 8.3.2.1.8  BUCK Regulator Current Limit
          9. 8.3.2.1.9  SW_Bx Short-to-Ground Detection
          10. 8.3.2.1.10 Sync Clock Functionality
          11.        49
        2. 8.3.2.2 Low Dropout Regulators (LDOs)
          1. 8.3.2.2.1 LDOVINT
          2. 8.3.2.2.2 LDOVRTC
          3. 8.3.2.2.3 LDO1, LDO2, and LDO3
          4. 8.3.2.2.4 Low-Noise LDO (LDO4)
      3. 8.3.3  Output Voltage Monitor and PGOOD Generation
      4. 8.3.4  Thermal Monitoring
        1. 8.3.4.1 Thermal Warning Function
        2. 8.3.4.2 Thermal Shutdown
      5. 8.3.5  Backup Supply Power-Path
      6. 8.3.6  General-Purpose I/Os (GPIO Pins)
      7. 8.3.7  nINT, EN_DRV, and nRSTOUT Pins
      8. 8.3.8  Interrupts
      9. 8.3.9  RTC
        1. 8.3.9.1 General Description
        2. 8.3.9.2 Time Calendar Registers
          1. 8.3.9.2.1 TC Registers Read Access
          2. 8.3.9.2.2 TC Registers Write Access
        3. 8.3.9.3 RTC Alarm
        4. 8.3.9.4 RTC Interrupts
        5. 8.3.9.5 RTC 32-kHz Oscillator Drift Compensation
      10. 8.3.10 Watchdog (WDOG)
        1. 8.3.10.1 Watchdog Fail Counter and Status
        2. 8.3.10.2 Watchdog Start-Up and Configuration
        3. 8.3.10.3 MCU to Watchdog Synchronization
        4. 8.3.10.4 Watchdog Disable Function
        5. 8.3.10.5 Watchdog Sequence
        6. 8.3.10.6 Watchdog Trigger Mode
        7. 8.3.10.7 WatchDog Flow Chart and Timing Diagrams in Trigger Mode
        8.       79
        9. 8.3.10.8 Watchdog Question-Answer Mode
          1. 8.3.10.8.1 Watchdog Q&A Related Definitions
          2. 8.3.10.8.2 Question Generation
          3. 8.3.10.8.3 Answer Comparison
            1. 8.3.10.8.3.1 Sequence of the 2-bit Watchdog Answer Counter
            2. 8.3.10.8.3.2 Watchdog Sequence Events and Status Updates
            3. 8.3.10.8.3.3 Watchdog Q&A Sequence Scenarios
      11. 8.3.11 Error Signal Monitor (ESM)
        1. 8.3.11.1 ESM Error-Handling Procedure
          1. 8.3.11.1.1 Level Mode
          2.        90
          3. 8.3.11.1.2 PWM Mode
            1. 8.3.11.1.2.1 Good-Events and Bad-Events
            2. 8.3.11.1.2.2 ESM Error-Counter
            3. 8.3.11.1.2.3 ESM Start-Up in PWM Mode
            4. 8.3.11.1.2.4 ESM Flow Chart and Timing Diagrams in PWM Mode
            5.         96
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device State Machine
        1. 8.4.1.1 Fixed Device Power FSM
          1. 8.4.1.1.1 Register Resets and NVM Read at INIT State
        2. 8.4.1.2 Pre-Configurable Mission States
          1. 8.4.1.2.1 PFSM Commands
            1. 8.4.1.2.1.1  REG_WRITE_IMM Command
            2. 8.4.1.2.1.2  REG_WRITE_MASK_IMM Command
            3. 8.4.1.2.1.3  REG_WRITE_MASK_PAGE0_IMM Command
            4. 8.4.1.2.1.4  REG_WRITE_BIT_PAGE0_IMM Command
            5. 8.4.1.2.1.5  REG_WRITE_WIN_PAGE0_IMM Command
            6. 8.4.1.2.1.6  REG_WRITE_VOUT_IMM Command
            7. 8.4.1.2.1.7  REG_WRITE_VCTRL_IMM Command
            8. 8.4.1.2.1.8  REG_WRITE_MASK_SREG Command
            9. 8.4.1.2.1.9  SREG_READ_REG Command
            10. 8.4.1.2.1.10 SREG_WRITE_IMM Command
            11. 8.4.1.2.1.11 WAIT Command
            12. 8.4.1.2.1.12 DELAY_IMM Command
            13. 8.4.1.2.1.13 DELAY_SREG Command
            14. 8.4.1.2.1.14 TRIG_SET Command
            15. 8.4.1.2.1.15 TRIG_MASK Command
            16. 8.4.1.2.1.16 END Command
          2. 8.4.1.2.2 Configuration Memory Organization and Sequence Execution
          3. 8.4.1.2.3 Mission State Configuration
          4. 8.4.1.2.4 Pre-Configured Hardware Transitions
            1. 8.4.1.2.4.1 ON Requests
            2. 8.4.1.2.4.2 OFF Requests
            3. 8.4.1.2.4.3 NSLEEP1 and NSLEEP2 Functions
            4. 8.4.1.2.4.4 WKUP1 and WKUP2 Functions
            5. 8.4.1.2.4.5 LP_WKUP Pins for Waking Up from LP STANDBY
        3. 8.4.1.3 Error Handling Operations
          1. 8.4.1.3.1 Power Rail Output Error
          2. 8.4.1.3.2 Catastrophic Error
          3. 8.4.1.3.3 Watchdog (WDOG) Error
          4. 8.4.1.3.4 Warnings
        4. 8.4.1.4 Device Start-up Timing
        5. 8.4.1.5 Power Sequences
        6. 8.4.1.6 First Supply Detection
        7. 8.4.1.7 Register Power Domains and Reset Levels
      2. 8.4.2 Multi-PMIC Synchronization
        1. 8.4.2.1 SPMI Interface System Setup
        2. 8.4.2.2 Transmission Protocol and CRC
          1. 8.4.2.2.1 Operation with Transmission Errors
          2. 8.4.2.2.2 Transmitted Information
        3. 8.4.2.3 SPMI Target Device Communication to SPMI Controller Device
          1. 8.4.2.3.1 Incomplete Communication from SPMI Target Device to SPMI Controller Device
        4. 8.4.2.4 SPMI-BIST Overview
          1. 8.4.2.4.1 SPMI Bus during Boot BIST and RUNTIME BIST
          2. 8.4.2.4.2 Periodic Checking of the SPMI
          3. 8.4.2.4.3 SPMI Message Priorities
    5. 8.5 Control Interfaces
      1. 8.5.1 CRC Calculation for I2C and SPI Interface Protocols
      2. 8.5.2 I2C-Compatible Interface
        1. 8.5.2.1 Data Validity
        2. 8.5.2.2 Start and Stop Conditions
        3. 8.5.2.3 Transferring Data
        4. 8.5.2.4 Auto-Increment Feature
      3. 8.5.3 Serial Peripheral Interface (SPI)
    6. 8.6 Configurable Registers
      1. 8.6.1 Register Page Partitioning
      2. 8.6.2 CRC Protection for Configuration, Control, and Test Registers
      3. 8.6.3 CRC Protection for User Registers
      4. 8.6.4 Register Write Protection
        1. 8.6.4.1 Watchdog and ESM Configuration Registers
        2. 8.6.4.2 User Registers
    7. 8.7 Register Maps
      1. 8.7.1 TPS6593-Q1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Powering a Processor
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 VCCA
          2. 9.2.1.2.2 Internal LDOs
          3. 9.2.1.2.3 Crystal Oscillator
          4. 9.2.1.2.4 Buck Input Capacitors
          5. 9.2.1.2.5 Buck Output Capacitors
          6. 9.2.1.2.6 Buck Inductors
          7. 9.2.1.2.7 LDO Input Capacitors
          8. 9.2.1.2.8 LDO Output Capacitors
          9. 9.2.1.2.9 Digital Signal Connections
      2. 9.2.2 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
    2. 10.2 Device Nomenclature
    3. 10.3 Documentation Support
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 サポート・リソース
    6. 10.6 Trademarks
    7. 10.7 静電気放電に関する注意事項
    8. 10.8 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.8 BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators

Over operating free-air temperature range (unless otherwise noted).  Voltage level are referenced to the thermal/ground pad of the device except for VOUT_Bn in multiphase configurations, in which case, the voltage level is referenced to the negative FB_Bn pin of the differential pair.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics - Output Voltage
4.1a VVOUT_Bn Output voltage configurable range 1-phase output 0.3 3.34 V
4.1b Multi-phase output 0.3 1.9 V
4.2a VVOUT_Bn_Step Output voltage configurable step size 0.3 V ≤ VVOUT_Bn < 0.6 V 20 mV
4.2b 0.6 V ≤ VVOUT_Bn < 1.1 V 5 mV
4.2c 1.1 V ≤ VVOUT_Bn < 1.66 V 10 mV
4.2d 1.66 V ≤ VVOUT_Bn < 3.34 V 20 mV
4.4 VDROPOUT_Bn Input and output voltage difference Minimum voltage between PVIN_Bn and VOUT_Bn to fulfill the electrical characteristics 0.7 V
4.5a VOUT_SR_Bn Output voltage slew-rate configurable range(5)(8) BUCKn_SLEW_RATE[2:0] = 000b 26.6 33.3 36.6 mV/µs
4.5b BUCKn_SLEW_RATE[2:0] = 001b 17 20 22 mV/µs
4.5c BUCKn_SLEW_RATE[2:0] = 010b 9 10 11 mV/µs
4.5d BUCKn_SLEW_RATE[2:0] = 011b 4.5 5 5.5 mV/µs
4.5e BUCKn_SLEW_RATE[2:0] = 100b 2.25 2.5 2.75 mV/µs
4.5f BUCKn_SLEW_RATE[2:0] = 101b 1.12 1.25 1.38 mV/µs
4.5g BUCKn_SLEW_RATE[2:0] = 110b 0.56 0.625 0.69 mV/µs
4.5h BUCKn_SLEW_RATE[2:0] = 111b 0.281 0.3125 0.344 mV/µs
Electrical Characteristics - Output Current, Limits and Thresholds
4.7a IOUT_Bn Output current(3)(4) 1-phase, BUCK5 2 A
4.7b 1-phase, BUCK4 4 A
4.7c 1-phase, BUCK1, BUCK2, BUCK3 3.5 A
4.7d 2-phase 7 A
4.7e 3-phase 10.5 A
4.7f 4-phase 14 A
4.8a IOUT_MP_Bal Current balancing for multi-phase output Mismatch between phase current and average phase current, 1A/phase < IOUT_Bn ≤ 2A / phase 20%
4.8b Mismatch between phase current and average phase current, IOUT_Bn > 2 A / phase 10%
4.9a ILIM_FWD_PEAK_ Range Forward current limit (peak during each switching cycle) configurable range BUCK5 2.5 3.5 A
4.9b BUCK1, BUCK2, BUCK3, BUCK4 2.5 5.5 A
4.10 ILIM_FWD_PEAK_Step Forward current limit step Size 1 A
4.11a ILIM_FWD_PEAK_Accuracy Forward current limit accuracy ILIM_FWD = 2.5 A or 3.5 A, 3.0 V ≤ VPVIN_Bn ≤ 5.5 V -0.55 0.55 A
4.11b ILIM_FWD = 4.5 A, 3.0 V ≤ VPVIN_Bn ≤ 5.5 V, BUCK1, BUCK2, BUCK3, BUCK4 -0.55 0.55 A
4.11c ILIM_FWD =  5.5 A, 3.0 V ≤ VPVIN_Bn ≤ 4.5 V, BUCK1, BUCK2, BUCK3, BUCK4 –15% 10%
4.11d ILIM_FWD = 5.5 A, 4.5 V ≤ VPVIN_Bn ≤ 5.5 V, BUCK1, BUCK2, BUCK3, BUCK4 –10% 10%
4.12 ILIM_NEG Negative current limit (peak during each switching cycle) 1.5 2 2.8 A
4.15a IADD Phase adding level (multi-phase rails) From 1-phase to 2-phase 2.0 A
4.15b From 2-phase to 3-phase 4.0 A
4.15c From 3-phase to 4-phase 6.0 A
4.16a ISHED Phase shedding level (multi-phase rails) From 2-phase to 1-phase 1.3 A
4.16b From 3-phase to 2-phase 2.7 A
4.16c From 4-phase to 3-phase 3.5 A
4.16d ISHED_Hyst Phase shedding hysteresis (multi-phase rails) Hysteresis from 2-phase to 1-phase 0.7 A
4.16e Hysteresis from 3-phase to 2-phase 1.3 A
4.16f Hysteresis from 4-phase to 3-phase 2.5 A
Electrical Characteristics - Current Consumption, On-Resistance, and Output Pulldown Resistance
4.17 Ioff Shutdown current, BUCKn disabled VCCA = VPVIN_Bn = 3.3 V.  TJ = 25°C 1 µA
4.18a IQ_AUTO Auto mode quiescent current IOUT_Bn = 0 mA, not switching, first single phase or primary phase in multi-phase configuration, TJ = 25°C 80 µA
4.18b IOUT_Bn = 0 mA, not switching, additional single phase or primary phase in multi-phase configuration, TJ = 25°C 60 µA
4.18c IOUT_Bn = 0 mA, not switching, secondary/tertiary/quaternary phase in multi-phase configuration, TJ = 25°C 30 µA
4.19a RDS(ON) HS FET On-resistance, high-side FET IOUT_Bn = 1 A, BUCK5 55 110 mΩ
4.19b IOUT_Bn = 1 A, BUCK1, BUCK2, BUCK3, BUCK4 52 100 mΩ
4.20a RDS(ON) LS FET On-resistance, low-side FET IOUT_Bn = 1 A, BUCK5 41 70 mΩ
4.20b IOUT_Bn = 1 A, BUCK1, BUCK2, BUCK3, BUCK4 30 55 mΩ
4.21 RDIS_Bn Output pulldown discharge resistance Regulator disabled, per phase, BUCKn_PLDN = 1 50 100 150 Ω
4.22 RSW_SC Short circuit detection resistance threshold at the SW pin 2 4.5 20 Ω
Electrical Characteristics - 4.4 MHz VOUT Less than 1.9 V, Multiphase or High COUT Single Phase
4.31 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V
4.32 VVOUT_Bn Output voltage configurable range 0.3 1.9 V
4.33a CIN_Bn Input filtering capacitance(1) 3 22 µF
4.33b COUT-Local(Buckn) Output capacitance, local(2) Per phase 10 22 µF
4.33c COUT-TOTAL_Bn Output capacitance, total (local and POL)(2) Per phase 70 250 µF
4.34a LBn Power inductor Inductance 154 220 286 nH
4.34b DCR 10 mΩ
4.35 IQ_PWM PWM mode Quiescent current Per phase, IOUT_Bn = 0 mA 19 mA
4.160a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV
4.160b VVOUT_Bx ≥ 1 V, PWM mode –1% 1%
4.160c VVOUT_Bx < 1 V, PFM mode –20 25 mV
4.160d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV
4.37a TLDSR_MP Transient load step response(7) 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 10 mV
4.37ba 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1.75A / phase, tr = tf = 1 µs, PWM mode, BUCK1, BUCK2, BUCK3, BUCK4 15 mV
4.37bb 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode, BUCK5 15 mV
4.37ca 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1.75 A / phase, tr = tf = 1 µs, PWM mode, BUCK1, BUCK2, BUCK3, BUCK4 1.2%
4.37cb 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode, BUCK5 1.0%
4.38 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT(max) -20 ±5 20 mV
4.39a VOUT_Ripple Ripple voltage(7) PWM mode, 1-phase 3 mVPP
4.39b PFM mode 15 25 mVPP
4.40 VTH_SC_RV(Bn) Threshold voltage for Short Circuit Bn_EN = 0 140 150 160 mV
4.102 IPWM-PFM PWM to PFM switch current threshold(6) Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 400 mA
4.101 IPFM-PWM PFM to PWM switch current threshold(6) Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 500 mA
4.103 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 100 mA
Electrical Characteristics - DDR VTT Termination, 2.2 MHz Single Phase Only
4.41 VPVIN_Bn Input voltage range 2.8 3.3 5.5 V
4.42 IOUT_Bn_SINK Current sink –1 A
4.43 VVOUT_Bn Output voltage programmable range 0.5 0.7 V
4.44a CIN_Bn Input filtering capacitance(1) 3 22 µF
4.44b COUT-TOTAL_Bn Output capacitance, local(2) 10 22 µF
4.44c COUT-TOTAL_Bn Output capacitance, total (local and POL)(2) 35 65 µF
4.45a LBn Power inductor Inductance 329 470 611 nH
4.45b DCR 10 mΩ
4.46a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 19 mA
4.161a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV
4.161b VVOUT_Bx ≥ 1 V, PWM mode –1% 1%
4.48 TLDSR_MP Transient load step response(7) 0.5 V ≤ VVOUT_Bn ≤ 0.7 V, IOUT_Bn = -1 mA to -1000 mA, tr = tf = 1 µs, PWM mode 15 mV
4.49 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) -20 ±5 20 mV
4.50 VOUT_Ripple Ripple voltage(7) PWM mode 3 6 mVPP
Electrical Characteristics - 4.4 MHz VOUT Less than 1.9 V, Low COUT, Single Phase Only
4.51 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V
4.52 VVOUT_Bn Output voltage configurable range 0.3 1.9 V
4.53a CIN_Bn Input filtering capacitance(1) 3 22 µF
4.53b COUT-Local_Bn Output capacitance, local(2) 10 22 µF
4.53c COUT-TOTAL_Bn Output capacitance, total (local and POL)(2) 25 100 µF
4.54a LBn Power inductor Inductance 154 220 286 nH
4.54b DCR 10 mΩ
4.55a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA, BUCK1, BUCK2, BUCK3, BUCK4 19 mA
4.55b IOUT_Bn = 0 mA, BUCK5 19 mA
4.162a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV
4.162b VVOUT_Bx ≥ 1 V, PWM mode –1% 1%
4.162c VVOUT_Bx < 1 V, PFM mode –20 35 mV
4.162d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 25 mV
4.57a TLDSR_MP Transient load step response(7) 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 200 mA / phase, tr = tf = 1 µs, PWM mode 15 mV
4.57b 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode 15 mV
4.57c 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode 1.5%
4.58 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) -20 ±5 20 mV
4.59a VOUT_Ripple Ripple voltage(7) PWM mode 5 8 mVPP
4.59b PFM mode 15 50 mVPP
4.111 IPFM-PWM PFM to PWM switch current threshold(6) Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 500 mA
4.112 IPWM-PFM PWM to PFM switch current threshold(6) Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 420 mA
4.113 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 100 mA
Electrical Characteristics - 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only
4.61 VPVIN_Bn Input voltage range 4.5 5 5.5 V
4.62 IOUT_Bn_4.4_HVOUT Output current 2.5 A
4.63 VVOUT_Bn Output voltage configurable range 1.7 3.34 V
4.64a CIN_Bn Input filtering capacitance(1) 3 22 µF
4.64b COUT-Local_Bn Output capacitance, local(2) 10 22 µF
4.64c COUT-TOTAL_Bn Output capacitance, total (local and POL)(2) 50 150 µF
4.65a LBn Power inductor Inductance 329 470 611 nH
4.65b DCR 10 mΩ
4.66a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 19 mA
4.163a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV
4.163b VVOUT_Bx ≥ 1 V, PWM mode –1% 1%
4.163c VVOUT_Bx < 1 V, PFM mode –20 25 mV
4.163d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV
4.68 TLDSR_SP Transient load step response(7) 1.7 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 1 A/phase, tr = tf = 1 µs, PWM mode 1.5%
4.69 TLNSR Transient line response VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) -20 ±5 20 mV
4.70a VOUT_Ripple Ripple voltage(7) PWM mode 3 7 mVPP
4.70b PFM mode 15 25 mVPP
4.121 IPFM-PWM PFM to PWM switch current threshold(6) Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 400 mA
4.122 IPWM-PFM PWM to PFM switch current threshold(6) Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 370 mA
4.123 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 30 mA
Electrical Characteristics - 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only
4.71 VPVIN_Bn Input voltage range 4.5 5 5.5 V
4.72 VVOUT_Bn Output voltage configurable range 0.3 3.34 V
4.73a CIN_Bn Input filtering capacitance(1) 3 22 µF
4.73b COUT-Local_Bn Output capacitance, local(2) 10 22 µF
4.73c COUT-TOTAL_Bn Output capacitance, total (local and POL)(2) 100 1000 µF
4.74a LBn Power inductor Inductance 700 1000 1300 nH
4.74b DCR 10 mΩ
4.75 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 13 mA
4.164a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV
4.164b VVOUT_Bx ≥ 1 V, PWM mode –1% 1%
4.164c VVOUT_Bx < 1 V, PFM mode –20 25 mV
4.164d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV
4.77a TLDSR_MP Transient load step response(7) 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 15 mV
4.77b 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 15 mV
4.77c 1.5 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 1.5%
4.78 TLNSR Transient line response VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) -20 ±5 20 mV
4.79a VOUT_Ripple Ripple voltage(7) PWM mode 3 7.5 mVPP
4.79b PFM mode 15 25 mVPP
4.131 IPFM-PWM PFM to PWM switch current threshold(6) Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 310 mA
4.132 IPWM-PFM PWM to PFM switch current threshold(6) Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 290 mA
4.133 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 20 mA
Electrical Characteristics - 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase
4.81 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V
4.82 VVOUT_Bn Output voltage configurable range 0.3 1.9 V
4.83a CIN_Bn Input filtering capacitance(1) 3 22 µF
4.83b COUT-Local_Bn Output capacitance, local(2) Per phase 10 22 µF
4.83c COUT-TOTAL_Bn Output capacitance, total (local and POL)(2) Per phase 100 1000 µF
4.84a LBn Power inductor Inductance 329 470 611 nH
4.84b DCR 10 mΩ
4.85 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 13 mA
4.165a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV
4.165b VVOUT_Bx ≥ 1 V, PWM mode –1% 1%
4.165c VVOUT_Bx < 1 V, PFM mode –20 25 mV
4.165d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV
4.87a TLDSR_MP Transient load step response(7) 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 5 mV
4.87b 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 15 mV
4.87c 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 1.0%
4.88 TLNSR Transient line response VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) -20 ±5 20 mV
4.89a VOUT_Ripple Ripple voltage(7) PWM mode, 1-phase 3 5 mVPP
4.89b PFM mode 15 25 mVPP
4.141 IPFM-PWM PFM to PWM switch current threshold(6) Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 500 mA
4.142 IPWM-PFM PWM to PFM switch current threshold(6) Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 400 mA
4.143 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 100 mA
Electrical Characteristics - 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only
4.91 VPVIN_Bn Input voltage range 2.8 3.3 5.5 V
4.92 VVOUT_Bn Output voltage configurable range 0.3 3.34 V
4.93a CIN_Bn Input filtering capacitance(1) 3 22 µF
4.93b COUT-Local_Bn Output capacitance, local(2) 10 22 µF
4.93c COUT-TOTAL_Bn Output capacitance, total (local and POL)(2) 100 500 µF
4.94a LBn Power inductor Inductance 700 1000 1300 nH
4.94b DCR 10 mΩ
4.95 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA, BUCK1, BUCK2, BUCK3, BUCK4 13 mA
4.166a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV
4.166b VVOUT_Bx ≥ 1 V, PWM mode –1% 1%
4.166d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV
4.166c VVOUT_Bx < 1 V, PFM mode –20 25 mV
4.97a TLDSR_SP Transient load step response(7) 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 35 mV
4.97b 0.6 V ≤ VVOUT_Bn < 1.0 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 17 mV
4.97c 1.0 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 3.5%
4.98 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) -20 ±5 20 mV
4.99a VOUT_Ripple Ripple voltage(7) PWM mode 3 7.5 mVPP
4.99b PFM mode 15 25 mVPP
4.151 IPFM-PWM PFM to PWM switch current threshold(6) Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 290 mA
4.152 IPWM-PFM PWM to PFM switch current threshold(6) Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 230 mA
4.153 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 50 mA
Switching Characteristics
20.1a fSW Steady state switching frequency in PWM mode (NVM configurable) 2.2 MHz setting, internal clock 2 2.2 2.4 MHz
20.1b 4.4 MHz setting, internal clock 4 4.4 4.8 MHz
20.1d 2.2 MHz setting, internal clock, spread spectrum 1.76 2.2 2.64 MHz
20.1e 4.4 MHz setting, internal clock, spread spectrum 3.5 4.4 5.3 MHz
20.1f 2.2 MHz setting, synchronized to external clock 1.76 2.2 2.64 MHz
20.1g 4.4 MHz setting, synchronized to external clock 3.5 4.4 5.3 MHz
20.2a fSW_max Automatic maximum switching frequency scaling in PWM mode 0.6 V ≤ VVOUT_Bn 4.4 MHz
20.2b 0.3 V ≤ VVOUT_Bn < 0.6 V 2.2 MHz
Timing Requirements
20.3 tsettle_Bn Settling time after voltage scaling From end of voltage ramp to within 15mV from target VOUT_DC_Bx 105 µs
20.4 tstartup_Bn Start-up delay From enable to start of output voltage rise 100 150 218 µs
20.5a tdelay_OC Over-current detection delay Peak current limit triggering during every
switching cycle		 7 µs
20.5b tdeglitch_OC Over-current detection signal deglitch time Digital deglitch time for detected signal.
Time duration to filter out short positive
and negative pulses		 19 23 µs
20.6 tlatency_OC Over-current signal latency time from detection Total delay from over-current detection to
interrupt or PFSM trigger		 30 µs
(1) Input capacitors must be placed as close as possible to the device pins.
(2) When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given DC voltage at the outputs of regulators.
(3) The maximum output current can be limited by the forward current limit. The maximum output current is also limited by the junction temperature and maximum average current over lifetime. The power dissipation inside the die increases the junction temperature and limits the maximum current depending on the length of the current pulse, efficiency, board and ambient temperature.
(4) Additional cooling strategies may be necessary to keep the device junction temperature at recommended limits with large output current.
(5) SLEW_RATEx[2:0] register default comes from NVM memory, and can be re-configured by the MCU.  Output capacitance, forward and negative current limits and load current may limit the maximum and minimum slew rates.
(6) The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage, and the inductor current level. The BUCK Regulator does not switch over from PWM to PFM for Fsw=2.2MHz and VOUT < 0.5V
(7) Please refer to the applications section of the data sheet regarding the power delivery network (PDN) used for the transient load step and output ripple test conditions.  All ripple specs are defined across POL capacitor in the described PDN.
(8) The 33.3 mV/µs slew-rate setting is not recommended for LBx ≥ 1 µH, as this can trigger OV detection due to larger overshoot at the buck output.