JAJSIA2B
December 2019 – February 2022
TPS6594-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
4
Revision History
5
概要 (続き)
6
Pin Configuration and Functions
6.1
Digital Signal Descriptions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
General Purpose Low Drop-Out Regulators (LDO1, LDO2, LDO3)
7.6
Low Noise Low Drop-Out Regulator (LDO4)
7.7
Internal Low Drop-Out Regulators (LDOVRTC, LDOVINT)
7.8
BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators
7.9
Reference Generator (BandGap)
7.10
Monitoring Functions
7.11
Clocks, Oscillators, and PLL
7.12
Thermal Monitoring and Shutdown
7.13
System Control Thresholds
7.14
Current Consumption
7.15
Backup Battery Charger
7.16
Digital Input Signal Parameters
7.17
Digital Output Signal Parameters
7.18
I/O Pullup and Pulldown Resistance
7.19
I2C Interface
7.20
Serial Peripheral Interface (SPI)
7.21
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
System Supply Voltage Monitor and Over-Voltage Protection
8.3.2
Power Resources (Bucks and LDOs)
8.3.2.1
Buck Regulators
8.3.2.1.1
BUCK Regulator Overview
8.3.2.1.2
Multi-Phase Operation and Phase-Adding or Shedding
8.3.2.1.3
Transition Between PWM and PFM Modes
8.3.2.1.4
Multi-Phase BUCK Regulator Configurations
8.3.2.1.5
Spread-Spectrum Mode
8.3.2.1.6
Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support
8.3.2.1.7
BUCK Output Voltage Setting
8.3.2.1.8
BUCK Regulator Current Limit
8.3.2.1.9
SW_Bx Short-to-Ground Detection
8.3.2.1.10
Sync Clock Functionality
48
8.3.2.2
Low Dropout Regulators (LDOs)
8.3.2.2.1
LDOVINT
8.3.2.2.2
LDOVRTC
8.3.2.2.3
LDO1, LDO2, and LDO3
8.3.2.2.4
Low-Noise LDO (LDO4)
8.3.3
Residual Voltage Checking
8.3.4
Output Voltage Monitor and PGOOD Generation
8.3.5
Thermal Monitoring
8.3.5.1
Thermal Warning Function
8.3.5.2
Thermal Shutdown
8.3.6
Backup Supply Power-Path
8.3.7
General-Purpose I/Os (GPIO Pins)
8.3.8
nINT, EN_DRV, and nRSTOUT Pins
8.3.9
Interrupts
8.3.10
RTC
8.3.10.1
General Description
8.3.10.2
Time Calendar Registers
8.3.10.2.1
TC Registers Read Access
8.3.10.2.2
TC Registers Write Access
8.3.10.3
RTC Alarm
8.3.10.4
RTC Interrupts
8.3.10.5
RTC 32-kHz Oscillator Drift Compensation
8.3.11
Watchdog (WDOG)
8.3.11.1
Watchdog Fail Counter and Status
8.3.11.2
Watchdog Start-Up and Configuration
8.3.11.3
MCU to Watchdog Synchronization
8.3.11.4
Watchdog Disable Function
8.3.11.5
Watchdog Sequence
8.3.11.6
Watchdog Trigger Mode
8.3.11.7
WatchDog Flow Chart and Timing Diagrams in Trigger Mode
79
8.3.11.8
Watchdog Question-Answer Mode
8.3.11.8.1
Watchdog Q&A Related Definitions
8.3.11.8.2
Question Generation
8.3.11.8.3
Answer Comparison
8.3.11.8.3.1
Sequence of the 2-bit Watchdog Answer Counter
8.3.11.8.3.2
Watchdog Sequence Events and Status Updates
8.3.11.8.3.3
Watchdog Q&A Sequence Scenarios
8.3.12
Error Signal Monitor (ESM)
8.3.12.1
ESM Error-Handling Procedure
8.3.12.1.1
Level Mode
90
8.3.12.1.2
PWM Mode
8.3.12.1.2.1
Good-Events and Bad-Events
8.3.12.1.2.2
ESM Error-Counter
8.3.12.1.2.3
ESM Start-Up in PWM Mode
8.3.12.1.2.4
ESM Flow Chart and Timing Diagrams in PWM Mode
96
8.4
Device Functional Modes
8.4.1
Device State Machine
8.4.1.1
Fixed Device Power FSM
8.4.1.1.1
Register Resets and NVM Read at INIT State
8.4.1.2
Pre-Configurable Mission States
8.4.1.2.1
PFSM Commands
8.4.1.2.1.1
REG_WRITE_IMM Command
8.4.1.2.1.2
REG_WRITE_MASK_IMM Command
8.4.1.2.1.3
REG_WRITE_MASK_PAGE0_IMM Command
8.4.1.2.1.4
REG_WRITE_BIT_PAGE0_IMM Command
8.4.1.2.1.5
REG_WRITE_WIN_PAGE0_IMM Command
8.4.1.2.1.6
REG_WRITE_VOUT_IMM Command
8.4.1.2.1.7
REG_WRITE_VCTRL_IMM Command
8.4.1.2.1.8
REG_WRITE_MASK_SREG Command
8.4.1.2.1.9
SREG_READ_REG Command
8.4.1.2.1.10
SREG_WRITE_IMM Command
8.4.1.2.1.11
WAIT Command
8.4.1.2.1.12
DELAY_IMM Command
8.4.1.2.1.13
DELAY_SREG Command
8.4.1.2.1.14
TRIG_SET Command
8.4.1.2.1.15
TRIG_MASK Command
8.4.1.2.1.16
END Command
8.4.1.2.2
Configuration Memory Organization and Sequence Execution
8.4.1.2.3
Mission State Configuration
8.4.1.2.4
Pre-Configured Hardware Transitions
8.4.1.2.4.1
ON Requests
8.4.1.2.4.2
OFF Requests
8.4.1.2.4.3
NSLEEP1 and NSLEEP2 Functions
8.4.1.2.4.4
WKUP1 and WKUP2 Functions
8.4.1.2.4.5
LP_WKUP Pins for Waking Up from LP STANDBY
8.4.1.3
Error Handling Operations
8.4.1.3.1
Power Rail Output Error
8.4.1.3.2
Boot BIST Error
8.4.1.3.3
Runtime BIST Error
8.4.1.3.4
Catastrophic Error
8.4.1.3.5
Watchdog (WDOG) Error
8.4.1.3.6
Error Signal Monitor (ESM) Error
8.4.1.3.7
Warnings
8.4.1.4
Device Start-up Timing
8.4.1.5
Power Sequences
8.4.1.6
First Supply Detection
8.4.1.7
Register Power Domains and Reset Levels
8.4.2
Multi-PMIC Synchronization
8.4.2.1
SPMI Interface System Setup
8.4.2.2
Transmission Protocol and CRC
8.4.2.2.1
Operation with Transmission Errors
8.4.2.2.2
Transmitted Information
8.4.2.3
SPMI Target Device Communication to SPMI Controller Device
8.4.2.3.1
Incomplete Communication from SPMI Target Device to SPMI Controller Device
8.4.2.4
SPMI-BIST Overview
8.4.2.4.1
SPMI Bus during Boot BIST and RUNTIME BIST
8.4.2.4.2
Periodic Checking of the SPMI
8.4.2.4.3
SPMI Message Priorities
8.5
Control Interfaces
8.5.1
CRC Calculation for I2C and SPI Interface Protocols
8.5.2
I2C-Compatible Interface
8.5.2.1
Data Validity
8.5.2.2
Start and Stop Conditions
8.5.2.3
Transferring Data
8.5.2.4
Auto-Increment Feature
8.5.3
Serial Peripheral Interface (SPI)
8.6
Configurable Registers
8.6.1
Register Page Partitioning
8.6.2
CRC Protection for Configuration, Control, and Test Registers
8.6.3
CRC Protection for User Registers
8.6.4
Register Write Protection
8.6.4.1
ESM and WDOG Configuration Registers
8.6.4.2
User Registers
8.7
Register Maps
8.7.1
TPS6594-Q1 Registers
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Powering a Processor
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.2.1
VCCA, VSYS_SENSE, and OVPGDRV
9.2.1.2.2
Internal LDOs
9.2.1.2.3
Crystal Oscillator
9.2.1.2.4
Buck Input Capacitors
9.2.1.2.5
Buck Output Capacitors
9.2.1.2.6
Buck Inductors
9.2.1.2.7
LDO Input Capacitors
9.2.1.2.8
LDO Output Capacitors
9.2.1.2.9
Digital Signal Connections
9.2.2
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Device Support
12.1.1
Third-Party Products Disclaimer
12.2
Device Nomenclature
12.3
Documentation Support
12.4
Receiving Notification of Documentation Updates
12.5
サポート・リソース
12.6
Trademarks
12.7
Electrostatic Discharge Caution
12.8
Glossary
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RWE|56
MPQF405A
サーマルパッド・メカニカル・データ
RWE|56
QFND656
発注情報
jajsia2b_oa
jajsia2b_pm
8.4
Device Functional Modes