JAJSIA2 データシート

JAJSIA2B December 2019 – February 2022 TPS6594-Q1

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RWE|56
- MPQF405A

サーマルパッド・メカニカル・データ

RWE|56
- QFND656

発注情報

7.11 Clocks, Oscillators, and PLL

Over operating free-air temperature range (unless otherwise noted).

POS	PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
Electrical Characteristics: CRYSTAL
6.1		Crystal frequency			32768		Hz
6.2		Crystal frequency tolerance	Parameter of crystal, T_J = 25°C	–20		20	ppm
6.4		Crystal series resistance	At fundamental frequency			90	kΩ
6.5		Oscillator drive power	The power dissipated in the crystal during oscillator operation		0.1	0.5	μW
6.6		Crystal Load capacitance⁽¹⁾	Corresponding to crystal frequency, including parasitic capacitances	6		12.5	pF
6.7		Crystal shunt capacitance	Parameter of crystal		1.4	2.6	pF
Electrical Characteristics: 32-kHz CRYSTAL OSCILLATOR EXTERNAL COMPONENTS
6.7a		Load capacitance on OSC32KIN and OSC32KOUT (parallel mode, including parasitic of PCB for external capacitor)⁽²⁾	External Capacitors	0		13	pF
6.7b			Internal Capacitors	9.5	12	14.5	pF
Switching Characteristics: 32-kHz CRYSTAL OSCILLATOR CLOCK
23.1		Crystal Oscillator output frequency	Typical with specified load capacitors		32768		Hz
23.2		Crystal Oscillator Output duty cycle	Parameter of crystal, T_J= 25°C	40%	50%	60%
23.3		Crystal Oscillator rise and fall time	10% to 90%, with 10 pF load capacitance		10	20	ns
23.4		Crystal Oscillator Settling time	From Oscillator enable to reaching ±1% of final output frequency			200	ms
Switching Characteristics: 20-MHz and 128-kHz RC OSCILLATOR CLOCK
23.10		20 MHz RC Oscillator output frequency		19	20	21	MHz
23.12		128 kHz RC Oscillator output frequency		121	128	135	kHz
Switching Characteristics: DPLL, SYNCCLKIN, and SYNCCLKOUT
22.1a		External input clock nominal frequency	EXT_CLK_FREQ = 0x0		1.1		MHz
22.1b			EXT_CLK_FREQ = 0x1		2.2
22.1c			EXT_CLK_FREQ = 0x2		4.4
22.2a		External input clock required accuracy from nominal frequency	SS_DEPTH = 0x0	–18%		18%
22.2b			SS_DEPTH = 0x1	–12%		12%
22.2c			SS_DEPTH = 0x2	–10%		10%
22.13a		Logic low time for SYNCCLKIN clock		40			ns
22.13b		Logic high time for SYNCCLKIN clock		40			ns
22.3		External clock detection delay for missing clock detection				1.8	µs
22.4		External clock input debounce time for clock detection				20	µs
22.5		Clock change delay (internal to external)	From valid clock detection to use of external clock		600		µs
22.7a		SYNCCLKOUT clock nominal frequency	SYNCCLKOUT_FREQ_SEL = 0x1		1.1		MHz
22.7b			SYNCCLKOUT_FREQ_SEL = 0x2		2.2		MHz
22.7c			SYNCCLKOUT_FREQ_SEL = 0x3		4.4		MHz
22.8		SYNCCLKOUT duty-cycle	Cycle-to-cycle	40%	50%	60%
22.9		SYNCCLKOUT output buffer external load		5	35	50	pF
22.11a		Spread spectrum variation for nominal switching frequency	SS_DEPTH = 0x1		6.3%
22.11b		Spread spectrum variation for nominal switching frequency	SS_DEPTH = 0x2		8.4%
Timing Requirements: Clock Monitors
26.7a	t_{latency_CLKfail}	Clock Monitor Failure signal latency from occurrence of error	Failure on 20MHz system clock			10	µs
26.7b	t_{latency_CLKfail}		Failure on 128KHz monitoring clock			40	µs
26.8	t_{latency_CLKdrift}	Clock Monitor Drift signal latency from detection				115	µs
26.9	f_sysclk	Internal system clock		19	20	21	MHz
26.10	CLKdrift_TH	Threshold for internal system clock frequency drift detection		-20%		20%
26.11	CLKfail_TH	Threshold for internal system clock stuck at high or stuck at low detection				10	MHz

(1) Customer must use the XTAL_SEL bit to select the corresponding crystal based on its load capacitance.

(2) External capacitors must be used if crystal load capacitance > 6 pF.