JAJSLQ9C February   2016  – August 2021 TPS65981

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Supply Requirements and Characteristics
    6. 7.6  Power Supervisor Characteristics
    7. 7.7  Power Consumption Characteristics
    8. 7.8  Cable Detection Characteristics
    9. 7.9  USB-PD Baseband Signal Requirements and Characteristics
    10. 7.10 USB-PD TX Driver Voltage Adjustment Parameter
    11. 7.11 Port Power Switch Characteristics
    12. 7.12 Port Data Multiplexer Switching Characteristics
    13. 7.13 Port Data Multiplexer Clamp Characteristics
    14. 7.14 Port Data Multiplexer SBU Detection Requirements
    15. 7.15 Port Data Multiplexer Signal Monitoring Pullup and Pulldown Characteristics
    16. 7.16 Port Data Multiplexer USB Endpoint Requirements and Characteristics
    17. 7.17 Port Data Multiplexer BC1.2 Detection Requirements and Characteristics
    18. 7.18 Analog-to-Digital Converter (ADC) Characteristics
    19. 7.19 Input-Output (I/O) Requirements and Characteristics
    20. 7.20 I2C Slave Requirements and Characteristics
    21. 7.21 SPI Controller Characteristics
    22. 7.22 BUSPOWERZ Configuration Requirements
    23. 7.23 Single-Wire Debugger (SWD) Timing Requirements
    24. 7.24 Thermal Shutdown Characteristics
    25. 7.25 HPD Timing Requirements and Characteristics
    26. 7.26 Oscillator Requirements and Characteristics
    27. 7.27 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  USB-PD Physical Layer
        1. 9.3.1.1 USB-PD Encoding and Signaling
        2. 9.3.1.2 USB-PD Bi-Phase Marked Coding
        3. 9.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 9.3.1.4 USB-PD BMC Transmitter
        5. 9.3.1.5 USB-PD BMC Receiver
      2. 9.3.2  Cable Plug and Orientation Detection
        1. 9.3.2.1 Configured as a DFP
        2. 9.3.2.2 Configured as a UFP
        3. 9.3.2.3 Dead-Battery or No-Battery Support
      3. 9.3.3  Port Power Switches
        1. 9.3.3.1  5-V Power Delivery
        2. 9.3.3.2  5V Power Switch as a Source
        3. 9.3.3.3  PP_5V0 Current Sense
        4. 9.3.3.4  PP_5V0 Current Limit
        5. 9.3.3.5  Internal HV Power Delivery
        6. 9.3.3.6  Internal HV Power Switch as a Source
        7. 9.3.3.7  Internal HV Power Switch as a Sink
        8. 9.3.3.8  Internal HV Power Switch Current Sense
        9. 9.3.3.9  Internal HV Power Switch Current Limit
        10. 9.3.3.10 External HV Power Delivery
        11. 9.3.3.11 External HV Power Switch as a Source with RSENSE
        12. 9.3.3.12 External HV Power Switch as a Sink With RSENSE
        13. 9.3.3.13 External HV Power Switch as a Sink Without RSENSE
        14. 9.3.3.14 External Current Sense
        15. 9.3.3.15 External Current Limit
        16. 9.3.3.16 Soft Start
        17. 9.3.3.17 BUSPOWERZ
        18. 9.3.3.18 Voltage Transitions on VBUS through Port Power Switches
        19. 9.3.3.19 HV Transition to PP_RV0 Pull-down on VBUS
        20. 9.3.3.20 VBUS Transition to VSAFE0V
        21. 9.3.3.21 C_CC1 and C_CC2 Power Configuration and Power Delivery
        22. 9.3.3.22 PP_CABLE to C_CC1 and C_CC2 Switch Architecture
        23. 9.3.3.23 PP_CABLE to C_CC1 and C_CC2 Current Limit
      4. 9.3.4  USB Type-C® Port Data Multiplexer
        1. 9.3.4.1 USB Top and Bottom Ports
        2. 9.3.4.2 Multiplexer Connection Orientation
        3. 9.3.4.3 SBU Crossbar Multiplexer
        4. 9.3.4.4 Signal Monitoring and Pull-up and Pull-down
        5. 9.3.4.5 Port Multiplexer Clamp
        6. 9.3.4.6 USB2.0 Low-Speed Endpoint
        7. 9.3.4.7 Battery Charger (BC1.2) Detection Block
        8. 9.3.4.8 BC1.2 Data Contact Detect
        9. 9.3.4.9 BC1.2 Primary and Secondary Detection
      5. 9.3.5  Power Management
        1. 9.3.5.1 Power-On and Supervisory Functions
        2. 9.3.5.2 Supply Switch-Over
        3. 9.3.5.3 RESETZ and MRESET
      6. 9.3.6  Digital Core
      7. 9.3.7  USB-PD BMC Modem Interface
      8. 9.3.8  System Glue Logic
      9. 9.3.9  Power Reset Congrol Module (PRCM)
      10. 9.3.10 Interrupt Monitor
      11. 9.3.11 ADC Sense
      12. 9.3.12 I2C Slave
      13. 9.3.13 SPI Controller
      14. 9.3.14 Single-Wire Debugger Interface
      15. 9.3.15 DisplayPort HPD Timers
      16. 9.3.16 ADC
        1. 9.3.16.1 ADC Divider Ratios
        2. 9.3.16.2 ADC Operating Modes
        3. 9.3.16.3 Single Channel Readout
        4. 9.3.16.4 Round-Robin Automatic Readout
        5. 9.3.16.5 One Time Automatic Readout
      17. 9.3.17 I/O Buffers
        1. 9.3.17.1 IOBUF_GPIOLS and IOBUF_GPIOLSI2C
        2. 9.3.17.2 IOBUF_OD
        3. 9.3.17.3 IOBUF_PORT
        4. 9.3.17.4 IOBUF_I2C
        5. 9.3.17.5 IOBUF_GPIOHSPI
        6. 9.3.17.6 IOBUF_GPIOHSSWD
      18. 9.3.18 Thermal Shutdown
      19. 9.3.19 Oscillators
    4. 9.4 Device Functional Modes
      1. 9.4.1 Boot Code
      2. 9.4.2 Initialization
      3. 9.4.3 I2C Configuration
      4. 9.4.4 Dead-Battery Condition
      5. 9.4.5 Application Code
      6. 9.4.6 Flash Memory Read
      7. 9.4.7 Invalid Flash Memory
    5. 9.5 Programming
      1. 9.5.1 SPI Controller Interface
      2. 9.5.2 I2C Slave Interface
        1. 9.5.2.1 I2C Interface Description
        2. 9.5.2.2 I2C Clock Stretching
        3. 9.5.2.3 I2C Address Setting
        4. 9.5.2.4 Unique Address Interface
        5. 9.5.2.5 I2C Pin Address Setting
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Fully-Featured USB Type-C® and PD Charger Application
        1. 10.2.1.1 Design Requirements
          1. 10.2.1.1.1 External FET Path Components (PP_EXT and RSENSE)
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 TPS65981 External Flash
          2. 10.2.1.2.2 Debug Control (DEBUG_CTL) and I2C (I2C) Resistors
          3. 10.2.1.2.3 Oscillator (R_OSC) Resistor
          4. 10.2.1.2.4 VBUS Capacitor and Ferrite Bead
          5. 10.2.1.2.5 Soft Start (SS) Capacitor
          6. 10.2.1.2.6 USB Top (C_USB_T), USB Bottom (C_USB_B), and Sideband-Use (SBU) Connections
          7. 10.2.1.2.7 Port Power Switch (PP_EXT, PP_HV, PP_5V0, and PP_CABLE) Capacitors
          8. 10.2.1.2.8 Cable Connection (CCn) Capacitors and RPD_Gn Connections
          9. 10.2.1.2.9 LDO_3V3, LDO_1V8A, LDO_1V8D, LDO_BMC, VIN_3V3, and VDDIO
        3. 10.2.1.3 Application Curve
      2. 10.2.2 USB Type-C® and PD Dock or Monitor Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Port Power Switch (PP_5V0 and PP_CABLE) Capacitors
          2. 10.2.2.2.2 HD3SS460 Control and DisplayPort Configuration
          3. 10.2.2.2.3 AC-DC Power Supply (Barrel Jack) Detection Circuitry
          4. 10.2.2.2.4 TPS65981 Control of Variable Buck Regulator Output Voltage (PP_HV)
          5. 10.2.2.2.5 TPS65981 and System Controller Interaction
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 3.3 V Power
      1. 11.1.1 VIN_3V3 Input Switch
      2. 11.1.2 VBUS 3.3-V LDO
    2. 11.2 1.8 V Core Power
      1. 11.2.1 1.8 V Digital LDO
      2. 11.2.2 1.8 V Analog LDO
    3. 11.3 VDDIO
      1. 11.3.1 Recommended Supply Load Capacitance
      2. 11.3.2 Schottky for Current Surge Protection
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1  TPS65981 Recommended Footprint
      2. 12.1.2  Top TPS65981 Placement and Bottom Component Placement and Layout
      3. 12.1.3  Component Placement
      4. 12.1.4  Designs Rules and Guidance
      5. 12.1.5  Routing PP_HV, PP_EXT, PP_5V0, and VBUS
      6. 12.1.6  Routing Top and Bottom Passive Components
      7. 12.1.7  Thermal Pad Via Placement
      8. 12.1.8  Top Layer Routing
      9. 12.1.9  Inner Signal Layer Routing
      10. 12.1.10 Bottom Layer Routing
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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発注情報

7.11 Port Power Switch Characteristics

Recommended operating conditions; TA = –40°C to +105°C unless otherwise noted. The maximum capacitance on VBUS, when configured as a source, must not exceed 12 µF.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
RPPCCPP_CABLE to C_CCn power switch resistance312mΩ
RPP5VPP_5V0 to VBUS power switch resistance5575mΩ
RPPHVPP_HV to VBUS power switch resistance95135mΩ
IHVACTActive quiescent current from PP_HV pinEN_HV = 11mA
IHVSDShutdown quiescent current from PP_HV pinEN_HV = 0100μA
IHVEXTACTActive quiescent current from SENSEP pin,Configured as source; EN_HV = 11mA
Active quiescent current from VBUS pinConfigured as sink; EN_HV = 13.5mA
IHVEXTSDShutdown quiescent current from SENSEP pinEN_HV = 040μA
IPP5VACTActive quiescent current from PP_5V01mA
IPP5VSDShutdown quiescent current from PP_5V0100μA
ILIMHV(4)PP_HV current limit, setting 01.0071.1181.330A
PP_HV current limit, setting 11.2581.3981.638A
PP_HV current limit, setting 21.511.6781.945A
PP_HV current limit, setting 31.7611.9572.153A
PP_HV current limit, setting 52.0132.2372.46A
PP_HV current limit, setting 62.2652.5162.768A
PP_HV current limit, setting 72.5162.7963.076A
PP_HV current limit, setting 82.7683.0763.383A
PP_HV current limit, setting 93.023.3553.691A
PP_HV current limit, setting 103.2713.6353.998A
PP_HV current limit, setting 113.5233.9144.306A
PP_HV current limit, setting 123.7754.1944.613A
PP_HV current limit, setting 134.0264.4744.921A
PP_HV current limit, setting 144.2784.7535.228A
PP_HV current limit, setting 154.5295.0335.536A
PP_HV current limit, setting 165.0335.5926.151A
ILIMHVEXT(3)(4)PP_EXT current limit, setting 00.9861.121.254A
PP_EXT current limit, setting 11.2311.3991.567A
PP_EXT current limit, setting 21.4771.6781.879A
PP_EXT current limit, setting 31.7611.9572.153A
PP_EXT current limit, setting 42.0122.2362.46A
PP_EXT current limit, setting 52.2632.5152.767A
PP_EXT current limit, setting 62.5142.7943.074A
PP_EXT current limit, setting 72.7653.0733.381A
PP_EXT current limit, setting 83.0163.3523.688A
PP_EXT current limit, setting 93.2673.6313.995A
PP_EXT current limit, setting 103.5193.914.301A
PP_EXT current limit, setting 113.774.1894.608A
PP_EXT current limit, setting 124.0214.4684.915A
PP_EXT current limit, setting 134.2724.7475.222A
PP_EXT current limit, setting 144.5235.0265.529A
PP_EXT current limit, setting 155.0255.5846.143A
ILIMPP5V(4)PP_5V0 current limit, setting 01.0061.1181.330A
PP_5V0 current limit, setting 11.1321.2581.484A
PP_5V0 current limit, setting 21.2581.3981.638A
PP_5V0 current limit, setting 31.3841.5381.691A
PP_5V0 current limit, setting 41.511.6771.845A
PP_5V0 current limit, setting 51.6361.8171.999A
PP_5V0 current limit, setting 61.7611.9572.153A
PP_5V0 current limit, setting 71.8872.0972.307A
PP_5V0 current limit, setting 82.0132.2372.46A
PP_5V0 current limit, setting 92.1392.3762.614A
PP_5V0 current limit, setting 102.2652.5162.768A
PP_5V0 current limit, setting 112.392.6562.922A
PP_5V0 current limit, setting 122.5162.7963.075A
PP_5V0 current limit, setting 132.6422.9363.229A
PP_5V0 current limit, setting 142.7683.0753.383A
PP_5V0 current limit, setting 153.0193.3553.69A
ILIMPPCCPP_CABLE current limit (highest setting)0.60.750.9A
PP_CABLE current limit (lowest setting)0.350.450.55A
IHV_ACC(1)PP_HV current sense accuracy I = 100 mA, Reverse current blocking disabled3.2556.75A/V
 I = 200 mA456A/V
 I = 500 mA4.455.6A/V
 I ≥ 1 A4.555.5A/V
IHVEXT_ACCPP_EXT current sense accuracy (excluding RSENSE accuracy) I = 100 mA, RSENSE = 10 mΩ, Reverse current blocking disabled3.556.5A/V
 I = 200 mA, RSENSE = 10 mΩ456A/V
 I = 500 mA, RSENSE = 10 mΩ4.455.6A/V
 I ≥ 1 A, RSENSE = 10 mΩ4.555.5A/V
IPP5V_ACC(1)PP_5V0 current sense accuracy I = 100 mA, Reverse current blocking disabled1.9534.05A/V
 I = 200 mA2.433.6A/V
 I = 500 mA2.6433.36A/V
 I ≥ 1 A2.733.3A/V
IPPCBL_ACCPP_CABLE current sense accuracy I = 100 mA1A/V
 I = 200 mA1A/V
 I = 500 mA1A/V
IGATEEXT(2)External gate-drive current on HV_GATE1 and HV_GATE2456μA
VGSEXTVGS voltage driving external FETs4.57.5V
TON_HVPP_HV path turn on time from enable to VBUS = 95% of PP_HV voltageConfigured as a source or as a sink with soft start disabled. PP_HV = 20 V, CVBUS = 10 μF, ILOAD = 100 mA8ms
TON_5VPP_5V0 path turn on time from enable to VBUS = 95% of PP_5V0 voltageConfigured as a source or as a sink with soft start disabled. PP_5V0 = 5 V, CVBUS = 10 μF, ILOAD = 100 mA2.5ms
TON_CCPP_CABLE path turn on time from enable to C_CCn = 95% of the PP_CABLE voltagePP_CABLE = 5 V, C_CCn = 500 nF, ILOAD = 100 mA2ms
ISSSoft-start charging current5.578.5μA
RSS_DISSoft-start discharge resistance0.611.4kΩ
VTHSSSoft-start complete threshold1.351.51.65V
TSSDONESoft-start complete timeCSS = 220 nF31.946.260.5ms
VREVPHVReverse current blocking voltage threshold for PP_HV switch2610mV
VREVPEXTReverse current blocking voltage Threshold for PP_EXT external switches2610mV
VREV5V0Reverse current blocking voltage threshold for PP_5V0 switches2610mV
VHVDISPDVoltage threshold above VIN at which the pull-down RHVDISPD on VBUS will disable during a transition from PHV to 5V045200250mV
VSAFE0VVoltage that is a safe 0 V per USB-PD Specifications00.8V
TSAFE0VVoltage transition time to VSAFE0V650ms
VSO_HVVoltage on PP_HV or PP_HVEXT above which the PP_HV or PP_EXT to PP_5V0 transition on VBUS will meet transition requirements9.9V
SRPOSMaximum slew rate for positive voltage transitions0.03V/μs
SRNEGMaximum slew rate for negative voltage transitions–0.03V/μs
TSTABLEEN to stable time for both positive and negative voltage transitions275ms
VSRCVALIDSupply output tolerance beyond VSRCNEW during time TSTABLE–0.50.5V
VSRCNEWSupply output tolerance–55%
(1) The current sense in the ADC does not accurately read below the current VREV5V0/RPP5V or VREVHV/RPPHV because of the reverse blocking behavior. When reverse blocking is disabled, the values given for accuracy are valid.
(2) Limit the resistance from the HV_GATE1/2 pins to the external FET gate pins to < 1Ω to provide adequate response time to short circuit events.
(3) Specified for a 10-mΩ RSENSE resistor and 10-mΩ RSENSE application code setting. The values scale with a different RSENSE resistance and application code setting.
(4) The settings are selected automatically by application code for the current limit required in the application.