SBVS068I February   2006  – January 2016 TPS717

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Shutdown
      3. 7.3.3 Startup and Noise Reduction Capacitor
      4. 7.3.4 Undervoltage Lockout (UVLO)
      5. 7.3.5 Minimum Load
      6. 7.3.6 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Transient Response
      2. 8.1.2 Input and Output Capacitor Requirements
      3. 8.1.3 Dropout Voltage
      4. 8.1.4 Output Noise
    2. 8.2 Typical Applications
      1. 8.2.1 Application for Fixed Voltage Versions and Adjustable Voltage Version
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Powering a PLL Integrated on an SOC
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
    2. 10.2 Layout Examples
    3. 10.3 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Module
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Revision History

Changes from H Revision (January 2015) to I Revision

  • Added TI Design Go
  • Changed PMOSFET to PMOS in Description section Go
  • Added footnote to the Recommended Operating Conditions tableGo
  • Changed VFB parameter in Electrical Characteristics table Go
  • Changed units of Vn parameter in Electrical Characteristics tableGo
  • Deleted UVLO parameter minimum specification from Electrical Characteristics tableGo
  • Changed TA to TJ in x-axis of Figure 7, Figure 10, and Figure 11 Go
  • Changed second paragraph of Startup and Noise Reduction Capacitor sectionGo
  • Changed last bullet in Normal Operation section Go
  • Changed value of the TJ column in last row of Table 1 Go
  • Added last sentence to Input and Output Capacitor Requirements sectionGo
  • Changed VREF to VFB in Equation 3 Go
  • Changed definition of z in Table 4 Go

Changes from G Revision (April 2009) to H Revision

  • Changed pin descriptions throughout Pin Functions tableGo
  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Changed load regulation typical specification from 120 µV to 70 µV to better reflect device performance Go
  • Changed condition for CNR = none for Vn parameterGo
  • Changed Figure 1, Figure 2, Figure 3, and Figure 4: removed legend, added call-outs for clarityGo
  • Changed titles of Figure 15, Figure 17, and Figure 25Go
  • Corrected input and output symbols in operational amplifiers in Functional Block Diagrams Go
  • Changed Undervoltage Lockout (UVLO) section text: reworded for clarityGo
  • Deleted Reverse Current Protection section Go

Changes from F Revision (February 2009) to G Revision

  • Changed min and max specs for Output accuracy, VOUT ≥ 1.0VGo