The TPS720-Q1 family of dual-rail, low-dropout linear regulators (LDOs) offers outstanding ac performance (PSRR, load and line transient response) and consume a very low quiescent current of 38 μA.
The VBIAS rail that powers the control circuit of the LDO draws very low current (on the order of the LDO quiescent current) and can be connected to any power supply that is equal to or greater than 1.4 V above the output voltage. The main power path is through VIN and can be a lower voltage than VBIAS; this path can be as low as VOUT + VDO, increasing the efficiency of the solution in many power-sensitive applications. For example, VIN can be an output of a high-efficiency, dc-dc, step-down regulator.
The TPS720-Q1 supports a novel feature where the output of the LDO regulates under light loads when the IN pin is left floating. The light-load drive current is sourced from VBIAS under this condition. This feature is particularly useful in power-saving applications where the dc-dc converter connected to the IN pin is disabled but the LDO is still required to regulate the voltage to a light load.
The TPS720-Q1 is stable with ceramic capacitors and uses an advanced BICMOS fabrication process that yields a dropout of 110 mV at a 350-mA output load. The TPS720-Q1 provides a monotonic VOUT rise (overshoot limited to 3%) with VIN inrush current limited to 100 mA + ILOAD with an output capacitor of 2.2 μF.
The TPS720-Q1 uses a precision voltage reference and feedback loop to achieve overall accuracy of 2% over load, line, process, and temperature extremes. The TPS720-Q1 is available in a 6-pin WSON package. This family of devices is fully specified over the temperature range of TJ = –40°C to +125°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS720-Q1 | WSON (6) | 2.00 mm × 2.00 mm |
Changes from * Revision (February 2016) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
OUT | 1 | O | Output pin. A 2.2-μF ceramic capacitor is connected from this pin to ground for stability and to provide load transients; see Input and Output Capacitor Requirements |
NC | 2 | — | No connection. |
EN | 3 | I | Enable pin. A logic high signal on this pin turns the device on and regulates the voltage from IN to OUT. A logic low on this pin turns the device off. |
BIAS | 4 | I | Bias supply pin. For better transient performance, TI recommends bypassing this input with a ceramic capacitor to ground; see Input and Output Capacitor Requirements |
GND | 5 | — | Ground pin. |
IN | 6 | I | Input pin. This pin can be a maximum of 4.5 V; VIN must not exceed VBIAS. Bypass this input with a ceramic capacitor to ground; see Input and Output Capacitor Requirements. |