JAJSEO1C June   2019  – May 2022 TPS745-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 TPS745-Q1 Comparison
      2. 7.3.2 Undervoltage Lockout (UVLO)
      3. 7.3.3 Shutdown
      4. 7.3.4 Foldback Current Limit
      5. 7.3.5 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Functional Mode Comparison
      2. 7.4.2 Normal Operation
      3. 7.4.3 Dropout Operation
      4. 7.4.4 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjustable Device Feedback Resistors
      2. 8.1.2 Input and Output Capacitor Selection
      3. 8.1.3 Dropout Voltage
      4. 8.1.4 Exiting Dropout
      5. 8.1.5 Reverse Current
      6. 8.1.6 Power Dissipation (PD)
      7. 8.1.7 Power-Good Function
      8. 8.1.8 Feed-Forward Capacitor (CFF)
      9. 8.1.9 Start-Up Sequencing
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Current
        2. 8.2.2.2 Thermal Dissipation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
      1.      Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

Figure 5-1 DRV Package,6-Pin Adjustable WSON(Top View)
Figure 5-3 DRB Package,8-Pin Adjustable VSON(Top View)
Figure 5-2 DRV Package,6-Pin Fixed WSON
(Top View)
Figure 5-4 DRB Package,8-Pin Fixed VSON
(Top View)
Table 5-1 Pin Functions
PINI/ODESCRIPTION
NAMEDRV
(Fixed)		DRV
(Adjust)		DRB
(Fixed)		DRB
(Adjust)
EN4455InputEnable pin. Drive EN greater than VEN(HI) to turn on the regulator. Drive EN less than VEN(LO) to put the low-dropout regulator (LDO) into shutdown mode.
FB—2—3—This pin is used as an input to the control loop error amplifier and is used to set the output voltage of the LDO.
GND3344—Ground pin.
IN6688InputInput pin. For best transient response and to minimize input impedance, use the recommended value or larger ceramic capacitor from IN to ground as listed in the Section 6.3 table and the Section 8.1.2 section. Place the input capacitor as close to the output of the device as possible.
NC2—2, 3, 72, 7—No internal connection. Ground this pin for better thermal performance.
OUT1111OutputRegulated output voltage pin. A capacitor is required from OUT to ground for stability. For best transient response, use the nominal recommended value or larger ceramic capacitor from OUT to ground; see the Section 6.3 table and the Section 8.1.2 section. Place the output capacitor as close to output of the device as possible.
PG5566OutputPower-good output. Available in open-drain and push-pull topologies. A pullup resistor is only required for the open-drain type. For the open-drain version, if the power-good functionality is not being used, ground this pin or leave floating. For the push-pull version, if the power-good functionality is not being used, leave this pin floating.
Thermal Pad—The thermal pad is electrically connected to the GND node. Connect to the GND plane for improved thermal performance.