JAJS238N January   2007  – June 2024

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics: IOUT = 50 mA
    7. 5.7 Typical Characteristics: IOUT = 1 A
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Enable/Shutdown
      2. 6.3.2 Power Good
      3. 6.3.3 Internal Current Limit
      4. 6.3.4 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
    5. 6.5 Programming
      1. 6.5.1 Programmable Soft-Start
      2. 6.5.2 Sequencing Requirements
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Adjusting the Output Voltage
      2. 7.1.2 Input, Output, and Bias Capacitor Requirements
      3. 7.1.3 Transient Response
      4. 7.1.4 Dropout Voltage
      5. 7.1.5 Output Noise
    2. 7.2 Typical Applications
      1. 7.2.1 FPGA I/O Supply at 1.5 V With a Bias Rail
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 FPGA I/O Supply at 1.5 V Without a Bias Rail
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Estimating Junction Temperature
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
      2. 8.1.2 Development Support
        1. 8.1.2.1 Evaluation Modules
        2. 8.1.2.2 Spice Models
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5.1 Programmable Soft-Start

The TPS74801 features a programmable, monotonic, voltage-controlled soft-start that is set with an external capacitor (CSS). This feature is important for many applications because soft-start eliminates power-up initialization problems when powering FPGAs, DSPs, or other processors. The controlled voltage ramp of the output also reduces peak inrush current during start-up, minimizing start-up transient events to the input power bus.

To achieve a linear and monotonic soft-start, the TPS74801 error amplifier tracks the voltage ramp of the external soft-start capacitor until the voltage exceeds the internal reference. The soft-start ramp time depends on the soft-start charging current (ISS), soft-start capacitance (CSS), and the internal reference voltage (VREF), and can be calculated using Equation 2:

Equation 2. TPS748

If large output capacitors are used, the device current limit (ICL) and the output capacitor can set the start-up time. In this case, the start-up time is given by Equation 3:

Equation 3. TPS748

where:

  • VOUT(nom) is the nominal output voltage
  • COUT is the output capacitance
  • ICL(min) is the minimum current limit for the device

In applications where monotonic start up is required, the soft-start time given by Equation 2 must be set greater than Equation 3.

The maximum recommended soft-start capacitor is 15 nF. Larger soft-start capacitors can be used and do not damage the device; however, the soft-start capacitor discharge circuit can possibly be unable to fully discharge the soft-start capacitor when enabled. Soft-start capacitors larger than 15 nF can be a problem in applications where the enable pin must be rapidly pulsed and with the device still required to soft-start from ground. CSS must be low-leakage; X7R, X5R, or C0G dielectric materials are preferred. See Table 6-2 for suggested soft-start capacitor values.

Table 6-2 Standard Capacitor Values for Programming the Soft-Start Time
CSS SOFT-START TIME(1)
(Legacy Chip)		 SOFT-START TIME(1)
(New Chip)
Open 0.1 ms 0.25ms
270 pF 0.5 ms 0.4ms
560 pF 1 ms 0.8ms
2.7 nF 5 ms 4.1ms
5.6 nF 10 ms 8.5ms
10 nF 18 ms 15ms
(1) tSS(s) = 0.8 × CSS(F) / ISS, where tSS(s) = soft-start time in seconds.

Another option to set the start-up rate is to use a feedforward capacitor; see the Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application note for more information.