The TPS786 family of low-dropout (LDO) low-power linear voltage regulators features high power-supply rejection ratio (PSRR), ultralow noise, fast start-up, and excellent line and load transient responses in small outline, SOT223-6 and DDPAK-5 packages. Each device in the family is stable, with a small 1-μF ceramic capacitor on the output. The family uses an advanced, proprietary BiCMOS fabrication process to yield extremely low dropout voltages (for example, 390 mV at 1.5 A). Each device achieves fast start-up times (approximately 50 μs with a 0.001-μF bypass capacitor) while consuming very low quiescent current (265 μA, typical). Moreover, when the device is placed in standby mode, the supply current is reduced to less than 1 μA. The TPS78630 exhibits approximately 48 μVRMS of output voltage at 3-V output noise with a 0.1-μF bypass capacitor. Applications with analog components that are noise sensitive, such as portable RF electronics, benefit from the high PSRR, low noise features, and the fast response time.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS786 | TO-263 (5) | 10.16 mm × 8.42 mm |
SOT-223 (6) | 6.50 mm × 3.50 mm | |
SON (8) | 3.00 mm × 3.00 mm |
Changes from L Revision (October 2010) to M Revision
Changes from K Revision (August, 2010) to L Revision
Changes from J Revision (May, 2009) to K Revision
PIN | I/O | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | SOT-223 | TO-263 | SON | ||
NR | 5 | 5 | 5 | — | Noise-reduction pin for fixed versions only. An external bypass capacitor, connected to this terminal, in conjunction with an internal resistor, creates a low-pass filter to further reduce regulator noise. |
EN | 1 | 1 | 8 | I | The EN terminal is an input that enables or shuts down the device. When EN is a logic high, the device is enabled. When the device is a logic low, the device is in shutdown mode. |
FB | 5 | 5 | 5 | I | Feedback input voltage for the adjustable device. |
GND | 3, 6 | 3, TAB | 6 | — | Regulator ground |
IN | 2 | 2 | 1, 2 | I | Input supply |
OUT | 4 | 4 | 3, 4 | O | Regulator output |
MIN | MAX | UNIT | |
---|---|---|---|
VIN | –0.3 | 6 | V |
VEN | –0.3 | VIN + 0.3 | V |
VOUT | 6 | V | |
Peak output current | Internally limited | ||
Continuous total power dissipation | See Thermal Information | ||
Junction temperature, TJ | –40 | 150 | °C |
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V | |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VIN Input supply voltage | 2.7 | 5.5 | V | ||
IOUT Output current | 0 | 1.5 | A | ||
TJ Operating junction temperature | –40 | 125 | °C |
THERMAL METRIC(1)(2) | TPS786(3) | UNIT | |||
---|---|---|---|---|---|
DRB (SON) | DCQ (S0T-223) | KTT (TO-263) | |||
8 PINS | 6 PINS | 5 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 41.1 | 54.2 | 40.7 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 49.1 | 33.3 | 43.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 16.6 | 8.9 | 21.5 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.7 | 2.6 | 9.4 | °C/W |
ψJB | Junction-to-board characterization parameter | 16.8 | 8.8 | 20 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 5.2 | N/A | 2.1 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
Input voltage, VIN(1) | 2.7 | 5.5 | V | |||||
Internal reference, VFB (TPS78601) | 1.200 | 1.225 | 1.250 | V | ||||
Continuous output current IOUT | 0 | 1.5 | A | |||||
Output voltage |
Output voltage range | TPS78601 | 1.225 | 5.5 – VDO | V | |||
Accuracy | TPS78601(2) | 0 μA ≤ IOUT ≤ 1.5 A, VOUT + 1 V ≤ VIN ≤ 5.5 V(1) | (0.98)VOUT | VOUT | (1.02)VOUT | V | ||
Fixed VOUT < 5 V | 0 μA ≤ IOUT ≤ 1.5 A, VOUT + 1 V ≤ VIN ≤ 5.5 V(1) | –2% | 2% | |||||
Fixed VOUT = 5 V | 0 μA ≤ IOUT ≤ 1.5 A, VOUT + 1 V ≤ VIN ≤ 5.5 V(1) | –3% | 3% | |||||
Output voltage line regulation (ΔVOUT%/VIN)(1) | VOUT + 1 V ≤ VIN ≤ 5.5 V | 5 | 12 | %/V | ||||
Load regulation (ΔVOUT%/VOUT) | 0 μA ≤ IOUT ≤ 1.5 A | 7 | mV | |||||
Dropout voltage(3)
VIN = VOUT(nom) – 0.1 V |
TPS78628 | IOUT = 1.5 A | 410 | 580 | mV | |||
TPS78630 | IOUT = 1.5 A | 390 | 550 | |||||
TPS78633 | IOUT = 1.5 A | 340 | 510 | |||||
TPS78650 | IOUT = 1.5 A | 310 | 470 | |||||
Output current limit | VOUT = 0 V | 2.4 | 4.2 | A | ||||
Ground pin current | 0 μA ≤ IOUT ≤ 1.5 A | 260 | 385 | μA | ||||
Shutdown current(4) | VEN = 0 V, 2.7 V ≤ VIN ≤ 5.5 V | 0.07 | 1 | μA | ||||
FB pin current | VFB = 1.225 V | 1 | μA | |||||
Power-supply ripple rejection | TPS78630 | f = 100 Hz, IOUT = 10 mA | 59 | dB | ||||
f = 100 Hz, IOUT = 1.5 A | 52 | |||||||
f = 10 kHz, IOUT = 1.5 A | 49 | |||||||
f = 100 kHz, IOUT = 1.5 A | 32 | |||||||
Output noise voltage (TPS78630) | BW = 100 Hz to 100 kHz, IOUT = 1.5 A |
CNR = 0.001 μF | 66 | μVRMS | ||||
CNR = 0.0047 μF | 51 | |||||||
CNR = 0.01 μF | 49 | |||||||
CNR = 0.1 μF | 48 | |||||||
Time, start-up (TPS78630) | RL = 2 Ω, COUT = 1 μF | CNR = 0.001 μF | 50 | μs | ||||
CNR = 0.0047 μF | 75 | |||||||
CNR = 0.01 μF | 110 | |||||||
High-level enable input voltage | 2.7 V ≤ VIN ≤ 5.5 V | 1.7 | VIN | V | ||||
Low-level enable input voltage | 2.7 V ≤ VIN ≤ 5.5 V | 0 | 0.7 | V | ||||
EN pin current | VEN = 0 | –1 | 1 | μA | ||||
UVLO threshold | VCC rising | 2.25 | 2.65 | V | ||||
UVLO hysteresis | 100 | mV |