SLVS389 Data sheet

SLVS389M September 2002 – September 2015 TPS786

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

DCQ|6
- MPDS098D
DRB|8
- MPDS118K
KTT|5
- MPSF007E

サーマルパッド・メカニカル・データ

DRB|8
- QFND043N
KTT|5
- PPTD069B

発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
V_IN	–0.3	6	V
V_EN	–0.3	V_IN + 0.3	V
V_OUT		6	V
Peak output current	Internally limited
Continuous total power dissipation	See Thermal Information
Junction temperature, T_J	–40	150	°C
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE		UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000		V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±500		V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)

	MIN	MAX	UNIT
V_IN Input supply voltage	2.7	5.5	V
I_OUT Output current	0	1.5	A
T_J Operating junction temperature	–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾⁽²⁾		TPS786⁽³⁾			UNIT
		DRB (SON)	DCQ (S0T-223)	KTT (TO-263)
		8 PINS	6 PINS	5 PINS
R_θJA	Junction-to-ambient thermal resistance	41.1	54.2	40.7	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	49.1	33.3	43.1	°C/W
R_θJB	Junction-to-board thermal resistance	16.6	8.9	21.5	°C/W
ψ_JT	Junction-to-top characterization parameter	0.7	2.6	9.4	°C/W
ψ_JB	Junction-to-board characterization parameter	16.8	8.8	20	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	5.2	N/A	2.1	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.

(3) Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations:

i. DRB: The exposed pad is connected to the PCB ground layer through a 2×2 thermal via array.
. ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3×2 thermal via array.
. iii. KTT: The exposed pad is connected to the PCB ground layer through a 5×4 thermal via array.
i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage.
. ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
. iii. KTT: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage.
These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3 inches × 3 inches copper area. To understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature sections of this data sheet.

6.5 Electrical Characteristics

Over recommended operating temperature range (T_J = –40°C to 125°C), V_EN = V_IN, V_IN = V_OUT(nom) + 1 V⁽¹⁾, I_OUT = 1 mA,
C_OUT = 10 μF, and C_NR = 0.01 μF, unless otherwise noted. Typical values are at 25°C.

PARAMETER			TEST CONDITIONS		MIN	TYP	MAX	UNIT
Input voltage, V_IN⁽¹⁾					2.7		5.5	V
Internal reference, V_FB (TPS78601)					1.200	1.225	1.250	V
Continuous output current I_OUT					0		1.5	A
Output voltage	Output voltage range	TPS78601			1.225		5.5 – V_DO	V
	Accuracy	TPS78601⁽²⁾	0 μA ≤ I_OUT ≤ 1.5 A, V_OUT + 1 V ≤ V_IN ≤ 5.5 V⁽¹⁾		(0.98)V_OUT	V_OUT	(1.02)V_OUT	V
		Fixed V_OUT < 5 V	0 μA ≤ I_OUT ≤ 1.5 A, V_OUT + 1 V ≤ V_IN ≤ 5.5 V⁽¹⁾		–2%		2%
		Fixed V_OUT = 5 V	0 μA ≤ I_OUT ≤ 1.5 A, V_OUT + 1 V ≤ V_IN ≤ 5.5 V⁽¹⁾		–3%		3%
Output voltage line regulation (ΔV_OUT%/V_IN)⁽¹⁾			V_OUT + 1 V ≤ V_IN ≤ 5.5 V			5	12	%/V
Load regulation (ΔV_OUT%/V_OUT)			0 μA ≤ I_OUT ≤ 1.5 A			7		mV
Dropout voltage⁽³⁾ V_IN = V_OUT(nom) – 0.1 V		TPS78628	I_OUT = 1.5 A			410	580	mV
		TPS78630	I_OUT = 1.5 A			390	550
		TPS78633	I_OUT = 1.5 A			340	510
		TPS78650	I_OUT = 1.5 A			310	470
Output current limit			V_OUT = 0 V		2.4		4.2	A
Ground pin current			0 μA ≤ I_OUT ≤ 1.5 A			260	385	μA
Shutdown current⁽⁴⁾			V_EN = 0 V, 2.7 V ≤ V_IN ≤ 5.5 V			0.07	1	μA
FB pin current			V_FB = 1.225 V				1	μA
Power-supply ripple rejection		TPS78630	f = 100 Hz, I_OUT = 10 mA			59		dB
			f = 100 Hz, I_OUT = 1.5 A			52
			f = 10 kHz, I_OUT = 1.5 A			49
			f = 100 kHz, I_OUT = 1.5 A			32
Output noise voltage (TPS78630)			BW = 100 Hz to 100 kHz, I_OUT = 1.5 A	C_NR = 0.001 μF		66		μV_RMS
				C_NR = 0.0047 μF		51
				C_NR = 0.01 μF		49
				C_NR = 0.1 μF		48
Time, start-up (TPS78630)			R_L = 2 Ω, C_OUT= 1 μF	C_NR = 0.001 μF		50		μs
				C_NR = 0.0047 μF		75
				C_NR = 0.01 μF		110
High-level enable input voltage			2.7 V ≤ V_IN ≤ 5.5 V		1.7		V_IN	V
Low-level enable input voltage			2.7 V ≤ V_IN ≤ 5.5 V		0		0.7	V
EN pin current			V_EN = 0		–1		1	μA
UVLO threshold			V_CC rising		2.25		2.65	V
UVLO hysteresis						100		mV