SLVS348L July   2001  – May 2015 TPS793

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout (UVLO)
      2. 7.3.2 Shutdown
      3. 7.3.3 Foldback Current Limit
      4. 7.3.4 Thermal Protection
      5. 7.3.5 Reverse Current Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjustable Operation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Capacitor Recommendations
        2. 8.2.2.2 Input and Output Capacitor Requirements
        3. 8.2.2.3 Noise Reduction and Feed-Forward Capacitor Requirements
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resource
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 TPS793XXYEQ, YZQ Nanostar Wafer Chip Scale Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted). All voltages are with respect to GND.(1)
MIN MAX UNIT
Voltage Input, VIN –0.3 6 V
Enable, VEN –0.3 6 V
Output, VOUT –0.3 6 V
Current Peak output, IOUT(max) Internally limited A
Output short-circuit duration Indefinite
Total power dissipation Continuous, PD(tot) See Thermal Information
Temperature Junction, TJ DBV package –40 150 °C
YZQ package –40 125 °C
Storage, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted).
MIN NOM MAX UNIT
VIN Input supply voltage range 2.7 5.5 V
VEN Enable supply voltage range 0 VIN V
VOUT Output voltage range VFB 5 V
IOUT Output current 0 200 mA
TJ Operating junction temperature –40 125 °C
CIN Input capacitor 0.1 1 µF
COUT Output capacitor 2.2(1) 10 µF
CNR Noise reduction capacitor 0 10 nF
CFF Feed-forward capacitor 15 pF
R2 Lower feedback resistor 30.1 kΩ
(1) If CFF is not used or VOUT(nom) < 1.8 V, the minimum recommended COUT = 4.7 µF.

6.4 Thermal Information

THERMAL METRIC(1) TPS79301 UNIT
DBV (SOT-23) YZQ (DSBGA)
6 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 225.1 178.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 78.4 1.4 °C/W
RθJB Junction-to-board thermal resistance 54.7 62.1 °C/W
ψJT Junction-to-top characterization parameter 3.3 0.9 °C/W
ψJB Junction-to-board characterization parameter 53.8 62.1 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Over recommended operating temperature range TJ = –40°C to 125°C, VEN = VIN, VIN = VOUT(nom) + 1 V(1), IOUT = 1 mA, COUT = 10 μF, CNR = 0.01 μF (unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range(1) 2.7 5.5 V
IOUT Continuous output current 0 200 mA
VFB Internal reference (TPS79301) 1.201 1.225 1.250 V
VOUT Output voltage range TPS79301 VFB 5.5 – VDO V
TPS79318 0 µA < IOUT < 200 mA, 2.8 V < VIN < 5.5 V 1.764 1.8 1.836
TPS79325 0 µA < IOUT < 200 mA, 3.5 V < VIN < 5.5 V 2.45 2.5 2.55
TPS79328 0 µA < IOUT < 200 mA, 3.8 V < VIN < 5.5 V 2.744 2.8 2.856
TPS793285 0 µA < IOUT < 200 mA, 3.85 V < VIN < 5.5 V 2.793 2.85 2.907
TPS79330 0 µA < IOUT < 200 mA, 4 V < VIN < 5.5 V 2.94 3 3.06
TPS79333 0 µA < IOUT < 200 mA, 4.3 V < VIN < 5.5 V 3.234 3.3 3.366
TPS793475 0 µA < IOUT < 200 mA, 5.25 V < VIN < 5.5 V 4.655 4.75 4.845
ΔVOUT(ΔVIN) Line regulation VOUT + 1 V < VIN ≤ 5.5 V 0.05 0.12 %/V
ΔVOUT(ΔIOUT) Load regulation 0 µA < IOUT < 200 mA, TJ = 25°C 5 mV
VDO Dropout voltage(2)
(VIN = VOUT(nom) – 0.1 V)		 TPS79328 IOUT = 200 mA 120 200 mV
TPS793285 IOUT = 200 mA 120 200
TPS79330 IOUT = 200 mA 112 200
TPS79333 IOUT = 200 mA 12 180
TPS793475 IOUT = 200 mA 77 125
ICL Output current limit VOUT = 0 V 285 600 mA
IGND Ground pin current 0 µA < IOUT < 200 mA 170 220 µA
ISHUTDOWN Shutdown current(3) VEN = 0 V, 2.7 V < VIN < 5.5 V 0.07 1 µA
IFB FB pin current VFB = 1.8 V 1 µA
PSRR Power-supply rejection ratio TPS79328 f = 100 Hz, IOUT = 10 mA 70 dB
f = 100 Hz, IOUT = 200 mA 68
f = 10 kHz, IOUT = 200 mA 70
f = 100 kHz, IOUT = 200 mA 43
Vn Output noise voltage TPS79328 BW = 200 Hz to
100 kHz,
IOUT = 200 mA		 CNR = 0.001 μF 55 µVRMS
CNR = 0.0047 μF 36
CNR = 0.01 μF 33
CNR = 0.1 μF 32
tSTR Startup time TPS79328 RL = 14 Ω,
COUT = 1 µF		 CNR = 0.001 μF 50 µs
CNR = 0.0047 μF 70
CNR = 0.01 μF 100
VEN(high) High-level enable input voltage 2.7 V < VIN < 5.5 V 1.7 VIN V
VEN(low) Low-level enable input voltage 2.7 V < VIN < 5.5 V 0 0.7 V
IEN EN pin current VEN = 0 V –1 1 µA
UVLO Threshold, VCC rising 2.25 2.65 V
Hysteresis 100 mV
(1) Minimum VIN is 2.7 V or VOUT + VDO, whichever is greater.
(2) Dropout is not measured for the TPS79318 and TPS79325 because minimum VIN = 2.7 V.
(3) For adjustable versions, this parameter applies only after VIN is applied; then VEN transitions high to low.

6.6 Typical Characteristics

Over recommended operating temperature range TJ = –40°C to 125°C, VEN = VIN, VIN = VOUT(nom) + 1 V, IOUT = 1 mA, COUT = 10 μF, CNR = 0.01 μF, VOUT(nom) = 2.8 V (unless otherwise noted). Typical values are at TJ = 25°C.
TPS793 VO_v_IO_lvs348.gif
Figure 1. TPS79328 Output Voltage vs Output Current
TPS793 GND_v_TJ_lvs348.gif
Figure 3. TPS79328 Ground Current vs Junction Temperature
TPS793 OSN_CO10_lvs348.gif
Figure 5. TPS79328 Output Spectral Noise Density vs Frequency
TPS793 rms_v_cbyp_lvs348.gif
Figure 7. Root Mean Square Output Noise vs CNR
TPS793 VDO_v_TJ_lvs348.gif
Figure 9. TPS79328 Dropout Voltage vs Junction Temperature
TPS793 RIP2_v_f_lvs348.gif
Figure 11. TPS79328 Ripple Rejection vs Frequency
TPS793 VO_v_time_lvs348.gif
Figure 13. TPS79328 Output Voltage, Enable Voltage vs Time (Start-Up)
TPS793 LoadTR_lvs348.gif
Figure 15. TPS79328 Load Transient Response
TPS793 VDO_v_IO_lvs348.gif
Figure 17. Dropout Voltage vs Output Current
TPS793 ESR1_v_IO_lvs348.gif
Figure 19. Typical Regions of Stability Equivalent Series Resistance (ESR) vs Output Current
TPS793 VO_v_TJ_lvs348.gif
Figure 2. TPS79328 Output Voltage vs Junction Temperature
TPS793 OSN_CO22_lvs348.gif
Figure 4. TPS79328 Output Spectral Noise Density vs Frequency
TPS793 OSN_IO200_lvs348.gif
Figure 6. TPS79328 Output Spectral Noise Density vs Frequency
TPS793 ZO_v_f_lvs348.gif
Figure 8. Output Impedance vs Frequency
TPS793 RIP1_v_f_lvs348.gif
Figure 10. TPS79328 Ripple Rejection vs Frequency
TPS793 RIP3_v_f_lvs348.gif
Figure 12. TPS79328 Ripple Rejection vs Frequency
TPS793 LineTR_lvs348.gif
Figure 14. TPS79328 Line Transient Response
TPS793 Power_plot_lvs348.gif
Figure 16. Power-Up and Power-Down
TPS793 VDO_v_VI_lvs348.gif
Figure 18. TPS79301 Dropout Voltage vs Input Voltage
TPS793 ESR2_v_IO_lvs348.gif
Figure 20. Typical Regions of Stability Equivalent Series Resistance (ESR) vs Output Current