JAJSQI0G
march 2008 – june 2023
TPS799-Q1
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagrams
7.3
Feature Description
7.3.1
Internal Current Limit
7.3.2
Shutdown
7.3.3
Dropout Voltage
7.3.4
Start-Up
7.3.5
Undervoltage Lockout (UVLO)
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Input and Output Capacitor Requirements
8.2.2.2
Feedback Capacitor Requirements (TPS79901-Q1 Only)
8.2.2.3
Output Noise
8.2.2.4
Transient Response
8.2.2.5
Minimum Load
8.2.3
Application Curve
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.1.1
Board Layout Recommendations to Improve PSRR and Noise Performance
8.4.1.2
Thermal Consideration
8.4.1.3
Power Dissipation
8.4.1.4
Package Mounting
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
ドキュメントの更新通知を受け取る方法
9.3
サポート・リソース
9.4
Trademarks
9.5
静電気放電に関する注意事項
9.6
用語集
10
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DDC|5
MPDS123G
DRV|6
MPDS216E
サーマルパッド・メカニカル・データ
DRV|6
QFND087M
発注情報
jajsqi0g_oa
jajsqi0g_pm
8.4.2
Layout Example
Figure 8-4
Layout Example